]> sigrok.org Git - libsigrok.git/blame - src/hardware/rigol-ds/protocol.h
Build: Set local include directories in Makefile.am
[libsigrok.git] / src / hardware / rigol-ds / protocol.h
CommitLineData
f4816ac6
ML
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
88e429c9 5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
f4816ac6
ML
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
3086efdd
ML
21#ifndef LIBSIGROK_HARDWARE_RIGOL_DS_PROTOCOL_H
22#define LIBSIGROK_HARDWARE_RIGOL_DS_PROTOCOL_H
f4816ac6
ML
23
24#include <stdint.h>
bafd4890 25#include <stdbool.h>
c1aae900 26#include <libsigrok/libsigrok.h>
f4816ac6
ML
27#include "libsigrok-internal.h"
28
3544f848 29#define LOG_PREFIX "rigol-ds"
f4816ac6 30
babab622 31/* Size of acquisition buffers */
1a46cc62 32#define ACQ_BUFFER_SIZE (32 * 1024)
babab622 33
702f42e8 34/* Maximum number of samples to retrieve at once. */
1a46cc62 35#define ACQ_BLOCK_SIZE (30 * 1000)
702f42e8 36
3f239f08
UH
37#define MAX_ANALOG_CHANNELS 4
38#define MAX_DIGITAL_CHANNELS 16
821fbcad 39
569d4dbd
ML
40enum protocol_version {
41 PROTOCOL_V1, /* VS5000 */
42 PROTOCOL_V2, /* DS1000 */
43 PROTOCOL_V3, /* DS2000, DSO1000 */
702f42e8 44 PROTOCOL_V4, /* DS1000Z */
babab622
ML
45};
46
569d4dbd
ML
47enum data_format {
48 /* Used by DS1000 versions up to 2.02, and VS5000 series */
49 FORMAT_RAW,
50 /* Used by DS1000 versions from 2.04 onwards and all later series */
51 FORMAT_IEEE488_2,
babab622
ML
52};
53
54enum data_source {
55 DATA_SOURCE_LIVE,
56 DATA_SOURCE_MEMORY,
57 DATA_SOURCE_SEGMENTED,
58};
e0b7d23c 59
569d4dbd
ML
60struct rigol_ds_vendor {
61 const char *name;
62 const char *full_name;
63};
64
65struct rigol_ds_series {
66 const struct rigol_ds_vendor *vendor;
67 const char *name;
68 enum protocol_version protocol;
69 enum data_format format;
bafd4890
ML
70 uint64_t max_timebase[2];
71 uint64_t min_vdiv[2];
569d4dbd
ML
72 int num_horizontal_divs;
73 int live_samples;
74 int buffer_samples;
75};
76
77struct rigol_ds_model {
78 const struct rigol_ds_series *series;
79 const char *name;
80 uint64_t min_timebase[2];
821fbcad 81 unsigned int analog_channels;
bafd4890 82 bool has_digital;
babab622
ML
83};
84
85enum wait_events {
86 WAIT_NONE, /* Don't wait */
87 WAIT_TRIGGER, /* Wait for trigger (only live capture) */
88 WAIT_BLOCK, /* Wait for block data (only when reading sample mem) */
89 WAIT_STOP, /* Wait for scope stopping (only single shots) */
bafd4890
ML
90};
91
f4816ac6
ML
92/** Private, per-device-instance driver context. */
93struct dev_context {
bafd4890
ML
94 /* Device model */
95 const struct rigol_ds_model *model;
569d4dbd 96 enum data_format format;
bafd4890
ML
97
98 /* Device properties */
99 const uint64_t (*timebases)[2];
100 uint64_t num_timebases;
101 const uint64_t (*vdivs)[2];
102 uint64_t num_vdivs;
6bb192bc 103
660e398f 104 /* Channel groups */
562b7ae5
SA
105 struct sr_channel_group **analog_groups;
106 struct sr_channel_group *digital_group;
3d3a601e 107
254dd102 108 /* Acquisition settings */
702f42e8 109 GSList *enabled_channels;
e0b7d23c 110 uint64_t limit_frames;
f4816ac6 111 void *cb_data;
babab622
ML
112 enum data_source data_source;
113 uint64_t analog_frame_size;
d22250a9 114 uint64_t digital_frame_size;
f4816ac6 115
254dd102 116 /* Device settings */
3f239f08
UH
117 gboolean analog_channels[MAX_ANALOG_CHANNELS];
118 gboolean digital_channels[MAX_DIGITAL_CHANNELS];
04e8e01e 119 gboolean la_enabled;
254dd102 120 float timebase;
3f239f08
UH
121 float vdiv[MAX_ANALOG_CHANNELS];
122 int vert_reference[MAX_ANALOG_CHANNELS];
123 float vert_offset[MAX_ANALOG_CHANNELS];
254dd102
BV
124 char *trigger_source;
125 float horiz_triggerpos;
126 char *trigger_slope;
3f239f08 127 char *coupling[MAX_ANALOG_CHANNELS];
254dd102
BV
128
129 /* Operational state */
0d87bd93
ML
130
131 /* Number of frames received in total. */
254dd102 132 uint64_t num_frames;
821fbcad
ML
133 /* GSList entry for the current channel. */
134 GSList *channel_entry;
f76c24f6
ML
135 /* Number of bytes received for current channel. */
136 uint64_t num_channel_bytes;
aff00e40
ML
137 /* Number of bytes of block header read */
138 uint64_t num_header_bytes;
bafd4890
ML
139 /* Number of bytes in current data block, if 0 block header expected */
140 uint64_t num_block_bytes;
141 /* Number of data block bytes already read */
142 uint64_t num_block_read;
babab622
ML
143 /* What to wait for in *_receive */
144 enum wait_events wait_event;
145 /* Trigger/block copying/stop waiting status */
146 int wait_status;
147 /* Acq buffers used for reading from the scope and sending data to app */
148 unsigned char *buffer;
149 float *data;
f4816ac6
ML
150};
151
38354d9d 152SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...);
babab622 153SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi);
677f85d0 154SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi);
3086efdd 155SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data);
3086efdd 156SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi);
e0b7d23c 157
f4816ac6 158#endif