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[libsigrok.git] / src / hardware / openbench-logic-sniffer / protocol.c
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0aba65da 1/*
50985c20 2 * This file is part of the libsigrok project.
0aba65da 3 *
13d8e03c 4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
515ab088 21#include "protocol.h"
0aba65da 22
f8fd8420 23struct ols_basic_trigger_desc {
24 uint32_t trigger_mask[NUM_BASIC_TRIGGER_STAGES];
25 uint32_t trigger_value[NUM_BASIC_TRIGGER_STAGES];
26 int num_stages;
27};
28
0aba65da 29SR_PRIV int send_shortcommand(struct sr_serial_dev_inst *serial,
55eca716 30 uint8_t command)
0aba65da
UH
31{
32 char buf[1];
33
34 sr_dbg("Sending cmd 0x%.2x.", command);
35 buf[0] = command;
f4d3a4fb 36 if (serial_write_blocking(serial, buf, 1, serial_timeout(serial, 1)) != 1)
0aba65da
UH
37 return SR_ERR;
38
dcdc2848 39 if (serial_drain(serial) != SR_OK)
bce75f94
UJ
40 return SR_ERR;
41
0aba65da
UH
42 return SR_OK;
43}
44
55eca716 45SR_PRIV int send_longcommand(struct sr_serial_dev_inst *serial, uint8_t command,
46 uint8_t *data)
0aba65da
UH
47{
48 char buf[5];
49
55eca716 50 sr_dbg("Sending cmd 0x%.2x data 0x%.2x%.2x%.2x%.2x.", command, data[0],
51 data[1], data[2], data[3]);
0aba65da 52 buf[0] = command;
016e72f3
BV
53 buf[1] = data[0];
54 buf[2] = data[1];
55 buf[3] = data[2];
56 buf[4] = data[3];
f4d3a4fb 57 if (serial_write_blocking(serial, buf, 5, serial_timeout(serial, 1)) != 5)
0aba65da
UH
58 return SR_ERR;
59
dcdc2848 60 if (serial_drain(serial) != SR_OK)
bce75f94
UJ
61 return SR_ERR;
62
0aba65da
UH
63 return SR_OK;
64}
65
55eca716 66static int ols_send_longdata(struct sr_serial_dev_inst *serial, uint8_t command,
67 uint32_t value)
3cc9e215 68{
69 uint8_t data[4];
70 WL32(data, value);
71 return send_longcommand(serial, command, data);
72}
73
244995a2
GGM
74SR_PRIV int ols_send_reset(struct sr_serial_dev_inst *serial)
75{
76 unsigned int i;
77
78 for (i = 0; i < 5; i++) {
79 if (send_shortcommand(serial, CMD_RESET) != SR_OK)
80 return SR_ERR;
81 }
82
83 return SR_OK;
84}
85
91fd0f72 86/* Configures the channel mask based on which channels are enabled. */
f8fd8420 87SR_PRIV uint32_t ols_channel_mask(const struct sr_dev_inst *sdi)
0aba65da 88{
f8fd8420 89 uint32_t channel_mask = 0;
90 for (const GSList *l = sdi->channels; l; l = l->next) {
91 struct sr_channel *channel = l->data;
91fd0f72 92 if (channel->enabled)
f8fd8420 93 channel_mask |= 1 << channel->index;
91fd0f72 94 }
f8fd8420 95
96 return channel_mask;
91fd0f72
BV
97}
98
55eca716 99static int convert_trigger(const struct sr_dev_inst *sdi,
100 struct ols_basic_trigger_desc *ols_trigger)
91fd0f72 101{
91fd0f72
BV
102 struct sr_trigger *trigger;
103 struct sr_trigger_stage *stage;
104 struct sr_trigger_match *match;
105 const GSList *l, *m;
106 int i;
107
f8fd8420 108 ols_trigger->num_stages = 0;
109 for (i = 0; i < NUM_BASIC_TRIGGER_STAGES; i++) {
110 ols_trigger->trigger_mask[i] = 0;
111 ols_trigger->trigger_value[i] = 0;
0aba65da
UH
112 }
113
0812c40e 114 if (!(trigger = sr_session_trigger_get(sdi->session)))
91fd0f72 115 return SR_OK;
0aba65da 116
f8fd8420 117 ols_trigger->num_stages = g_slist_length(trigger->stages);
118 if (ols_trigger->num_stages > NUM_BASIC_TRIGGER_STAGES) {
91fd0f72 119 sr_err("This device only supports %d trigger stages.",
55eca716 120 NUM_BASIC_TRIGGER_STAGES);
91fd0f72
BV
121 return SR_ERR;
122 }
b1de0407 123
91fd0f72
BV
124 for (l = trigger->stages; l; l = l->next) {
125 stage = l->data;
126 for (m = stage->matches; m; m = m->next) {
127 match = m->data;
128 if (!match->channel->enabled)
129 /* Ignore disabled channels with a trigger. */
130 continue;
55eca716 131 ols_trigger->trigger_mask[stage->stage] |=
132 1 << match->channel->index;
91fd0f72 133 if (match->match == SR_TRIGGER_ONE)
55eca716 134 ols_trigger->trigger_value[stage->stage] |=
135 1 << match->channel->index;
0aba65da 136 }
0aba65da
UH
137 }
138
139 return SR_OK;
140}
141
aad6b9de 142static void ols_metadata_quirks(struct sr_dev_inst *sdi)
ad4174c1
GS
143{
144 struct dev_context *devc;
145 gboolean is_shrimp;
146
147 if (!sdi)
148 return;
149 devc = sdi->priv;
150 if (!devc)
151 return;
152
153 is_shrimp = sdi->model && strcmp(sdi->model, "Shrimp1.0") == 0;
154 if (is_shrimp) {
155 if (!devc->max_channels)
fbf9e657 156 devc->max_channels = 4;
ad4174c1
GS
157 if (!devc->max_samples)
158 devc->max_samples = 256 * 1024;
159 if (!devc->max_samplerate)
160 devc->max_samplerate = SR_MHZ(20);
161 }
6f9234e6 162
163 if (sdi->version && strstr(sdi->version, "FPGA version 3.07"))
164 devc->device_flags |= DEVICE_FLAG_IS_DEMON_CORE;
ad4174c1
GS
165}
166
838f0122 167SR_PRIV int ols_get_metadata(struct sr_dev_inst *sdi)
0aba65da 168{
838f0122 169 struct sr_serial_dev_inst *serial;
0aba65da 170 struct dev_context *devc;
4a34a74d 171 uint32_t tmp_int;
6f9234e6 172 uint8_t key, type;
f4d3a4fb 173 int delay_ms;
0aba65da
UH
174 GString *tmp_str, *devname, *version;
175 guchar tmp_c;
176
838f0122
GS
177 serial = sdi->conn;
178 devc = sdi->priv;
0aba65da
UH
179
180 devname = g_string_new("");
181 version = g_string_new("");
182
183 key = 0xff;
184 while (key) {
f4d3a4fb
BV
185 delay_ms = serial_timeout(serial, 1);
186 if (serial_read_blocking(serial, &key, 1, delay_ms) != 1)
0aba65da 187 break;
6f9234e6 188 if (key == METADATA_TOKEN_END) {
625763e2
BV
189 sr_dbg("Got metadata key 0x00, metadata ends.");
190 break;
191 }
0aba65da 192 type = key >> 5;
0aba65da
UH
193 switch (type) {
194 case 0:
195 /* NULL-terminated string */
196 tmp_str = g_string_new("");
f4d3a4fb 197 delay_ms = serial_timeout(serial, 1);
55eca716 198 while (serial_read_blocking(serial, &tmp_c, 1,
199 delay_ms) == 1 &&
200 tmp_c != '\0')
0aba65da 201 g_string_append_c(tmp_str, tmp_c);
55eca716 202 sr_dbg("Got metadata token 0x%.2x value '%s'.", key,
203 tmp_str->str);
6f9234e6 204 switch (key) {
205 case METADATA_TOKEN_DEVICE_NAME:
0aba65da 206 /* Device name */
55eca716 207 devname =
208 g_string_append(devname, tmp_str->str);
0aba65da 209 break;
6f9234e6 210 case METADATA_TOKEN_FPGA_VERSION:
0aba65da
UH
211 /* FPGA firmware version */
212 if (version->len)
213 g_string_append(version, ", ");
214 g_string_append(version, "FPGA version ");
215 g_string_append(version, tmp_str->str);
216 break;
6f9234e6 217 case METADATA_TOKEN_ANCILLARY_VERSION:
0aba65da
UH
218 /* Ancillary version */
219 if (version->len)
220 g_string_append(version, ", ");
221 g_string_append(version, "Ancillary version ");
222 g_string_append(version, tmp_str->str);
223 break;
224 default:
55eca716 225 sr_info("ols: unknown token 0x%.2x: '%s'", key,
226 tmp_str->str);
0aba65da
UH
227 break;
228 }
229 g_string_free(tmp_str, TRUE);
230 break;
231 case 1:
232 /* 32-bit unsigned integer */
f4d3a4fb 233 delay_ms = serial_timeout(serial, 4);
55eca716 234 if (serial_read_blocking(serial, &tmp_int, 4,
235 delay_ms) != 4)
0aba65da 236 break;
016e72f3 237 tmp_int = RB32(&tmp_int);
55eca716 238 sr_dbg("Got metadata token 0x%.2x value 0x%.8x.", key,
239 tmp_int);
6f9234e6 240 switch (key) {
241 case METADATA_TOKEN_NUM_PROBES_LONG:
ba7dd8bb 242 /* Number of usable channels */
fbf9e657 243 devc->max_channels = tmp_int;
0aba65da 244 break;
6f9234e6 245 case METADATA_TOKEN_SAMPLE_MEMORY_BYTES:
0aba65da
UH
246 /* Amount of sample memory available (bytes) */
247 devc->max_samples = tmp_int;
248 break;
6f9234e6 249 case METADATA_TOKEN_DYNAMIC_MEMORY_BYTES:
0aba65da
UH
250 /* Amount of dynamic memory available (bytes) */
251 /* what is this for? */
252 break;
6f9234e6 253 case METADATA_TOKEN_MAX_SAMPLE_RATE_HZ:
f3f19d11 254 /* Maximum sample rate (Hz) */
0aba65da
UH
255 devc->max_samplerate = tmp_int;
256 break;
6f9234e6 257 case METADATA_TOKEN_PROTOCOL_VERSION_LONG:
0aba65da
UH
258 /* protocol version */
259 devc->protocol_version = tmp_int;
260 break;
261 default:
55eca716 262 sr_info("Unknown token 0x%.2x: 0x%.8x.", key,
263 tmp_int);
0aba65da
UH
264 break;
265 }
266 break;
267 case 2:
268 /* 8-bit unsigned integer */
f4d3a4fb
BV
269 delay_ms = serial_timeout(serial, 1);
270 if (serial_read_blocking(serial, &tmp_c, 1, delay_ms) != 1)
0aba65da 271 break;
55eca716 272 sr_dbg("Got metadata token 0x%.2x value 0x%.2x.", key,
273 tmp_c);
6f9234e6 274 switch (key) {
275 case METADATA_TOKEN_NUM_PROBES_SHORT:
ba7dd8bb 276 /* Number of usable channels */
fbf9e657 277 devc->max_channels = tmp_c;
0aba65da 278 break;
6f9234e6 279 case METADATA_TOKEN_PROTOCOL_VERSION_SHORT:
0aba65da
UH
280 /* protocol version */
281 devc->protocol_version = tmp_c;
282 break;
283 default:
55eca716 284 sr_info("Unknown token 0x%.2x: 0x%.2x.", key,
285 tmp_c);
0aba65da
UH
286 break;
287 }
288 break;
289 default:
290 /* unknown type */
291 break;
292 }
293 }
294
295 sdi->model = devname->str;
296 sdi->version = version->str;
297 g_string_free(devname, FALSE);
298 g_string_free(version, FALSE);
299
ad4174c1 300 /* Optionally amend received metadata, model specific quirks. */
aad6b9de 301 ols_metadata_quirks(sdi);
ad4174c1 302
838f0122 303 return SR_OK;
0aba65da
UH
304}
305
306SR_PRIV int ols_set_samplerate(const struct sr_dev_inst *sdi,
55eca716 307 const uint64_t samplerate)
0aba65da
UH
308{
309 struct dev_context *devc;
310
311 devc = sdi->priv;
e46aa4f6 312 if (devc->max_samplerate && samplerate > devc->max_samplerate)
0aba65da
UH
313 return SR_ERR_SAMPLERATE;
314
315 if (samplerate > CLOCK_RATE) {
6ebe0039 316 sr_info("Enabling demux mode.");
a80bed76 317 devc->capture_flags |= CAPTURE_FLAG_DEMUX;
318 devc->capture_flags &= ~CAPTURE_FLAG_NOISE_FILTER;
55eca716 319 devc->cur_samplerate_divider =
320 (CLOCK_RATE * 2 / samplerate) - 1;
0aba65da 321 } else {
6ebe0039 322 sr_info("Disabling demux mode.");
a80bed76 323 devc->capture_flags &= ~CAPTURE_FLAG_DEMUX;
324 devc->capture_flags |= CAPTURE_FLAG_NOISE_FILTER;
0aba65da
UH
325 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
326 }
327
328 /* Calculate actual samplerate used and complain if it is different
329 * from the requested.
330 */
331 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
a80bed76 332 if (devc->capture_flags & CAPTURE_FLAG_DEMUX)
0aba65da
UH
333 devc->cur_samplerate *= 2;
334 if (devc->cur_samplerate != samplerate)
55eca716 335 sr_info("Can't match samplerate %" PRIu64 ", using %" PRIu64
336 ".",
337 samplerate, devc->cur_samplerate);
0aba65da
UH
338
339 return SR_OK;
340}
341
342SR_PRIV void abort_acquisition(const struct sr_dev_inst *sdi)
343{
459a0f26 344 struct sr_serial_dev_inst *serial;
0aba65da 345
459a0f26 346 serial = sdi->conn;
7dd1dd9f 347 ols_send_reset(serial);
6d8182b6 348
102f1239 349 serial_source_remove(sdi->session, serial);
0aba65da 350
bee2b016 351 std_session_send_df_end(sdi);
0aba65da
UH
352}
353
354SR_PRIV int ols_receive_data(int fd, int revents, void *cb_data)
355{
459a0f26 356 struct dev_context *devc;
625763e2 357 struct sr_dev_inst *sdi;
459a0f26 358 struct sr_serial_dev_inst *serial;
0aba65da
UH
359 struct sr_datafeed_packet packet;
360 struct sr_datafeed_logic logic;
fe9ac252 361 uint32_t sample;
f8fd8420 362 int num_changroups, offset, j;
b1de0407 363 unsigned int i;
0aba65da 364 unsigned char byte;
625763e2
BV
365
366 (void)fd;
367
368 sdi = cb_data;
369 serial = sdi->conn;
370 devc = sdi->priv;
0aba65da 371
8105e829
DE
372 if (devc->num_transfers == 0 && revents == 0) {
373 /* Ignore timeouts as long as we haven't received anything */
374 return TRUE;
375 }
376
0aba65da 377 if (devc->num_transfers++ == 0) {
0aba65da
UH
378 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
379 if (!devc->raw_sample_buf) {
380 sr_err("Sample buffer malloc failed.");
381 return FALSE;
382 }
383 /* fill with 1010... for debugging */
384 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
385 }
386
f8fd8420 387 num_changroups = 0;
be15c51e 388 for (i = 0x20; i > 0x02; i >>= 1) {
a80bed76 389 if ((devc->capture_flags & i) == 0) {
f8fd8420 390 num_changroups++;
f51acd69 391 }
0aba65da
UH
392 }
393
faf72024 394 if (revents == G_IO_IN && devc->num_samples < devc->limit_samples) {
9f5d4c3c 395 if (serial_read_nonblocking(serial, &byte, 1) != 1)
0aba65da 396 return FALSE;
625763e2 397 devc->cnt_bytes++;
0aba65da
UH
398
399 /* Ignore it if we've read enough. */
400 if (devc->num_samples >= devc->limit_samples)
401 return TRUE;
402
403 devc->sample[devc->num_bytes++] = byte;
6d16fdfb 404 sr_spew("Received byte 0x%.2x.", byte);
f8fd8420 405 if (devc->num_bytes == num_changroups) {
625763e2
BV
406 devc->cnt_samples++;
407 devc->cnt_samples_rle++;
408 /*
409 * Got a full sample. Convert from the OLS's little-endian
410 * sample to the local format.
411 */
55eca716 412 sample = devc->sample[0] | (devc->sample[1] << 8) |
413 (devc->sample[2] << 16) |
414 (devc->sample[3] << 24);
415 sr_dbg("Received sample 0x%.*x.", devc->num_bytes * 2,
416 sample);
a80bed76 417 if (devc->capture_flags & CAPTURE_FLAG_RLE) {
0aba65da 418 /*
00d04d3b
BV
419 * In RLE mode the high bit of the sample is the
420 * "count" flag, meaning this sample is the number
421 * of times the previous sample occurred.
0aba65da
UH
422 */
423 if (devc->sample[devc->num_bytes - 1] & 0x80) {
00d04d3b 424 /* Clear the high bit. */
55eca716 425 sample &= ~(0x80 << (devc->num_bytes -
426 1) * 8);
fe9ac252 427 devc->rle_count = sample;
55eca716 428 devc->cnt_samples_rle +=
429 devc->rle_count;
430 sr_dbg("RLE count: %u.",
431 devc->rle_count);
0aba65da
UH
432 devc->num_bytes = 0;
433 return TRUE;
434 }
435 }
436 devc->num_samples += devc->rle_count + 1;
437 if (devc->num_samples > devc->limit_samples) {
438 /* Save us from overrunning the buffer. */
55eca716 439 devc->rle_count -=
440 devc->num_samples - devc->limit_samples;
0aba65da
UH
441 devc->num_samples = devc->limit_samples;
442 }
443
f8fd8420 444 if (num_changroups < 4) {
0aba65da
UH
445 /*
446 * Some channel groups may have been turned
447 * off, to speed up transfer between the
448 * hardware and the PC. Expand that here before
449 * submitting it over the session bus --
450 * whatever is listening on the bus will be
451 * expecting a full 32-bit sample, based on
ba7dd8bb 452 * the number of channels.
0aba65da
UH
453 */
454 j = 0;
cfe55d09 455 uint8_t tmp_sample[4] = { 0, 0, 0, 0 };
0aba65da 456 for (i = 0; i < 4; i++) {
55eca716 457 if (((devc->capture_flags >> 2) &
458 (1 << i)) == 0) {
0aba65da
UH
459 /*
460 * This channel group was
461 * enabled, copy from received
462 * sample.
463 */
cfe55d09 464 tmp_sample[i] =
55eca716 465 devc->sample[j++];
0aba65da
UH
466 }
467 }
cfe55d09 468 memcpy(devc->sample, tmp_sample, 4);
29f15d52 469 sr_spew("Expanded sample: 0x%.2hhx%.2hhx%.2hhx%.2hhx ",
55eca716 470 devc->sample[3], devc->sample[2],
471 devc->sample[1], devc->sample[0]);
0aba65da
UH
472 }
473
625763e2
BV
474 /*
475 * the OLS sends its sample buffer backwards.
0aba65da
UH
476 * store it in reverse order here, so we can dump
477 * this on the session bus later.
478 */
479 offset = (devc->limit_samples - devc->num_samples) * 4;
480 for (i = 0; i <= devc->rle_count; i++) {
481 memcpy(devc->raw_sample_buf + offset + (i * 4),
482 devc->sample, 4);
483 }
484 memset(devc->sample, 0, 4);
485 devc->num_bytes = 0;
486 devc->rle_count = 0;
487 }
488 } else {
489 /*
490 * This is the main loop telling us a timeout was reached, or
491 * we've acquired all the samples we asked for -- we're done.
492 * Send the (properly-ordered) buffer to the frontend.
493 */
625763e2 494 sr_dbg("Received %d bytes, %d samples, %d decompressed samples.",
55eca716 495 devc->cnt_bytes, devc->cnt_samples,
496 devc->cnt_samples_rle);
a2b1a53b 497 if (devc->trigger_at_smpl != OLS_NO_TRIGGER) {
625763e2
BV
498 /*
499 * A trigger was set up, so we need to tell the frontend
0aba65da
UH
500 * about it.
501 */
a2b1a53b 502 if (devc->trigger_at_smpl > 0) {
625763e2 503 /* There are pre-trigger samples, send those first. */
0aba65da
UH
504 packet.type = SR_DF_LOGIC;
505 packet.payload = &logic;
a2b1a53b 506 logic.length = devc->trigger_at_smpl * 4;
0aba65da
UH
507 logic.unitsize = 4;
508 logic.data = devc->raw_sample_buf +
55eca716 509 (devc->limit_samples -
510 devc->num_samples) *
511 4;
695dc859 512 sr_session_send(sdi, &packet);
0aba65da
UH
513 }
514
625763e2 515 /* Send the trigger. */
0fa71943 516 std_session_send_df_trigger(sdi);
0aba65da 517 }
2755ab36 518
519 /* Send post-trigger / all captured samples. */
55eca716 520 int num_pre_trigger_samples = devc->trigger_at_smpl ==
521 OLS_NO_TRIGGER ?
522 0 :
523 devc->trigger_at_smpl;
2755ab36 524 packet.type = SR_DF_LOGIC;
525 packet.payload = &logic;
55eca716 526 logic.length =
527 (devc->num_samples - num_pre_trigger_samples) * 4;
2755ab36 528 logic.unitsize = 4;
55eca716 529 logic.data = devc->raw_sample_buf +
530 (num_pre_trigger_samples + devc->limit_samples -
531 devc->num_samples) *
532 4;
2755ab36 533 sr_session_send(sdi, &packet);
534
0aba65da
UH
535 g_free(devc->raw_sample_buf);
536
459a0f26 537 serial_flush(serial);
0aba65da 538 abort_acquisition(sdi);
0aba65da
UH
539 }
540
541 return TRUE;
542}
f8fd8420 543
55eca716 544static int
545ols_set_basic_trigger_stage(const struct ols_basic_trigger_desc *trigger_desc,
546 struct sr_serial_dev_inst *serial, int stage)
f8fd8420 547{
548 uint8_t cmd, arg[4];
549
550 cmd = CMD_SET_BASIC_TRIGGER_MASK0 + stage * 4;
3cc9e215 551 if (ols_send_longdata(serial, cmd, trigger_desc->trigger_mask[stage]) != SR_OK)
f8fd8420 552 return SR_ERR;
553
554 cmd = CMD_SET_BASIC_TRIGGER_VALUE0 + stage * 4;
3cc9e215 555 if (ols_send_longdata(serial, cmd, trigger_desc->trigger_value[stage]) != SR_OK)
f8fd8420 556 return SR_ERR;
557
558 cmd = CMD_SET_BASIC_TRIGGER_CONFIG0 + stage * 4;
559 arg[0] = arg[1] = arg[3] = 0x00;
560 arg[2] = stage;
b28e391a 561 if (stage == trigger_desc->num_stages - 1)
f8fd8420 562 /* Last stage, fire when this one matches. */
563 arg[3] |= TRIGGER_START;
564 if (send_longcommand(serial, cmd, arg) != SR_OK)
565 return SR_ERR;
566
567 return SR_OK;
568}
569
55eca716 570SR_PRIV int ols_prepare_acquisition(const struct sr_dev_inst *sdi)
571{
f8fd8420 572 int ret;
f8fd8420 573
574 struct dev_context *devc = sdi->priv;
575 struct sr_serial_dev_inst *serial = sdi->conn;
576
577 int num_changroups = 0;
578 uint8_t changroup_mask = 0;
579 uint32_t channel_mask = ols_channel_mask(sdi);
580 for (unsigned int i = 0; i < 4; i++) {
581 if (channel_mask & (0xff << (i * 8))) {
582 changroup_mask |= (1 << i);
583 num_changroups++;
584 }
585 }
586
587 /*
588 * Limit readcount to prevent reading past the end of the hardware
589 * buffer. Rather read too many samples than too few.
590 */
55eca716 591 uint32_t samplecount =
592 MIN(devc->max_samples / num_changroups, devc->limit_samples);
f8fd8420 593 uint32_t readcount = (samplecount + 3) / 4;
594 uint32_t delaycount;
595
596 /* Basic triggers. */
597 struct ols_basic_trigger_desc basic_trigger_desc;
598 if (convert_trigger(sdi, &basic_trigger_desc) != SR_OK) {
599 sr_err("Failed to configure channels.");
600 return SR_ERR;
601 }
602 if (basic_trigger_desc.num_stages > 0) {
603 /*
604 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
605 * reset command must be send prior each arm command
606 */
607 sr_dbg("Send reset command before trigger configure");
608 if (ols_send_reset(serial) != SR_OK)
609 return SR_ERR;
610
611 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
55eca716 612 devc->trigger_at_smpl = (readcount - delaycount) * 4 -
613 basic_trigger_desc.num_stages;
b28e391a 614 for (int i = 0; i < basic_trigger_desc.num_stages; i++) {
f8fd8420 615 sr_dbg("Setting OLS stage %d trigger.", i);
55eca716 616 if ((ret = ols_set_basic_trigger_stage(
617 &basic_trigger_desc, serial, i)) != SR_OK)
f8fd8420 618 return ret;
619 }
620 } else {
621 /* No triggers configured, force trigger on first stage. */
622 sr_dbg("Forcing trigger at stage 0.");
b28e391a 623 basic_trigger_desc.num_stages = 1;
55eca716 624 if ((ret = ols_set_basic_trigger_stage(&basic_trigger_desc,
625 serial, 0)) != SR_OK)
f8fd8420 626 return ret;
627 delaycount = readcount;
628 }
629
630 /* Samplerate. */
631 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
55eca716 632 devc->cur_samplerate, devc->cur_samplerate_divider);
633 if (ols_send_longdata(serial, CMD_SET_DIVIDER,
634 devc->cur_samplerate_divider & 0x00FFFFFF) != SR_OK)
f8fd8420 635 return SR_ERR;
636
637 /* Send sample limit and pre/post-trigger capture ratio. */
638 sr_dbg("Setting sample limit %d, trigger point at %d",
55eca716 639 (readcount - 1) * 4, (delaycount - 1) * 4);
f8fd8420 640
641 if (devc->max_samples > 256 * 1024) {
55eca716 642 if (ols_send_longdata(serial, CMD_CAPTURE_READCOUNT,
643 readcount - 1) != SR_OK)
f8fd8420 644 return SR_ERR;
55eca716 645 if (ols_send_longdata(serial, CMD_CAPTURE_DELAYCOUNT,
646 delaycount - 1) != SR_OK)
f8fd8420 647 return SR_ERR;
648 } else {
3cc9e215 649 uint8_t arg[4];
55eca716 650 WL16(&arg[0], readcount - 1);
651 WL16(&arg[2], delaycount - 1);
f8fd8420 652 if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
653 return SR_ERR;
654 }
655
656 /* Flag register. */
55eca716 657 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s, "
658 "%s clock%s",
659 devc->capture_flags & CAPTURE_FLAG_INTERNAL_TEST_MODE ? "on" :
660 "off",
661 devc->capture_flags & CAPTURE_FLAG_EXTERNAL_TEST_MODE ? "on" :
662 "off",
663 devc->capture_flags & CAPTURE_FLAG_RLE ? "on" : "off",
664 devc->capture_flags & CAPTURE_FLAG_NOISE_FILTER ? "on" : "off",
665 devc->capture_flags & CAPTURE_FLAG_DEMUX ? "on" : "off",
666 devc->capture_flags & CAPTURE_FLAG_CLOCK_EXTERNAL ? "external" :
667 "internal",
668 devc->capture_flags & CAPTURE_FLAG_CLOCK_EXTERNAL ?
669 (devc->capture_flags & CAPTURE_FLAG_INVERT_EXT_CLOCK ?
670 " on falling edge" :
671 "on rising edge") :
672 "");
f8fd8420 673
674 /*
675 * Enable/disable OLS channel groups in the flag register according
676 * to the channel mask. 1 means "disable channel".
677 */
678 devc->capture_flags &= ~0x3c;
679 devc->capture_flags |= ~(changroup_mask << 2) & 0x3c;
680
681 /* RLE mode is always zero, for now. */
682
3cc9e215 683 if (ols_send_longdata(serial, CMD_SET_FLAGS, devc->capture_flags) != SR_OK)
f8fd8420 684 return SR_ERR;
685
686 return SR_OK;
687}