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ols: move device context creation from protocol.c to api.c
[libsigrok.git] / src / hardware / openbench-logic-sniffer / protocol.c
CommitLineData
0aba65da 1/*
50985c20 2 * This file is part of the libsigrok project.
0aba65da 3 *
13d8e03c 4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
515ab088 21#include "protocol.h"
0aba65da 22
f8fd8420 23struct ols_basic_trigger_desc {
24 uint32_t trigger_mask[NUM_BASIC_TRIGGER_STAGES];
25 uint32_t trigger_value[NUM_BASIC_TRIGGER_STAGES];
26 int num_stages;
27};
28
0aba65da 29SR_PRIV int send_shortcommand(struct sr_serial_dev_inst *serial,
55eca716 30 uint8_t command)
0aba65da
UH
31{
32 char buf[1];
33
34 sr_dbg("Sending cmd 0x%.2x.", command);
35 buf[0] = command;
f4d3a4fb 36 if (serial_write_blocking(serial, buf, 1, serial_timeout(serial, 1)) != 1)
0aba65da
UH
37 return SR_ERR;
38
dcdc2848 39 if (serial_drain(serial) != SR_OK)
bce75f94
UJ
40 return SR_ERR;
41
0aba65da
UH
42 return SR_OK;
43}
44
55eca716 45SR_PRIV int send_longcommand(struct sr_serial_dev_inst *serial, uint8_t command,
46 uint8_t *data)
0aba65da
UH
47{
48 char buf[5];
49
55eca716 50 sr_dbg("Sending cmd 0x%.2x data 0x%.2x%.2x%.2x%.2x.", command, data[0],
51 data[1], data[2], data[3]);
0aba65da 52 buf[0] = command;
016e72f3
BV
53 buf[1] = data[0];
54 buf[2] = data[1];
55 buf[3] = data[2];
56 buf[4] = data[3];
f4d3a4fb 57 if (serial_write_blocking(serial, buf, 5, serial_timeout(serial, 1)) != 5)
0aba65da
UH
58 return SR_ERR;
59
dcdc2848 60 if (serial_drain(serial) != SR_OK)
bce75f94
UJ
61 return SR_ERR;
62
0aba65da
UH
63 return SR_OK;
64}
65
55eca716 66static int ols_send_longdata(struct sr_serial_dev_inst *serial, uint8_t command,
67 uint32_t value)
3cc9e215 68{
69 uint8_t data[4];
70 WL32(data, value);
71 return send_longcommand(serial, command, data);
72}
73
244995a2
GGM
74SR_PRIV int ols_send_reset(struct sr_serial_dev_inst *serial)
75{
76 unsigned int i;
77
78 for (i = 0; i < 5; i++) {
79 if (send_shortcommand(serial, CMD_RESET) != SR_OK)
80 return SR_ERR;
81 }
82
83 return SR_OK;
84}
85
91fd0f72 86/* Configures the channel mask based on which channels are enabled. */
f8fd8420 87SR_PRIV uint32_t ols_channel_mask(const struct sr_dev_inst *sdi)
0aba65da 88{
f8fd8420 89 uint32_t channel_mask = 0;
90 for (const GSList *l = sdi->channels; l; l = l->next) {
91 struct sr_channel *channel = l->data;
91fd0f72 92 if (channel->enabled)
f8fd8420 93 channel_mask |= 1 << channel->index;
91fd0f72 94 }
f8fd8420 95
96 return channel_mask;
91fd0f72
BV
97}
98
55eca716 99static int convert_trigger(const struct sr_dev_inst *sdi,
100 struct ols_basic_trigger_desc *ols_trigger)
91fd0f72 101{
91fd0f72
BV
102 struct sr_trigger *trigger;
103 struct sr_trigger_stage *stage;
104 struct sr_trigger_match *match;
105 const GSList *l, *m;
106 int i;
107
f8fd8420 108 ols_trigger->num_stages = 0;
109 for (i = 0; i < NUM_BASIC_TRIGGER_STAGES; i++) {
110 ols_trigger->trigger_mask[i] = 0;
111 ols_trigger->trigger_value[i] = 0;
0aba65da
UH
112 }
113
0812c40e 114 if (!(trigger = sr_session_trigger_get(sdi->session)))
91fd0f72 115 return SR_OK;
0aba65da 116
f8fd8420 117 ols_trigger->num_stages = g_slist_length(trigger->stages);
118 if (ols_trigger->num_stages > NUM_BASIC_TRIGGER_STAGES) {
91fd0f72 119 sr_err("This device only supports %d trigger stages.",
55eca716 120 NUM_BASIC_TRIGGER_STAGES);
91fd0f72
BV
121 return SR_ERR;
122 }
b1de0407 123
91fd0f72
BV
124 for (l = trigger->stages; l; l = l->next) {
125 stage = l->data;
126 for (m = stage->matches; m; m = m->next) {
127 match = m->data;
128 if (!match->channel->enabled)
129 /* Ignore disabled channels with a trigger. */
130 continue;
55eca716 131 ols_trigger->trigger_mask[stage->stage] |=
132 1 << match->channel->index;
91fd0f72 133 if (match->match == SR_TRIGGER_ONE)
55eca716 134 ols_trigger->trigger_value[stage->stage] |=
135 1 << match->channel->index;
0aba65da 136 }
0aba65da
UH
137 }
138
139 return SR_OK;
140}
141
4a34a74d
WS
142static void ols_channel_new(struct sr_dev_inst *sdi, int num_chan)
143{
ea642977 144 struct dev_context *devc = sdi->priv;
4a34a74d
WS
145 int i;
146
147 for (i = 0; i < num_chan; i++)
148 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
55eca716 149 ols_channel_names[i]);
ea642977
WS
150
151 devc->max_channels = num_chan;
4a34a74d
WS
152}
153
aad6b9de 154static void ols_metadata_quirks(struct sr_dev_inst *sdi)
ad4174c1
GS
155{
156 struct dev_context *devc;
157 gboolean is_shrimp;
158
159 if (!sdi)
160 return;
161 devc = sdi->priv;
162 if (!devc)
163 return;
164
165 is_shrimp = sdi->model && strcmp(sdi->model, "Shrimp1.0") == 0;
166 if (is_shrimp) {
167 if (!devc->max_channels)
168 ols_channel_new(sdi, 4);
169 if (!devc->max_samples)
170 devc->max_samples = 256 * 1024;
171 if (!devc->max_samplerate)
172 devc->max_samplerate = SR_MHZ(20);
173 }
6f9234e6 174
175 if (sdi->version && strstr(sdi->version, "FPGA version 3.07"))
176 devc->device_flags |= DEVICE_FLAG_IS_DEMON_CORE;
ad4174c1
GS
177}
178
838f0122 179SR_PRIV int ols_get_metadata(struct sr_dev_inst *sdi)
0aba65da 180{
838f0122 181 struct sr_serial_dev_inst *serial;
0aba65da 182 struct dev_context *devc;
4a34a74d 183 uint32_t tmp_int;
6f9234e6 184 uint8_t key, type;
f4d3a4fb 185 int delay_ms;
0aba65da
UH
186 GString *tmp_str, *devname, *version;
187 guchar tmp_c;
188
838f0122
GS
189 serial = sdi->conn;
190 devc = sdi->priv;
0aba65da
UH
191
192 devname = g_string_new("");
193 version = g_string_new("");
194
195 key = 0xff;
196 while (key) {
f4d3a4fb
BV
197 delay_ms = serial_timeout(serial, 1);
198 if (serial_read_blocking(serial, &key, 1, delay_ms) != 1)
0aba65da 199 break;
6f9234e6 200 if (key == METADATA_TOKEN_END) {
625763e2
BV
201 sr_dbg("Got metadata key 0x00, metadata ends.");
202 break;
203 }
0aba65da 204 type = key >> 5;
0aba65da
UH
205 switch (type) {
206 case 0:
207 /* NULL-terminated string */
208 tmp_str = g_string_new("");
f4d3a4fb 209 delay_ms = serial_timeout(serial, 1);
55eca716 210 while (serial_read_blocking(serial, &tmp_c, 1,
211 delay_ms) == 1 &&
212 tmp_c != '\0')
0aba65da 213 g_string_append_c(tmp_str, tmp_c);
55eca716 214 sr_dbg("Got metadata token 0x%.2x value '%s'.", key,
215 tmp_str->str);
6f9234e6 216 switch (key) {
217 case METADATA_TOKEN_DEVICE_NAME:
0aba65da 218 /* Device name */
55eca716 219 devname =
220 g_string_append(devname, tmp_str->str);
0aba65da 221 break;
6f9234e6 222 case METADATA_TOKEN_FPGA_VERSION:
0aba65da
UH
223 /* FPGA firmware version */
224 if (version->len)
225 g_string_append(version, ", ");
226 g_string_append(version, "FPGA version ");
227 g_string_append(version, tmp_str->str);
228 break;
6f9234e6 229 case METADATA_TOKEN_ANCILLARY_VERSION:
0aba65da
UH
230 /* Ancillary version */
231 if (version->len)
232 g_string_append(version, ", ");
233 g_string_append(version, "Ancillary version ");
234 g_string_append(version, tmp_str->str);
235 break;
236 default:
55eca716 237 sr_info("ols: unknown token 0x%.2x: '%s'", key,
238 tmp_str->str);
0aba65da
UH
239 break;
240 }
241 g_string_free(tmp_str, TRUE);
242 break;
243 case 1:
244 /* 32-bit unsigned integer */
f4d3a4fb 245 delay_ms = serial_timeout(serial, 4);
55eca716 246 if (serial_read_blocking(serial, &tmp_int, 4,
247 delay_ms) != 4)
0aba65da 248 break;
016e72f3 249 tmp_int = RB32(&tmp_int);
55eca716 250 sr_dbg("Got metadata token 0x%.2x value 0x%.8x.", key,
251 tmp_int);
6f9234e6 252 switch (key) {
253 case METADATA_TOKEN_NUM_PROBES_LONG:
ba7dd8bb 254 /* Number of usable channels */
4a34a74d 255 ols_channel_new(sdi, tmp_int);
0aba65da 256 break;
6f9234e6 257 case METADATA_TOKEN_SAMPLE_MEMORY_BYTES:
0aba65da
UH
258 /* Amount of sample memory available (bytes) */
259 devc->max_samples = tmp_int;
260 break;
6f9234e6 261 case METADATA_TOKEN_DYNAMIC_MEMORY_BYTES:
0aba65da
UH
262 /* Amount of dynamic memory available (bytes) */
263 /* what is this for? */
264 break;
6f9234e6 265 case METADATA_TOKEN_MAX_SAMPLE_RATE_HZ:
f3f19d11 266 /* Maximum sample rate (Hz) */
0aba65da
UH
267 devc->max_samplerate = tmp_int;
268 break;
6f9234e6 269 case METADATA_TOKEN_PROTOCOL_VERSION_LONG:
0aba65da
UH
270 /* protocol version */
271 devc->protocol_version = tmp_int;
272 break;
273 default:
55eca716 274 sr_info("Unknown token 0x%.2x: 0x%.8x.", key,
275 tmp_int);
0aba65da
UH
276 break;
277 }
278 break;
279 case 2:
280 /* 8-bit unsigned integer */
f4d3a4fb
BV
281 delay_ms = serial_timeout(serial, 1);
282 if (serial_read_blocking(serial, &tmp_c, 1, delay_ms) != 1)
0aba65da 283 break;
55eca716 284 sr_dbg("Got metadata token 0x%.2x value 0x%.2x.", key,
285 tmp_c);
6f9234e6 286 switch (key) {
287 case METADATA_TOKEN_NUM_PROBES_SHORT:
ba7dd8bb 288 /* Number of usable channels */
4a34a74d 289 ols_channel_new(sdi, tmp_c);
0aba65da 290 break;
6f9234e6 291 case METADATA_TOKEN_PROTOCOL_VERSION_SHORT:
0aba65da
UH
292 /* protocol version */
293 devc->protocol_version = tmp_c;
294 break;
295 default:
55eca716 296 sr_info("Unknown token 0x%.2x: 0x%.2x.", key,
297 tmp_c);
0aba65da
UH
298 break;
299 }
300 break;
301 default:
302 /* unknown type */
303 break;
304 }
305 }
306
307 sdi->model = devname->str;
308 sdi->version = version->str;
309 g_string_free(devname, FALSE);
310 g_string_free(version, FALSE);
311
ad4174c1 312 /* Optionally amend received metadata, model specific quirks. */
aad6b9de 313 ols_metadata_quirks(sdi);
ad4174c1 314
838f0122 315 return SR_OK;
0aba65da
UH
316}
317
318SR_PRIV int ols_set_samplerate(const struct sr_dev_inst *sdi,
55eca716 319 const uint64_t samplerate)
0aba65da
UH
320{
321 struct dev_context *devc;
322
323 devc = sdi->priv;
e46aa4f6 324 if (devc->max_samplerate && samplerate > devc->max_samplerate)
0aba65da
UH
325 return SR_ERR_SAMPLERATE;
326
327 if (samplerate > CLOCK_RATE) {
6ebe0039 328 sr_info("Enabling demux mode.");
a80bed76 329 devc->capture_flags |= CAPTURE_FLAG_DEMUX;
330 devc->capture_flags &= ~CAPTURE_FLAG_NOISE_FILTER;
55eca716 331 devc->cur_samplerate_divider =
332 (CLOCK_RATE * 2 / samplerate) - 1;
0aba65da 333 } else {
6ebe0039 334 sr_info("Disabling demux mode.");
a80bed76 335 devc->capture_flags &= ~CAPTURE_FLAG_DEMUX;
336 devc->capture_flags |= CAPTURE_FLAG_NOISE_FILTER;
0aba65da
UH
337 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
338 }
339
340 /* Calculate actual samplerate used and complain if it is different
341 * from the requested.
342 */
343 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
a80bed76 344 if (devc->capture_flags & CAPTURE_FLAG_DEMUX)
0aba65da
UH
345 devc->cur_samplerate *= 2;
346 if (devc->cur_samplerate != samplerate)
55eca716 347 sr_info("Can't match samplerate %" PRIu64 ", using %" PRIu64
348 ".",
349 samplerate, devc->cur_samplerate);
0aba65da
UH
350
351 return SR_OK;
352}
353
354SR_PRIV void abort_acquisition(const struct sr_dev_inst *sdi)
355{
459a0f26 356 struct sr_serial_dev_inst *serial;
0aba65da 357
459a0f26 358 serial = sdi->conn;
7dd1dd9f 359 ols_send_reset(serial);
6d8182b6 360
102f1239 361 serial_source_remove(sdi->session, serial);
0aba65da 362
bee2b016 363 std_session_send_df_end(sdi);
0aba65da
UH
364}
365
366SR_PRIV int ols_receive_data(int fd, int revents, void *cb_data)
367{
459a0f26 368 struct dev_context *devc;
625763e2 369 struct sr_dev_inst *sdi;
459a0f26 370 struct sr_serial_dev_inst *serial;
0aba65da
UH
371 struct sr_datafeed_packet packet;
372 struct sr_datafeed_logic logic;
fe9ac252 373 uint32_t sample;
f8fd8420 374 int num_changroups, offset, j;
b1de0407 375 unsigned int i;
0aba65da 376 unsigned char byte;
625763e2
BV
377
378 (void)fd;
379
380 sdi = cb_data;
381 serial = sdi->conn;
382 devc = sdi->priv;
0aba65da 383
8105e829
DE
384 if (devc->num_transfers == 0 && revents == 0) {
385 /* Ignore timeouts as long as we haven't received anything */
386 return TRUE;
387 }
388
0aba65da 389 if (devc->num_transfers++ == 0) {
0aba65da
UH
390 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
391 if (!devc->raw_sample_buf) {
392 sr_err("Sample buffer malloc failed.");
393 return FALSE;
394 }
395 /* fill with 1010... for debugging */
396 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
397 }
398
f8fd8420 399 num_changroups = 0;
be15c51e 400 for (i = 0x20; i > 0x02; i >>= 1) {
a80bed76 401 if ((devc->capture_flags & i) == 0) {
f8fd8420 402 num_changroups++;
f51acd69 403 }
0aba65da
UH
404 }
405
faf72024 406 if (revents == G_IO_IN && devc->num_samples < devc->limit_samples) {
9f5d4c3c 407 if (serial_read_nonblocking(serial, &byte, 1) != 1)
0aba65da 408 return FALSE;
625763e2 409 devc->cnt_bytes++;
0aba65da
UH
410
411 /* Ignore it if we've read enough. */
412 if (devc->num_samples >= devc->limit_samples)
413 return TRUE;
414
415 devc->sample[devc->num_bytes++] = byte;
6d16fdfb 416 sr_spew("Received byte 0x%.2x.", byte);
f8fd8420 417 if (devc->num_bytes == num_changroups) {
625763e2
BV
418 devc->cnt_samples++;
419 devc->cnt_samples_rle++;
420 /*
421 * Got a full sample. Convert from the OLS's little-endian
422 * sample to the local format.
423 */
55eca716 424 sample = devc->sample[0] | (devc->sample[1] << 8) |
425 (devc->sample[2] << 16) |
426 (devc->sample[3] << 24);
427 sr_dbg("Received sample 0x%.*x.", devc->num_bytes * 2,
428 sample);
a80bed76 429 if (devc->capture_flags & CAPTURE_FLAG_RLE) {
0aba65da 430 /*
00d04d3b
BV
431 * In RLE mode the high bit of the sample is the
432 * "count" flag, meaning this sample is the number
433 * of times the previous sample occurred.
0aba65da
UH
434 */
435 if (devc->sample[devc->num_bytes - 1] & 0x80) {
00d04d3b 436 /* Clear the high bit. */
55eca716 437 sample &= ~(0x80 << (devc->num_bytes -
438 1) * 8);
fe9ac252 439 devc->rle_count = sample;
55eca716 440 devc->cnt_samples_rle +=
441 devc->rle_count;
442 sr_dbg("RLE count: %u.",
443 devc->rle_count);
0aba65da
UH
444 devc->num_bytes = 0;
445 return TRUE;
446 }
447 }
448 devc->num_samples += devc->rle_count + 1;
449 if (devc->num_samples > devc->limit_samples) {
450 /* Save us from overrunning the buffer. */
55eca716 451 devc->rle_count -=
452 devc->num_samples - devc->limit_samples;
0aba65da
UH
453 devc->num_samples = devc->limit_samples;
454 }
455
f8fd8420 456 if (num_changroups < 4) {
0aba65da
UH
457 /*
458 * Some channel groups may have been turned
459 * off, to speed up transfer between the
460 * hardware and the PC. Expand that here before
461 * submitting it over the session bus --
462 * whatever is listening on the bus will be
463 * expecting a full 32-bit sample, based on
ba7dd8bb 464 * the number of channels.
0aba65da
UH
465 */
466 j = 0;
cfe55d09 467 uint8_t tmp_sample[4] = { 0, 0, 0, 0 };
0aba65da 468 for (i = 0; i < 4; i++) {
55eca716 469 if (((devc->capture_flags >> 2) &
470 (1 << i)) == 0) {
0aba65da
UH
471 /*
472 * This channel group was
473 * enabled, copy from received
474 * sample.
475 */
cfe55d09 476 tmp_sample[i] =
55eca716 477 devc->sample[j++];
0aba65da
UH
478 }
479 }
cfe55d09 480 memcpy(devc->sample, tmp_sample, 4);
29f15d52 481 sr_spew("Expanded sample: 0x%.2hhx%.2hhx%.2hhx%.2hhx ",
55eca716 482 devc->sample[3], devc->sample[2],
483 devc->sample[1], devc->sample[0]);
0aba65da
UH
484 }
485
625763e2
BV
486 /*
487 * the OLS sends its sample buffer backwards.
0aba65da
UH
488 * store it in reverse order here, so we can dump
489 * this on the session bus later.
490 */
491 offset = (devc->limit_samples - devc->num_samples) * 4;
492 for (i = 0; i <= devc->rle_count; i++) {
493 memcpy(devc->raw_sample_buf + offset + (i * 4),
494 devc->sample, 4);
495 }
496 memset(devc->sample, 0, 4);
497 devc->num_bytes = 0;
498 devc->rle_count = 0;
499 }
500 } else {
501 /*
502 * This is the main loop telling us a timeout was reached, or
503 * we've acquired all the samples we asked for -- we're done.
504 * Send the (properly-ordered) buffer to the frontend.
505 */
625763e2 506 sr_dbg("Received %d bytes, %d samples, %d decompressed samples.",
55eca716 507 devc->cnt_bytes, devc->cnt_samples,
508 devc->cnt_samples_rle);
a2b1a53b 509 if (devc->trigger_at_smpl != OLS_NO_TRIGGER) {
625763e2
BV
510 /*
511 * A trigger was set up, so we need to tell the frontend
0aba65da
UH
512 * about it.
513 */
a2b1a53b 514 if (devc->trigger_at_smpl > 0) {
625763e2 515 /* There are pre-trigger samples, send those first. */
0aba65da
UH
516 packet.type = SR_DF_LOGIC;
517 packet.payload = &logic;
a2b1a53b 518 logic.length = devc->trigger_at_smpl * 4;
0aba65da
UH
519 logic.unitsize = 4;
520 logic.data = devc->raw_sample_buf +
55eca716 521 (devc->limit_samples -
522 devc->num_samples) *
523 4;
695dc859 524 sr_session_send(sdi, &packet);
0aba65da
UH
525 }
526
625763e2 527 /* Send the trigger. */
0fa71943 528 std_session_send_df_trigger(sdi);
0aba65da 529 }
2755ab36 530
531 /* Send post-trigger / all captured samples. */
55eca716 532 int num_pre_trigger_samples = devc->trigger_at_smpl ==
533 OLS_NO_TRIGGER ?
534 0 :
535 devc->trigger_at_smpl;
2755ab36 536 packet.type = SR_DF_LOGIC;
537 packet.payload = &logic;
55eca716 538 logic.length =
539 (devc->num_samples - num_pre_trigger_samples) * 4;
2755ab36 540 logic.unitsize = 4;
55eca716 541 logic.data = devc->raw_sample_buf +
542 (num_pre_trigger_samples + devc->limit_samples -
543 devc->num_samples) *
544 4;
2755ab36 545 sr_session_send(sdi, &packet);
546
0aba65da
UH
547 g_free(devc->raw_sample_buf);
548
459a0f26 549 serial_flush(serial);
0aba65da 550 abort_acquisition(sdi);
0aba65da
UH
551 }
552
553 return TRUE;
554}
f8fd8420 555
55eca716 556static int
557ols_set_basic_trigger_stage(const struct ols_basic_trigger_desc *trigger_desc,
558 struct sr_serial_dev_inst *serial, int stage)
f8fd8420 559{
560 uint8_t cmd, arg[4];
561
562 cmd = CMD_SET_BASIC_TRIGGER_MASK0 + stage * 4;
3cc9e215 563 if (ols_send_longdata(serial, cmd, trigger_desc->trigger_mask[stage]) != SR_OK)
f8fd8420 564 return SR_ERR;
565
566 cmd = CMD_SET_BASIC_TRIGGER_VALUE0 + stage * 4;
3cc9e215 567 if (ols_send_longdata(serial, cmd, trigger_desc->trigger_value[stage]) != SR_OK)
f8fd8420 568 return SR_ERR;
569
570 cmd = CMD_SET_BASIC_TRIGGER_CONFIG0 + stage * 4;
571 arg[0] = arg[1] = arg[3] = 0x00;
572 arg[2] = stage;
b28e391a 573 if (stage == trigger_desc->num_stages - 1)
f8fd8420 574 /* Last stage, fire when this one matches. */
575 arg[3] |= TRIGGER_START;
576 if (send_longcommand(serial, cmd, arg) != SR_OK)
577 return SR_ERR;
578
579 return SR_OK;
580}
581
55eca716 582SR_PRIV int ols_prepare_acquisition(const struct sr_dev_inst *sdi)
583{
f8fd8420 584 int ret;
f8fd8420 585
586 struct dev_context *devc = sdi->priv;
587 struct sr_serial_dev_inst *serial = sdi->conn;
588
589 int num_changroups = 0;
590 uint8_t changroup_mask = 0;
591 uint32_t channel_mask = ols_channel_mask(sdi);
592 for (unsigned int i = 0; i < 4; i++) {
593 if (channel_mask & (0xff << (i * 8))) {
594 changroup_mask |= (1 << i);
595 num_changroups++;
596 }
597 }
598
599 /*
600 * Limit readcount to prevent reading past the end of the hardware
601 * buffer. Rather read too many samples than too few.
602 */
55eca716 603 uint32_t samplecount =
604 MIN(devc->max_samples / num_changroups, devc->limit_samples);
f8fd8420 605 uint32_t readcount = (samplecount + 3) / 4;
606 uint32_t delaycount;
607
608 /* Basic triggers. */
609 struct ols_basic_trigger_desc basic_trigger_desc;
610 if (convert_trigger(sdi, &basic_trigger_desc) != SR_OK) {
611 sr_err("Failed to configure channels.");
612 return SR_ERR;
613 }
614 if (basic_trigger_desc.num_stages > 0) {
615 /*
616 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
617 * reset command must be send prior each arm command
618 */
619 sr_dbg("Send reset command before trigger configure");
620 if (ols_send_reset(serial) != SR_OK)
621 return SR_ERR;
622
623 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
55eca716 624 devc->trigger_at_smpl = (readcount - delaycount) * 4 -
625 basic_trigger_desc.num_stages;
b28e391a 626 for (int i = 0; i < basic_trigger_desc.num_stages; i++) {
f8fd8420 627 sr_dbg("Setting OLS stage %d trigger.", i);
55eca716 628 if ((ret = ols_set_basic_trigger_stage(
629 &basic_trigger_desc, serial, i)) != SR_OK)
f8fd8420 630 return ret;
631 }
632 } else {
633 /* No triggers configured, force trigger on first stage. */
634 sr_dbg("Forcing trigger at stage 0.");
b28e391a 635 basic_trigger_desc.num_stages = 1;
55eca716 636 if ((ret = ols_set_basic_trigger_stage(&basic_trigger_desc,
637 serial, 0)) != SR_OK)
f8fd8420 638 return ret;
639 delaycount = readcount;
640 }
641
642 /* Samplerate. */
643 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
55eca716 644 devc->cur_samplerate, devc->cur_samplerate_divider);
645 if (ols_send_longdata(serial, CMD_SET_DIVIDER,
646 devc->cur_samplerate_divider & 0x00FFFFFF) != SR_OK)
f8fd8420 647 return SR_ERR;
648
649 /* Send sample limit and pre/post-trigger capture ratio. */
650 sr_dbg("Setting sample limit %d, trigger point at %d",
55eca716 651 (readcount - 1) * 4, (delaycount - 1) * 4);
f8fd8420 652
653 if (devc->max_samples > 256 * 1024) {
55eca716 654 if (ols_send_longdata(serial, CMD_CAPTURE_READCOUNT,
655 readcount - 1) != SR_OK)
f8fd8420 656 return SR_ERR;
55eca716 657 if (ols_send_longdata(serial, CMD_CAPTURE_DELAYCOUNT,
658 delaycount - 1) != SR_OK)
f8fd8420 659 return SR_ERR;
660 } else {
3cc9e215 661 uint8_t arg[4];
55eca716 662 WL16(&arg[0], readcount - 1);
663 WL16(&arg[2], delaycount - 1);
f8fd8420 664 if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
665 return SR_ERR;
666 }
667
668 /* Flag register. */
55eca716 669 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s, "
670 "%s clock%s",
671 devc->capture_flags & CAPTURE_FLAG_INTERNAL_TEST_MODE ? "on" :
672 "off",
673 devc->capture_flags & CAPTURE_FLAG_EXTERNAL_TEST_MODE ? "on" :
674 "off",
675 devc->capture_flags & CAPTURE_FLAG_RLE ? "on" : "off",
676 devc->capture_flags & CAPTURE_FLAG_NOISE_FILTER ? "on" : "off",
677 devc->capture_flags & CAPTURE_FLAG_DEMUX ? "on" : "off",
678 devc->capture_flags & CAPTURE_FLAG_CLOCK_EXTERNAL ? "external" :
679 "internal",
680 devc->capture_flags & CAPTURE_FLAG_CLOCK_EXTERNAL ?
681 (devc->capture_flags & CAPTURE_FLAG_INVERT_EXT_CLOCK ?
682 " on falling edge" :
683 "on rising edge") :
684 "");
f8fd8420 685
686 /*
687 * Enable/disable OLS channel groups in the flag register according
688 * to the channel mask. 1 means "disable channel".
689 */
690 devc->capture_flags &= ~0x3c;
691 devc->capture_flags |= ~(changroup_mask << 2) & 0x3c;
692
693 /* RLE mode is always zero, for now. */
694
3cc9e215 695 if (ols_send_longdata(serial, CMD_SET_FLAGS, devc->capture_flags) != SR_OK)
f8fd8420 696 return SR_ERR;
697
698 return SR_OK;
699}