[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

#define SERIALCOMM "115200/8n1"

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t scanopts[] = {
	SR_CONF_CONN,
	SR_CONF_SERIALCOMM,
};

static const uint32_t devopts[] = {
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_EXTERNAL_CLOCK | SR_CONF_SET,
	SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SWAP | SR_CONF_SET,
	SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
};

#define STR_PATTERN_NONE     "None"
#define STR_PATTERN_EXTERNAL "External"
#define STR_PATTERN_INTERNAL "Internal"

/* Supported methods of test pattern outputs */
enum {
	/**
	 * Capture pins 31:16 (unbuffered wing) output a test pattern
	 * that can captured on pins 0:15.
	 */
	PATTERN_EXTERNAL,

	/** Route test pattern internally to capture buffer. */
	PATTERN_INTERNAL,
};

static const char *patterns[] = {
	STR_PATTERN_NONE,
	STR_PATTERN_EXTERNAL,
	STR_PATTERN_INTERNAL,
};

/* Channels are numbered 0-31 (on the PCB silkscreen). */
SR_PRIV const char *ols_channel_names[] = {
	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	"24", "25", "26", "27", "28", "29", "30", "31",
};

/* Default supported samplerates, can be overridden by device metadata. */
static const uint64_t samplerates[] = {
	SR_HZ(10),
	SR_MHZ(200),
	SR_HZ(1),
};

#define RESPONSE_DELAY_US (10 * 1000)

SR_PRIV struct sr_dev_driver ols_driver_info;

static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
{
	return std_init(sr_ctx, di, LOG_PREFIX);
}

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct sr_config *src;
	struct sr_dev_inst *sdi;
	struct drv_context *drvc;
	struct sr_serial_dev_inst *serial;
	GSList *l, *devices;
	int ret;
	unsigned int i;
	const char *conn, *serialcomm;
	char buf[8];

	drvc = di->context;

	devices = NULL;

	conn = serialcomm = NULL;
	for (l = options; l; l = l->next) {
		src = l->data;
		switch (src->key) {
		case SR_CONF_CONN:
			conn = g_variant_get_string(src->data, NULL);
			break;
		case SR_CONF_SERIALCOMM:
			serialcomm = g_variant_get_string(src->data, NULL);
			break;
		}
	}
	if (!conn)
		return NULL;

	if (!serialcomm)
		serialcomm = SERIALCOMM;

	serial = sr_serial_dev_inst_new(conn, serialcomm);

	/* The discovery procedure is like this: first send the Reset
	 * command (0x00) 5 times, since the device could be anywhere
	 * in a 5-byte command. Then send the ID command (0x02).
	 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	 * have a match.
	 */
	sr_info("Probing %s.", conn);
	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
		return NULL;

	ret = SR_OK;
	for (i = 0; i < 5; i++) {
		if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
			sr_err("Port %s is not writable.", conn);
			break;
		}
	}
	if (ret != SR_OK) {
		serial_close(serial);
		sr_err("Could not use port %s. Quitting.", conn);
		return NULL;
	}
	send_shortcommand(serial, CMD_ID);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) == 0) {
		sr_dbg("Didn't get any reply.");
		return NULL;
	}

	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	if (ret != 4) {
		sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
		return NULL;
	}

	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
		sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
		       "'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
		return NULL;
	}

	/* Definitely using the OLS protocol, check if it supports
	 * the metadata command.
	 */
	send_shortcommand(serial, CMD_METADATA);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) != 0) {
		/* Got metadata. */
		sdi = get_metadata(serial);
	} else {
		/* Not an OLS -- some other board that uses the sump protocol. */
		sr_info("Device does not support metadata.");
		sdi = g_malloc0(sizeof(struct sr_dev_inst));
		sdi->status = SR_ST_INACTIVE;
		sdi->vendor = g_strdup("Sump");
		sdi->model = g_strdup("Logic Analyzer");
		sdi->version = g_strdup("v1.0");
		sdi->driver = di;
		for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
			sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
					ols_channel_names[i]);
		sdi->priv = ols_dev_new();
	}
	/* Configure samplerate and divider. */
	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
		sr_dbg("Failed to set default samplerate (%"PRIu64").",
				DEFAULT_SAMPLERATE);
	sdi->inst_type = SR_INST_SERIAL;
	sdi->conn = serial;

	drvc->instances = g_slist_append(drvc->instances, sdi);
	devices = g_slist_append(devices, sdi);

	serial_close(serial);

	return devices;
}

static GSList *dev_list(const struct sr_dev_driver *di)
{
	return ((struct drv_context *)(di->context))->instances;
}

static int cleanup(const struct sr_dev_driver *di)
{
	return std_dev_clear(di, NULL);
}

static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;

	(void)cg;

	if (!sdi)
		return SR_ERR_ARG;

	devc = sdi->priv;
	switch (key) {
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(devc->cur_samplerate);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->limit_samples);
		break;
	case SR_CONF_PATTERN_MODE:
		if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
		else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_INTERNAL);
		else
			*data = g_variant_new_string(STR_PATTERN_NONE);
		break;
	case SR_CONF_RLE:
		*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	uint16_t flag;
	uint64_t tmp_u64;
	int ret;
	const char *stropt;

	(void)cg;

	if (sdi->status != SR_ST_ACTIVE)
		return SR_ERR_DEV_CLOSED;

	devc = sdi->priv;

	switch (key) {
	case SR_CONF_SAMPLERATE:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
			return SR_ERR_SAMPLERATE;
		ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < MIN_NUM_SAMPLES)
			return SR_ERR;
		devc->limit_samples = tmp_u64;
		ret = SR_OK;
		break;
	case SR_CONF_CAPTURE_RATIO:
		devc->capture_ratio = g_variant_get_uint64(data);
		if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
			devc->capture_ratio = 0;
			ret = SR_ERR;
		} else
			ret = SR_OK;
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling external clock.");
			devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
		} else {
			sr_info("Disabled external clock.");
			devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
		}
		ret = SR_OK;
		break;
	case SR_CONF_PATTERN_MODE:
		stropt = g_variant_get_string(data, NULL);
		ret = SR_OK;
		flag = 0xffff;
		if (!strcmp(stropt, STR_PATTERN_NONE)) {
			sr_info("Disabling test modes.");
			flag = 0x0000;
		}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
			sr_info("Enabling internal test mode.");
			flag = FLAG_INTERNAL_TEST_MODE;
		} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
			sr_info("Enabling external test mode.");
			flag = FLAG_EXTERNAL_TEST_MODE;
		} else {
			ret = SR_ERR;
		}
		if (flag != 0xffff) {
			devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
			devc->flag_reg |= flag;
		}
		break;
	case SR_CONF_SWAP:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling channel swapping.");
			devc->flag_reg |= FLAG_SWAP_CHANNELS;
		} else {
			sr_info("Disabling channel swapping.");
			devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
		}
		ret = SR_OK;
		break;

	case SR_CONF_RLE:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling RLE.");
			devc->flag_reg |= FLAG_RLE;
		} else {
			sr_info("Disabling RLE.");
			devc->flag_reg &= ~FLAG_RLE;
		}
		ret = SR_OK;
		break;
	default:
		ret = SR_ERR_NA;
	}

	return ret;
}

static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	GVariant *gvar, *grange[2];
	GVariantBuilder gvb;
	int num_ols_changrp, i;

	(void)cg;

	switch (key) {
	case SR_CONF_SCAN_OPTIONS:
		*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
				scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
		break;
	case SR_CONF_DEVICE_OPTIONS:
		if (!sdi)
			*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
					drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
		else
			*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
					devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
		break;
	case SR_CONF_SAMPLERATE:
		g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
		gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
				ARRAY_SIZE(samplerates), sizeof(uint64_t));
		g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
		*data = g_variant_builder_end(&gvb);
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
				trigger_matches, ARRAY_SIZE(trigger_matches),
				sizeof(int32_t));
		break;
	case SR_CONF_PATTERN_MODE:
		*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		if (!sdi)
			return SR_ERR_ARG;
		devc = sdi->priv;
		if (devc->flag_reg & FLAG_RLE)
			return SR_ERR_NA;
		if (devc->max_samples == 0)
			/* Device didn't specify sample memory size in metadata. */
			return SR_ERR_NA;
		/*
		 * Channel groups are turned off if no channels in that group are
		 * enabled, making more room for samples for the enabled group.
		*/
		ols_channel_mask(sdi);
		num_ols_changrp = 0;
		for (i = 0; i < 4; i++) {
			if (devc->channel_mask & (0xff << (i * 8)))
				num_ols_changrp++;
		}
		grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		if (num_ols_changrp)
			grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
		else
			grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		*data = g_variant_new_tuple(grange, 2);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int set_trigger(const struct sr_dev_inst *sdi, int stage)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint8_t cmd, arg[4];

	devc = sdi->priv;
	serial = sdi->conn;

	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	arg[0] = devc->trigger_mask[stage] & 0xff;
	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	arg[0] = devc->trigger_value[stage] & 0xff;
	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	arg[0] = arg[1] = arg[3] = 0x00;
	arg[2] = stage;
	if (stage == devc->num_stages)
		/* Last stage, fire when this one matches. */
		arg[3] |= TRIGGER_START;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi,
		void *cb_data)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint16_t samplecount, readcount, delaycount;
	uint8_t ols_changrp_mask, arg[4];
	int num_ols_changrp;
	int ret, i;

	if (sdi->status != SR_ST_ACTIVE)
		return SR_ERR_DEV_CLOSED;

	devc = sdi->priv;
	serial = sdi->conn;

	ols_channel_mask(sdi);

	num_ols_changrp = 0;
	ols_changrp_mask = 0;
	for (i = 0; i < 4; i++) {
		if (devc->channel_mask & (0xff << (i * 8))) {
			ols_changrp_mask |= (1 << i);
			num_ols_changrp++;
		}
	}

	/*
	 * Limit readcount to prevent reading past the end of the hardware
	 * buffer.
	 */
	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
	readcount = samplecount / 4;

	/* Rather read too many samples than too few. */
	if (samplecount % 4 != 0)
		readcount++;

	/* Basic triggers. */
	if (ols_convert_trigger(sdi) != SR_OK) {
		sr_err("Failed to configure channels.");
		return SR_ERR;
	}
	if (devc->num_stages > 0) {
		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
		for (i = 0; i <= devc->num_stages; i++) {
			sr_dbg("Setting OLS stage %d trigger.", i);
			if ((ret = set_trigger(sdi, i)) != SR_OK)
				return ret;
		}
	} else {
		/* No triggers configured, force trigger on first stage. */
		sr_dbg("Forcing trigger at stage 0.");
		if ((ret = set_trigger(sdi, 0)) != SR_OK)
			return ret;
		delaycount = readcount;
	}

	/* Samplerate. */
	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
			devc->cur_samplerate, devc->cur_samplerate_divider);
	arg[0] = devc->cur_samplerate_divider & 0xff;
	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
		return SR_ERR;

	/* Send sample limit and pre/post-trigger capture ratio. */
	sr_dbg("Setting sample limit %d, trigger point at %d",
			(readcount - 1) * 4, (delaycount - 1) * 4);
	arg[0] = ((readcount - 1) & 0xff);
	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	arg[2] = ((delaycount - 1) & 0xff);
	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
		return SR_ERR;

	/* Flag register. */
	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
			devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_RLE ? "on" : "off",
			devc->flag_reg & FLAG_FILTER ? "on": "off",
			devc->flag_reg & FLAG_DEMUX ? "on" : "off");
	/*
	 * Enable/disable OLS channel groups in the flag register according
	 * to the channel mask. 1 means "disable channel".
	 */
	devc->flag_reg |= ~(ols_changrp_mask << 2) & 0x3c;
	arg[0] = devc->flag_reg & 0xff;
	arg[1] = devc->flag_reg >> 8;
	arg[2] = arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
		return SR_ERR;

	/* Start acquisition on the device. */
	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
		return SR_ERR;

	/* Reset all operational states. */
	devc->rle_count = devc->num_transfers = 0;
	devc->num_samples = devc->num_bytes = 0;
	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
	memset(devc->sample, 0, 4);

	/* Send header packet to the session bus. */
	std_session_send_df_header(cb_data, LOG_PREFIX);

	serial_source_add(sdi->session, serial, G_IO_IN, -1,
			ols_receive_data, cb_data);

	return SR_OK;
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
{
	(void)cb_data;

	abort_acquisition(sdi);

	return SR_OK;
}

SR_PRIV struct sr_dev_driver ols_driver_info = {
	.name = "ols",
	.longname = "Openbench Logic Sniffer",
	.api_version = 1,
	.init = init,
	.cleanup = cleanup,
	.scan = scan,
	.dev_list = dev_list,
	.dev_clear = NULL,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = std_serial_dev_open,
	.dev_close = std_serial_dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
Commit	Line	Data
0aba65da	1	/*
50985c20	2	* This file is part of the libsigrok project.
0aba65da	3	*
13d8e03c	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da UH	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
6ec6c43b	20	#include <config.h>
515ab088	21	#include "protocol.h"
0aba65da UH	22
	23	#define SERIALCOMM "115200/8n1"
	24
63ea6141 BV	25	static const uint32_t drvopts[] = {
	26	SR_CONF_LOGIC_ANALYZER,
	27	};
	28
a0e0bb41	29	static const uint32_t scanopts[] = {
1953564a BV	30	SR_CONF_CONN,
1953564a BV	31	SR_CONF_SERIALCOMM,
aeabd308 UH	32	};
aeabd308 UH	33
f254bc4b	34	static const uint32_t devopts[] = {
5827f61b BV	35	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	36	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	37	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	38	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET,
	39	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_SET,
	40	SR_CONF_PATTERN_MODE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	41	SR_CONF_SWAP \| SR_CONF_SET,
	42	SR_CONF_RLE \| SR_CONF_GET \| SR_CONF_SET,
0aba65da UH	43	};
0aba65da UH	44
91fd0f72 BV	45	static const int32_t trigger_matches[] = {
	46	SR_TRIGGER_ZERO,
	47	SR_TRIGGER_ONE,
	48	};
	49
6d16fdfb BV	50	#define STR_PATTERN_NONE "None"
	51	#define STR_PATTERN_EXTERNAL "External"
	52	#define STR_PATTERN_INTERNAL "Internal"
967760a8 MR	53
	54	/* Supported methods of test pattern outputs */
	55	enum {
	56	/**
	57	* Capture pins 31:16 (unbuffered wing) output a test pattern
	58	* that can captured on pins 0:15.
	59	*/
	60	PATTERN_EXTERNAL,
	61
	62	/** Route test pattern internally to capture buffer. */
	63	PATTERN_INTERNAL,
	64	};
	65
7c07a178	66	static const char *patterns[] = {
6d16fdfb	67	STR_PATTERN_NONE,
7c07a178 UH	68	STR_PATTERN_EXTERNAL,
	69	STR_PATTERN_INTERNAL,
	70	};
	71
ba7dd8bb	72	/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a	73	SR_PRIV const char *ols_channel_names[] = {
78693401 UH	74	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	75	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	76	"24", "25", "26", "27", "28", "29", "30", "31",
0aba65da UH	77	};
0aba65da UH	78
d3b38ad3	79	/* Default supported samplerates, can be overridden by device metadata. */
e46aa4f6 BV	80	static const uint64_t samplerates[] = {
	81	SR_HZ(10),
	82	SR_MHZ(200),
	83	SR_HZ(1),
0aba65da UH	84	};
0aba65da UH	85
1a46cc62 UH	86	#define RESPONSE_DELAY_US (10 * 1000)
1a46cc62 UH	87
0aba65da	88	SR_PRIV struct sr_dev_driver ols_driver_info;
0aba65da	89
4f840ce9	90	static int init(struct sr_dev_driver di, struct sr_context sr_ctx)
0aba65da	91	{
f6beaac5	92	return std_init(sr_ctx, di, LOG_PREFIX);
0aba65da UH	93	}
0aba65da UH	94
4f840ce9	95	static GSList scan(struct sr_dev_driver di, GSList *options)
0aba65da	96	{
1987b8d6	97	struct sr_config *src;
0aba65da UH	98	struct sr_dev_inst *sdi;
0aba65da UH	99	struct drv_context *drvc;
0aba65da	100	struct sr_serial_dev_inst *serial;
0aba65da	101	GSList l, devices;
07ffa5b3 UH	102	int ret;
07ffa5b3 UH	103	unsigned int i;
0aba65da UH	104	const char conn, serialcomm;
	105	char buf[8];
	106
41812aca	107	drvc = di->context;
4b97c74e	108
0aba65da UH	109	devices = NULL;
	110
	111	conn = serialcomm = NULL;
	112	for (l = options; l; l = l->next) {
1987b8d6 BV	113	src = l->data;
1987b8d6 BV	114	switch (src->key) {
1953564a	115	case SR_CONF_CONN:
e46aa4f6	116	conn = g_variant_get_string(src->data, NULL);
0aba65da	117	break;
1953564a	118	case SR_CONF_SERIALCOMM:
e46aa4f6	119	serialcomm = g_variant_get_string(src->data, NULL);
0aba65da UH	120	break;
	121	}
	122	}
	123	if (!conn)
	124	return NULL;
	125
98fec29e	126	if (!serialcomm)
0aba65da UH	127	serialcomm = SERIALCOMM;
0aba65da UH	128
91219afc	129	serial = sr_serial_dev_inst_new(conn, serialcomm);
0aba65da UH	130
	131	/* The discovery procedure is like this: first send the Reset
	132	* command (0x00) 5 times, since the device could be anywhere
	133	* in a 5-byte command. Then send the ID command (0x02).
	134	* If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	135	* have a match.
	136	*/
	137	sr_info("Probing %s.", conn);
4ded59ee	138	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
0aba65da UH	139	return NULL;
	140
	141	ret = SR_OK;
	142	for (i = 0; i < 5; i++) {
	143	if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
	144	sr_err("Port %s is not writable.", conn);
	145	break;
	146	}
	147	}
	148	if (ret != SR_OK) {
	149	serial_close(serial);
	150	sr_err("Could not use port %s. Quitting.", conn);
	151	return NULL;
	152	}
	153	send_shortcommand(serial, CMD_ID);
	154
1a46cc62	155	g_usleep(RESPONSE_DELAY_US);
0aba65da	156
ed936ccc UH	157	if (sp_input_waiting(serial->data) == 0) {
ed936ccc UH	158	sr_dbg("Didn't get any reply.");
0aba65da	159	return NULL;
ed936ccc UH	160	}
	161
	162	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	163	if (ret != 4) {
	164	sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
0aba65da	165	return NULL;
ed936ccc UH	166	}
	167
	168	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
	169	sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
	170	"'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
0aba65da	171	return NULL;
ed936ccc	172	}
0aba65da UH	173
	174	/* Definitely using the OLS protocol, check if it supports
	175	* the metadata command.
	176	*/
	177	send_shortcommand(serial, CMD_METADATA);
ed936ccc	178
1a46cc62	179	g_usleep(RESPONSE_DELAY_US);
ed936ccc UH	180
ed936ccc UH	181	if (sp_input_waiting(serial->data) != 0) {
0aba65da UH	182	/* Got metadata. */
0aba65da UH	183	sdi = get_metadata(serial);
0aba65da UH	184	} else {
0aba65da UH	185	/* Not an OLS -- some other board that uses the sump protocol. */
72cd99b8	186	sr_info("Device does not support metadata.");
aac29cc1	187	sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be UH	188	sdi->status = SR_ST_INACTIVE;
	189	sdi->vendor = g_strdup("Sump");
	190	sdi->model = g_strdup("Logic Analyzer");
	191	sdi->version = g_strdup("v1.0");
0aba65da	192	sdi->driver = di;
07ffa5b3	193	for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
5e23fcab	194	sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
c368e6f3	195	ols_channel_names[i]);
e57057ae	196	sdi->priv = ols_dev_new();
0aba65da	197	}
bf256783 BV	198	/* Configure samplerate and divider. */
	199	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
	200	sr_dbg("Failed to set default samplerate (%"PRIu64").",
	201	DEFAULT_SAMPLERATE);
459a0f26 BV	202	sdi->inst_type = SR_INST_SERIAL;
459a0f26 BV	203	sdi->conn = serial;
bf256783	204
0aba65da UH	205	drvc->instances = g_slist_append(drvc->instances, sdi);
	206	devices = g_slist_append(devices, sdi);
	207
	208	serial_close(serial);
	209
	210	return devices;
	211	}
	212
4f840ce9	213	static GSList dev_list(const struct sr_dev_driver di)
0aba65da	214	{
41812aca	215	return ((struct drv_context *)(di->context))->instances;
0aba65da UH	216	}
0aba65da UH	217
4f840ce9	218	static int cleanup(const struct sr_dev_driver *di)
0aba65da	219	{
a6630742	220	return std_dev_clear(di, NULL);
0aba65da UH	221	}
0aba65da UH	222
584560f1	223	static int config_get(uint32_t key, GVariant *data, const struct sr_dev_inst sdi,
53b4680f	224	const struct sr_channel_group *cg)
0aba65da UH	225	{
	226	struct dev_context *devc;
	227
53b4680f	228	(void)cg;
8f996b89	229
0c05591a BV	230	if (!sdi)
	231	return SR_ERR_ARG;
	232
	233	devc = sdi->priv;
584560f1	234	switch (key) {
123e1313	235	case SR_CONF_SAMPLERATE:
0c05591a BV	236	*data = g_variant_new_uint64(devc->cur_samplerate);
	237	break;
	238	case SR_CONF_CAPTURE_RATIO:
	239	*data = g_variant_new_uint64(devc->capture_ratio);
	240	break;
	241	case SR_CONF_LIMIT_SAMPLES:
	242	*data = g_variant_new_uint64(devc->limit_samples);
	243	break;
967760a8 MR	244	case SR_CONF_PATTERN_MODE:
	245	if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
	246	*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
	247	else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
	248	*data = g_variant_new_string(STR_PATTERN_INTERNAL);
6d16fdfb BV	249	else
6d16fdfb BV	250	*data = g_variant_new_string(STR_PATTERN_NONE);
967760a8	251	break;
0c05591a BV	252	case SR_CONF_RLE:
0c05591a BV	253	*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
7730e4f0	254	break;
0aba65da	255	default:
bd6fbf62	256	return SR_ERR_NA;
0aba65da UH	257	}
	258
	259	return SR_OK;
	260	}
	261
584560f1	262	static int config_set(uint32_t key, GVariant data, const struct sr_dev_inst sdi,
53b4680f	263	const struct sr_channel_group *cg)
0aba65da UH	264	{
0aba65da UH	265	struct dev_context *devc;
6d16fdfb	266	uint16_t flag;
e46aa4f6	267	uint64_t tmp_u64;
6d16fdfb	268	int ret;
967760a8	269	const char *stropt;
0aba65da	270
53b4680f	271	(void)cg;
8f996b89	272
e73ffd42 BV	273	if (sdi->status != SR_ST_ACTIVE)
	274	return SR_ERR_DEV_CLOSED;
	275
0aba65da UH	276	devc = sdi->priv;
0aba65da UH	277
584560f1	278	switch (key) {
1953564a	279	case SR_CONF_SAMPLERATE:
e46aa4f6 BV	280	tmp_u64 = g_variant_get_uint64(data);
	281	if (tmp_u64 < samplerates[0] \|\| tmp_u64 > samplerates[1])
	282	return SR_ERR_SAMPLERATE;
	283	ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
0aba65da	284	break;
1953564a	285	case SR_CONF_LIMIT_SAMPLES:
e46aa4f6 BV	286	tmp_u64 = g_variant_get_uint64(data);
e46aa4f6 BV	287	if (tmp_u64 < MIN_NUM_SAMPLES)
0aba65da	288	return SR_ERR;
e46aa4f6	289	devc->limit_samples = tmp_u64;
0aba65da UH	290	ret = SR_OK;
0aba65da UH	291	break;
1953564a	292	case SR_CONF_CAPTURE_RATIO:
e46aa4f6	293	devc->capture_ratio = g_variant_get_uint64(data);
0aba65da UH	294	if (devc->capture_ratio < 0 \|\| devc->capture_ratio > 100) {
	295	devc->capture_ratio = 0;
	296	ret = SR_ERR;
	297	} else
	298	ret = SR_OK;
	299	break;
eb1b610b MR	300	case SR_CONF_EXTERNAL_CLOCK:
	301	if (g_variant_get_boolean(data)) {
	302	sr_info("Enabling external clock.");
	303	devc->flag_reg \|= FLAG_CLOCK_EXTERNAL;
	304	} else {
	305	sr_info("Disabled external clock.");
	306	devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
	307	}
	308	ret = SR_OK;
	309	break;
967760a8 MR	310	case SR_CONF_PATTERN_MODE:
	311	stropt = g_variant_get_string(data, NULL);
	312	ret = SR_OK;
6d16fdfb BV	313	flag = 0xffff;
	314	if (!strcmp(stropt, STR_PATTERN_NONE)) {
	315	sr_info("Disabling test modes.");
	316	flag = 0x0000;
	317	}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
967760a8	318	sr_info("Enabling internal test mode.");
6d16fdfb	319	flag = FLAG_INTERNAL_TEST_MODE;
967760a8 MR	320	} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
967760a8 MR	321	sr_info("Enabling external test mode.");
6d16fdfb	322	flag = FLAG_EXTERNAL_TEST_MODE;
967760a8 MR	323	} else {
	324	ret = SR_ERR;
	325	}
6d16fdfb BV	326	if (flag != 0xffff) {
	327	devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE \| FLAG_EXTERNAL_TEST_MODE);
	328	devc->flag_reg \|= flag;
	329	}
967760a8	330	break;
7b0a57fd MR	331	case SR_CONF_SWAP:
	332	if (g_variant_get_boolean(data)) {
	333	sr_info("Enabling channel swapping.");
3f239f08	334	devc->flag_reg \|= FLAG_SWAP_CHANNELS;
7b0a57fd MR	335	} else {
7b0a57fd MR	336	sr_info("Disabling channel swapping.");
3f239f08	337	devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
7b0a57fd MR	338	}
	339	ret = SR_OK;
	340	break;
	341
1953564a	342	case SR_CONF_RLE:
e46aa4f6	343	if (g_variant_get_boolean(data)) {
0aba65da UH	344	sr_info("Enabling RLE.");
0aba65da UH	345	devc->flag_reg \|= FLAG_RLE;
aeea0572 BV	346	} else {
	347	sr_info("Disabling RLE.");
	348	devc->flag_reg &= ~FLAG_RLE;
0aba65da UH	349	}
	350	ret = SR_OK;
	351	break;
	352	default:
bd6fbf62	353	ret = SR_ERR_NA;
0aba65da UH	354	}
	355
	356	return ret;
	357	}
	358
584560f1	359	static int config_list(uint32_t key, GVariant *data, const struct sr_dev_inst sdi,
53b4680f	360	const struct sr_channel_group *cg)
a1c743fc	361	{
f0de2dd0 BV	362	struct dev_context *devc;
f0de2dd0 BV	363	GVariant gvar, grange[2];
e46aa4f6	364	GVariantBuilder gvb;
91fd0f72	365	int num_ols_changrp, i;
a1c743fc	366
53b4680f	367	(void)cg;
a1c743fc BV	368
a1c743fc BV	369	switch (key) {
0d485e30	370	case SR_CONF_SCAN_OPTIONS:
584560f1	371	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
a0e0bb41	372	scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
0d485e30	373	break;
9a6517d1	374	case SR_CONF_DEVICE_OPTIONS:
63ea6141 BV	375	if (!sdi)
	376	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
	377	drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
	378	else
	379	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
	380	devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
9a6517d1	381	break;
a1c743fc	382	case SR_CONF_SAMPLERATE:
e46aa4f6 BV	383	g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
	384	gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
	385	ARRAY_SIZE(samplerates), sizeof(uint64_t));
	386	g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
	387	*data = g_variant_builder_end(&gvb);
a1c743fc	388	break;
91fd0f72 BV	389	case SR_CONF_TRIGGER_MATCH:
	390	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
	391	trigger_matches, ARRAY_SIZE(trigger_matches),
	392	sizeof(int32_t));
c50277a6	393	break;
7c07a178 UH	394	case SR_CONF_PATTERN_MODE:
	395	*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
	396	break;
f0de2dd0 BV	397	case SR_CONF_LIMIT_SAMPLES:
	398	if (!sdi)
	399	return SR_ERR_ARG;
	400	devc = sdi->priv;
	401	if (devc->flag_reg & FLAG_RLE)
	402	return SR_ERR_NA;
	403	if (devc->max_samples == 0)
	404	/* Device didn't specify sample memory size in metadata. */
	405	return SR_ERR_NA;
	406	/*
ba7dd8bb	407	* Channel groups are turned off if no channels in that group are
f0de2dd0 BV	408	* enabled, making more room for samples for the enabled group.
f0de2dd0 BV	409	*/
91fd0f72 BV	410	ols_channel_mask(sdi);
91fd0f72 BV	411	num_ols_changrp = 0;
f0de2dd0	412	for (i = 0; i < 4; i++) {
ba7dd8bb	413	if (devc->channel_mask & (0xff << (i * 8)))
91fd0f72	414	num_ols_changrp++;
1e1dac0c	415	}
f0de2dd0	416	grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
91fd0f72 BV	417	if (num_ols_changrp)
	418	grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
	419	else
	420	grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
f0de2dd0 BV	421	*data = g_variant_new_tuple(grange, 2);
f0de2dd0 BV	422	break;
a1c743fc	423	default:
bd6fbf62	424	return SR_ERR_NA;
a1c743fc BV	425	}
	426
	427	return SR_OK;
	428	}
	429
016e72f3 BV	430	static int set_trigger(const struct sr_dev_inst *sdi, int stage)
	431	{
	432	struct dev_context *devc;
	433	struct sr_serial_dev_inst *serial;
	434	uint8_t cmd, arg[4];
	435
	436	devc = sdi->priv;
	437	serial = sdi->conn;
	438
	439	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	440	arg[0] = devc->trigger_mask[stage] & 0xff;
	441	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	442	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	443	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	444	if (send_longcommand(serial, cmd, arg) != SR_OK)
	445	return SR_ERR;
	446
	447	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	448	arg[0] = devc->trigger_value[stage] & 0xff;
	449	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	450	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	451	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	452	if (send_longcommand(serial, cmd, arg) != SR_OK)
	453	return SR_ERR;
	454
	455	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	456	arg[0] = arg[1] = arg[3] = 0x00;
	457	arg[2] = stage;
	458	if (stage == devc->num_stages)
	459	/* Last stage, fire when this one matches. */
	460	arg[3] \|= TRIGGER_START;
	461	if (send_longcommand(serial, cmd, arg) != SR_OK)
	462	return SR_ERR;
	463
	464	return SR_OK;
	465	}
	466
03f4de8c	467	static int dev_acquisition_start(const struct sr_dev_inst *sdi,
0aba65da UH	468	void *cb_data)
0aba65da UH	469	{
0aba65da	470	struct dev_context *devc;
459a0f26	471	struct sr_serial_dev_inst *serial;
32f09bfd	472	uint16_t samplecount, readcount, delaycount;
91fd0f72 BV	473	uint8_t ols_changrp_mask, arg[4];
91fd0f72 BV	474	int num_ols_changrp;
016e72f3	475	int ret, i;
0aba65da	476
e73ffd42 BV	477	if (sdi->status != SR_ST_ACTIVE)
	478	return SR_ERR_DEV_CLOSED;
	479
0aba65da	480	devc = sdi->priv;
459a0f26	481	serial = sdi->conn;
0aba65da	482
91fd0f72	483	ols_channel_mask(sdi);
0aba65da	484
91fd0f72 BV	485	num_ols_changrp = 0;
91fd0f72 BV	486	ols_changrp_mask = 0;
0aba65da	487	for (i = 0; i < 4; i++) {
ba7dd8bb	488	if (devc->channel_mask & (0xff << (i * 8))) {
91fd0f72 BV	489	ols_changrp_mask \|= (1 << i);
91fd0f72 BV	490	num_ols_changrp++;
0aba65da UH	491	}
	492	}
	493
	494	/*
	495	* Limit readcount to prevent reading past the end of the hardware
	496	* buffer.
	497	*/
91fd0f72	498	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
32f09bfd	499	readcount = samplecount / 4;
016e72f3 BV	500
	501	/* Rather read too many samples than too few. */
	502	if (samplecount % 4 != 0)
32f09bfd	503	readcount++;
0aba65da	504
016e72f3	505	/* Basic triggers. */
91fd0f72 BV	506	if (ols_convert_trigger(sdi) != SR_OK) {
	507	sr_err("Failed to configure channels.");
	508	return SR_ERR;
	509	}
	510	if (devc->num_stages > 0) {
0aba65da UH	511	delaycount = readcount * (1 - devc->capture_ratio / 100.0);
0aba65da UH	512	devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
016e72f3	513	for (i = 0; i <= devc->num_stages; i++) {
91fd0f72	514	sr_dbg("Setting OLS stage %d trigger.", i);
016e72f3 BV	515	if ((ret = set_trigger(sdi, i)) != SR_OK)
	516	return ret;
	517	}
0aba65da	518	} else {
016e72f3 BV	519	/* No triggers configured, force trigger on first stage. */
	520	sr_dbg("Forcing trigger at stage 0.");
	521	if ((ret = set_trigger(sdi, 0)) != SR_OK)
	522	return ret;
0aba65da UH	523	delaycount = readcount;
	524	}
	525
6d16fdfb	526	/* Samplerate. */
016e72f3	527	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
6d16fdfb	528	devc->cur_samplerate, devc->cur_samplerate_divider);
016e72f3 BV	529	arg[0] = devc->cur_samplerate_divider & 0xff;
	530	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	531	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	532	arg[3] = 0x00;
	533	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
0aba65da UH	534	return SR_ERR;
	535
	536	/* Send sample limit and pre/post-trigger capture ratio. */
016e72f3	537	sr_dbg("Setting sample limit %d, trigger point at %d",
6d16fdfb	538	(readcount - 1) * 4, (delaycount - 1) * 4);
016e72f3 BV	539	arg[0] = ((readcount - 1) & 0xff);
	540	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	541	arg[2] = ((delaycount - 1) & 0xff);
	542	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	543	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
0aba65da UH	544	return SR_ERR;
0aba65da UH	545
6d16fdfb	546	/* Flag register. */
625763e2 BV	547	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
625763e2 BV	548	devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
6d16fdfb	549	devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
625763e2 BV	550	devc->flag_reg & FLAG_RLE ? "on" : "off",
	551	devc->flag_reg & FLAG_FILTER ? "on": "off",
	552	devc->flag_reg & FLAG_DEMUX ? "on" : "off");
91fd0f72 BV	553	/*
	554	* Enable/disable OLS channel groups in the flag register according
	555	* to the channel mask. 1 means "disable channel".
	556	*/
	557	devc->flag_reg \|= ~(ols_changrp_mask << 2) & 0x3c;
016e72f3 BV	558	arg[0] = devc->flag_reg & 0xff;
	559	arg[1] = devc->flag_reg >> 8;
	560	arg[2] = arg[3] = 0x00;
	561	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
0aba65da UH	562	return SR_ERR;
	563
	564	/* Start acquisition on the device. */
459a0f26	565	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
0aba65da UH	566	return SR_ERR;
0aba65da UH	567
bf256783	568	/* Reset all operational states. */
6d16fdfb BV	569	devc->rle_count = devc->num_transfers = 0;
6d16fdfb BV	570	devc->num_samples = devc->num_bytes = 0;
625763e2	571	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
abb39e6b	572	memset(devc->sample, 0, 4);
bf256783	573
4afdfd46	574	/* Send header packet to the session bus. */
29a27196	575	std_session_send_df_header(cb_data, LOG_PREFIX);
4afdfd46	576
102f1239 BV	577	serial_source_add(sdi->session, serial, G_IO_IN, -1,
102f1239 BV	578	ols_receive_data, cb_data);
0aba65da	579
0aba65da UH	580	return SR_OK;
	581	}
	582
03f4de8c	583	static int dev_acquisition_stop(struct sr_dev_inst sdi, void cb_data)
0aba65da	584	{
0aba65da UH	585	(void)cb_data;
	586
	587	abort_acquisition(sdi);
	588
	589	return SR_OK;
	590	}
	591
	592	SR_PRIV struct sr_dev_driver ols_driver_info = {
	593	.name = "ols",
	594	.longname = "Openbench Logic Sniffer",
	595	.api_version = 1,
03f4de8c	596	.init = init,
eea49cf1	597	.cleanup = cleanup,
03f4de8c BV	598	.scan = scan,
03f4de8c BV	599	.dev_list = dev_list,
a6630742	600	.dev_clear = NULL,
035a1078 BV	601	.config_get = config_get,
035a1078 BV	602	.config_set = config_set,
a1c743fc	603	.config_list = config_list,
854434de	604	.dev_open = std_serial_dev_open,
bf2c987f	605	.dev_close = std_serial_dev_close,
03f4de8c BV	606	.dev_acquisition_start = dev_acquisition_start,
03f4de8c BV	607	.dev_acquisition_stop = dev_acquisition_stop,
41812aca	608	.context = NULL,
0aba65da	609	};