[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

#define SERIALCOMM "115200/8n1"

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t scanopts[] = {
	SR_CONF_CONN,
	SR_CONF_SERIALCOMM,
};

static const uint32_t devopts[] = {
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_EXTERNAL_CLOCK | SR_CONF_SET,
	SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SWAP | SR_CONF_SET,
	SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
};

#define STR_PATTERN_NONE     "None"
#define STR_PATTERN_EXTERNAL "External"
#define STR_PATTERN_INTERNAL "Internal"

/* Supported methods of test pattern outputs */
enum {
	/**
	 * Capture pins 31:16 (unbuffered wing) output a test pattern
	 * that can captured on pins 0:15.
	 */
	PATTERN_EXTERNAL,

	/** Route test pattern internally to capture buffer. */
	PATTERN_INTERNAL,
};

static const char *patterns[] = {
	STR_PATTERN_NONE,
	STR_PATTERN_EXTERNAL,
	STR_PATTERN_INTERNAL,
};

/* Channels are numbered 0-31 (on the PCB silkscreen). */
SR_PRIV const char *ols_channel_names[] = {
	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	"24", "25", "26", "27", "28", "29", "30", "31",
};

/* Default supported samplerates, can be overridden by device metadata. */
static const uint64_t samplerates[] = {
	SR_HZ(10),
	SR_MHZ(200),
	SR_HZ(1),
};

#define RESPONSE_DELAY_US (10 * 1000)

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct sr_config *src;
	struct sr_dev_inst *sdi;
	struct sr_serial_dev_inst *serial;
	GSList *l;
	int ret;
	unsigned int i;
	const char *conn, *serialcomm;
	char buf[8];

	conn = serialcomm = NULL;
	for (l = options; l; l = l->next) {
		src = l->data;
		switch (src->key) {
		case SR_CONF_CONN:
			conn = g_variant_get_string(src->data, NULL);
			break;
		case SR_CONF_SERIALCOMM:
			serialcomm = g_variant_get_string(src->data, NULL);
			break;
		}
	}
	if (!conn)
		return NULL;

	if (!serialcomm)
		serialcomm = SERIALCOMM;

	serial = sr_serial_dev_inst_new(conn, serialcomm);

	/* The discovery procedure is like this: first send the Reset
	 * command (0x00) 5 times, since the device could be anywhere
	 * in a 5-byte command. Then send the ID command (0x02).
	 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	 * have a match.
	 */
	sr_info("Probing %s.", conn);
	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
		return NULL;

	ret = SR_OK;
	for (i = 0; i < 5; i++) {
		if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
			sr_err("Port %s is not writable.", conn);
			break;
		}
	}
	if (ret != SR_OK) {
		serial_close(serial);
		sr_err("Could not use port %s. Quitting.", conn);
		return NULL;
	}
	send_shortcommand(serial, CMD_ID);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) == 0) {
		sr_dbg("Didn't get any reply.");
		return NULL;
	}

	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	if (ret != 4) {
		sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
		return NULL;
	}

	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
		sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
		       "'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
		return NULL;
	}

	/* Definitely using the OLS protocol, check if it supports
	 * the metadata command.
	 */
	send_shortcommand(serial, CMD_METADATA);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) != 0) {
		/* Got metadata. */
		sdi = get_metadata(serial);
	} else {
		/* Not an OLS -- some other board that uses the sump protocol. */
		sr_info("Device does not support metadata.");
		sdi = g_malloc0(sizeof(struct sr_dev_inst));
		sdi->status = SR_ST_INACTIVE;
		sdi->vendor = g_strdup("Sump");
		sdi->model = g_strdup("Logic Analyzer");
		sdi->version = g_strdup("v1.0");
		for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
			sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
					ols_channel_names[i]);
		sdi->priv = ols_dev_new();
	}
	/* Configure samplerate and divider. */
	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
		sr_dbg("Failed to set default samplerate (%"PRIu64").",
				DEFAULT_SAMPLERATE);
	sdi->inst_type = SR_INST_SERIAL;
	sdi->conn = serial;

	serial_close(serial);

	return std_scan_complete(di, g_slist_append(NULL, sdi));
}

static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;

	(void)cg;

	if (!sdi)
		return SR_ERR_ARG;

	devc = sdi->priv;
	switch (key) {
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(devc->cur_samplerate);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->limit_samples);
		break;
	case SR_CONF_PATTERN_MODE:
		if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
		else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_INTERNAL);
		else
			*data = g_variant_new_string(STR_PATTERN_NONE);
		break;
	case SR_CONF_RLE:
		*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	uint16_t flag;
	uint64_t tmp_u64;
	int ret;
	const char *stropt;

	(void)cg;

	if (sdi->status != SR_ST_ACTIVE)
		return SR_ERR_DEV_CLOSED;

	devc = sdi->priv;

	switch (key) {
	case SR_CONF_SAMPLERATE:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
			return SR_ERR_SAMPLERATE;
		ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < MIN_NUM_SAMPLES)
			return SR_ERR;
		devc->limit_samples = tmp_u64;
		ret = SR_OK;
		break;
	case SR_CONF_CAPTURE_RATIO:
		devc->capture_ratio = g_variant_get_uint64(data);
		if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
			ret = SR_ERR;
		else
			ret = SR_OK;
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling external clock.");
			devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
		} else {
			sr_info("Disabled external clock.");
			devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
		}
		ret = SR_OK;
		break;
	case SR_CONF_PATTERN_MODE:
		stropt = g_variant_get_string(data, NULL);
		ret = SR_OK;
		flag = 0xffff;
		if (!strcmp(stropt, STR_PATTERN_NONE)) {
			sr_info("Disabling test modes.");
			flag = 0x0000;
		}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
			sr_info("Enabling internal test mode.");
			flag = FLAG_INTERNAL_TEST_MODE;
		} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
			sr_info("Enabling external test mode.");
			flag = FLAG_EXTERNAL_TEST_MODE;
		} else {
			ret = SR_ERR;
		}
		if (flag != 0xffff) {
			devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
			devc->flag_reg |= flag;
		}
		break;
	case SR_CONF_SWAP:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling channel swapping.");
			devc->flag_reg |= FLAG_SWAP_CHANNELS;
		} else {
			sr_info("Disabling channel swapping.");
			devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
		}
		ret = SR_OK;
		break;

	case SR_CONF_RLE:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling RLE.");
			devc->flag_reg |= FLAG_RLE;
		} else {
			sr_info("Disabling RLE.");
			devc->flag_reg &= ~FLAG_RLE;
		}
		ret = SR_OK;
		break;
	default:
		ret = SR_ERR_NA;
	}

	return ret;
}

static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
		const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	GVariant *gvar, *grange[2];
	GVariantBuilder gvb;
	int num_ols_changrp, i;

	(void)cg;

	switch (key) {
	case SR_CONF_SCAN_OPTIONS:
		*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
				scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
		break;
	case SR_CONF_DEVICE_OPTIONS:
		if (!sdi)
			*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
					drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
		else
			*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
					devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
		break;
	case SR_CONF_SAMPLERATE:
		g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
		gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
				ARRAY_SIZE(samplerates), sizeof(uint64_t));
		g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
		*data = g_variant_builder_end(&gvb);
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
				trigger_matches, ARRAY_SIZE(trigger_matches),
				sizeof(int32_t));
		break;
	case SR_CONF_PATTERN_MODE:
		*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		if (!sdi)
			return SR_ERR_ARG;
		devc = sdi->priv;
		if (devc->flag_reg & FLAG_RLE)
			return SR_ERR_NA;
		if (devc->max_samples == 0)
			/* Device didn't specify sample memory size in metadata. */
			return SR_ERR_NA;
		/*
		 * Channel groups are turned off if no channels in that group are
		 * enabled, making more room for samples for the enabled group.
		*/
		ols_channel_mask(sdi);
		num_ols_changrp = 0;
		for (i = 0; i < 4; i++) {
			if (devc->channel_mask & (0xff << (i * 8)))
				num_ols_changrp++;
		}
		grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		if (num_ols_changrp)
			grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
		else
			grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		*data = g_variant_new_tuple(grange, 2);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int set_trigger(const struct sr_dev_inst *sdi, int stage)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint8_t cmd, arg[4];

	devc = sdi->priv;
	serial = sdi->conn;

	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	arg[0] = devc->trigger_mask[stage] & 0xff;
	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	arg[0] = devc->trigger_value[stage] & 0xff;
	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	arg[0] = arg[1] = arg[3] = 0x00;
	arg[2] = stage;
	if (stage == devc->num_stages)
		/* Last stage, fire when this one matches. */
		arg[3] |= TRIGGER_START;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint16_t samplecount, readcount, delaycount;
	uint8_t ols_changrp_mask, arg[4];
	int num_ols_changrp;
	int ret, i;

	if (sdi->status != SR_ST_ACTIVE)
		return SR_ERR_DEV_CLOSED;

	devc = sdi->priv;
	serial = sdi->conn;

	ols_channel_mask(sdi);

	num_ols_changrp = 0;
	ols_changrp_mask = 0;
	for (i = 0; i < 4; i++) {
		if (devc->channel_mask & (0xff << (i * 8))) {
			ols_changrp_mask |= (1 << i);
			num_ols_changrp++;
		}
	}

	/*
	 * Limit readcount to prevent reading past the end of the hardware
	 * buffer.
	 */
	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
	readcount = samplecount / 4;

	/* Rather read too many samples than too few. */
	if (samplecount % 4 != 0)
		readcount++;

	/* Basic triggers. */
	if (ols_convert_trigger(sdi) != SR_OK) {
		sr_err("Failed to configure channels.");
		return SR_ERR;
	}
	if (devc->num_stages > 0) {
		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
		for (i = 0; i <= devc->num_stages; i++) {
			sr_dbg("Setting OLS stage %d trigger.", i);
			if ((ret = set_trigger(sdi, i)) != SR_OK)
				return ret;
		}
	} else {
		/* No triggers configured, force trigger on first stage. */
		sr_dbg("Forcing trigger at stage 0.");
		if ((ret = set_trigger(sdi, 0)) != SR_OK)
			return ret;
		delaycount = readcount;
	}

	/* Samplerate. */
	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
			devc->cur_samplerate, devc->cur_samplerate_divider);
	arg[0] = devc->cur_samplerate_divider & 0xff;
	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
		return SR_ERR;

	/* Send sample limit and pre/post-trigger capture ratio. */
	sr_dbg("Setting sample limit %d, trigger point at %d",
			(readcount - 1) * 4, (delaycount - 1) * 4);
	arg[0] = ((readcount - 1) & 0xff);
	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	arg[2] = ((delaycount - 1) & 0xff);
	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
		return SR_ERR;

	/* Flag register. */
	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
			devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_RLE ? "on" : "off",
			devc->flag_reg & FLAG_FILTER ? "on": "off",
			devc->flag_reg & FLAG_DEMUX ? "on" : "off");
	/*
	 * Enable/disable OLS channel groups in the flag register according
	 * to the channel mask. 1 means "disable channel".
	 */
	devc->flag_reg |= ~(ols_changrp_mask << 2) & 0x3c;
	arg[0] = devc->flag_reg & 0xff;
	arg[1] = devc->flag_reg >> 8;
	arg[2] = arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
		return SR_ERR;

	/* Start acquisition on the device. */
	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
		return SR_ERR;

	/* Reset all operational states. */
	devc->rle_count = devc->num_transfers = 0;
	devc->num_samples = devc->num_bytes = 0;
	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
	memset(devc->sample, 0, 4);

	std_session_send_df_header(sdi);

	/* If the device stops sending for longer than it takes to send a byte,
	 * that means it's finished. But wait at least 100 ms to be safe.
	 */
	serial_source_add(sdi->session, serial, G_IO_IN, 100,
			ols_receive_data, (struct sr_dev_inst *)sdi);

	return SR_OK;
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi)
{
	abort_acquisition(sdi);

	return SR_OK;
}

static struct sr_dev_driver ols_driver_info = {
	.name = "ols",
	.longname = "Openbench Logic Sniffer",
	.api_version = 1,
	.init = std_init,
	.cleanup = std_cleanup,
	.scan = scan,
	.dev_list = std_dev_list,
	.dev_clear = NULL,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = std_serial_dev_open,
	.dev_close = std_serial_dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
SR_REGISTER_DEV_DRIVER(ols_driver_info);
Commit	Line	Data
0aba65da	1	/*
50985c20	2	* This file is part of the libsigrok project.
0aba65da	3	*
13d8e03c	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da UH	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
6ec6c43b	20	#include <config.h>
515ab088	21	#include "protocol.h"
0aba65da UH	22
	23	#define SERIALCOMM "115200/8n1"
	24
63ea6141 BV	25	static const uint32_t drvopts[] = {
	26	SR_CONF_LOGIC_ANALYZER,
	27	};
	28
a0e0bb41	29	static const uint32_t scanopts[] = {
1953564a BV	30	SR_CONF_CONN,
1953564a BV	31	SR_CONF_SERIALCOMM,
aeabd308 UH	32	};
aeabd308 UH	33
f254bc4b	34	static const uint32_t devopts[] = {
5827f61b BV	35	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	36	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	37	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	38	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET,
	39	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_SET,
	40	SR_CONF_PATTERN_MODE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	41	SR_CONF_SWAP \| SR_CONF_SET,
	42	SR_CONF_RLE \| SR_CONF_GET \| SR_CONF_SET,
0aba65da UH	43	};
0aba65da UH	44
91fd0f72 BV	45	static const int32_t trigger_matches[] = {
	46	SR_TRIGGER_ZERO,
	47	SR_TRIGGER_ONE,
	48	};
	49
6d16fdfb BV	50	#define STR_PATTERN_NONE "None"
	51	#define STR_PATTERN_EXTERNAL "External"
	52	#define STR_PATTERN_INTERNAL "Internal"
967760a8 MR	53
	54	/* Supported methods of test pattern outputs */
	55	enum {
	56	/**
	57	* Capture pins 31:16 (unbuffered wing) output a test pattern
	58	* that can captured on pins 0:15.
	59	*/
	60	PATTERN_EXTERNAL,
	61
	62	/** Route test pattern internally to capture buffer. */
	63	PATTERN_INTERNAL,
	64	};
	65
7c07a178	66	static const char *patterns[] = {
6d16fdfb	67	STR_PATTERN_NONE,
7c07a178 UH	68	STR_PATTERN_EXTERNAL,
	69	STR_PATTERN_INTERNAL,
	70	};
	71
ba7dd8bb	72	/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a	73	SR_PRIV const char *ols_channel_names[] = {
78693401 UH	74	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	75	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	76	"24", "25", "26", "27", "28", "29", "30", "31",
0aba65da UH	77	};
0aba65da UH	78
d3b38ad3	79	/* Default supported samplerates, can be overridden by device metadata. */
e46aa4f6 BV	80	static const uint64_t samplerates[] = {
	81	SR_HZ(10),
	82	SR_MHZ(200),
	83	SR_HZ(1),
0aba65da UH	84	};
0aba65da UH	85
1a46cc62 UH	86	#define RESPONSE_DELAY_US (10 * 1000)
1a46cc62 UH	87
4f840ce9	88	static GSList scan(struct sr_dev_driver di, GSList *options)
0aba65da	89	{
1987b8d6	90	struct sr_config *src;
0aba65da	91	struct sr_dev_inst *sdi;
0aba65da	92	struct sr_serial_dev_inst *serial;
43376f33	93	GSList *l;
07ffa5b3 UH	94	int ret;
07ffa5b3 UH	95	unsigned int i;
0aba65da UH	96	const char conn, serialcomm;
	97	char buf[8];
	98
0aba65da UH	99	conn = serialcomm = NULL;
0aba65da UH	100	for (l = options; l; l = l->next) {
1987b8d6 BV	101	src = l->data;
1987b8d6 BV	102	switch (src->key) {
1953564a	103	case SR_CONF_CONN:
e46aa4f6	104	conn = g_variant_get_string(src->data, NULL);
0aba65da	105	break;
1953564a	106	case SR_CONF_SERIALCOMM:
e46aa4f6	107	serialcomm = g_variant_get_string(src->data, NULL);
0aba65da UH	108	break;
	109	}
	110	}
	111	if (!conn)
	112	return NULL;
	113
98fec29e	114	if (!serialcomm)
0aba65da UH	115	serialcomm = SERIALCOMM;
0aba65da UH	116
91219afc	117	serial = sr_serial_dev_inst_new(conn, serialcomm);
0aba65da UH	118
	119	/* The discovery procedure is like this: first send the Reset
	120	* command (0x00) 5 times, since the device could be anywhere
	121	* in a 5-byte command. Then send the ID command (0x02).
	122	* If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	123	* have a match.
	124	*/
	125	sr_info("Probing %s.", conn);
4ded59ee	126	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
0aba65da UH	127	return NULL;
	128
	129	ret = SR_OK;
	130	for (i = 0; i < 5; i++) {
	131	if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
	132	sr_err("Port %s is not writable.", conn);
	133	break;
	134	}
	135	}
	136	if (ret != SR_OK) {
	137	serial_close(serial);
	138	sr_err("Could not use port %s. Quitting.", conn);
	139	return NULL;
	140	}
	141	send_shortcommand(serial, CMD_ID);
	142
1a46cc62	143	g_usleep(RESPONSE_DELAY_US);
0aba65da	144
ed936ccc UH	145	if (sp_input_waiting(serial->data) == 0) {
ed936ccc UH	146	sr_dbg("Didn't get any reply.");
0aba65da	147	return NULL;
ed936ccc UH	148	}
	149
	150	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	151	if (ret != 4) {
	152	sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
0aba65da	153	return NULL;
ed936ccc UH	154	}
	155
	156	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
	157	sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
	158	"'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
0aba65da	159	return NULL;
ed936ccc	160	}
0aba65da UH	161
	162	/* Definitely using the OLS protocol, check if it supports
	163	* the metadata command.
	164	*/
	165	send_shortcommand(serial, CMD_METADATA);
ed936ccc	166
1a46cc62	167	g_usleep(RESPONSE_DELAY_US);
ed936ccc UH	168
ed936ccc UH	169	if (sp_input_waiting(serial->data) != 0) {
0aba65da UH	170	/* Got metadata. */
0aba65da UH	171	sdi = get_metadata(serial);
0aba65da UH	172	} else {
0aba65da UH	173	/* Not an OLS -- some other board that uses the sump protocol. */
72cd99b8	174	sr_info("Device does not support metadata.");
aac29cc1	175	sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be UH	176	sdi->status = SR_ST_INACTIVE;
	177	sdi->vendor = g_strdup("Sump");
	178	sdi->model = g_strdup("Logic Analyzer");
	179	sdi->version = g_strdup("v1.0");
07ffa5b3	180	for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
5e23fcab	181	sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
c368e6f3	182	ols_channel_names[i]);
e57057ae	183	sdi->priv = ols_dev_new();
0aba65da	184	}
bf256783 BV	185	/* Configure samplerate and divider. */
	186	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
	187	sr_dbg("Failed to set default samplerate (%"PRIu64").",
	188	DEFAULT_SAMPLERATE);
459a0f26 BV	189	sdi->inst_type = SR_INST_SERIAL;
459a0f26 BV	190	sdi->conn = serial;
bf256783	191
0aba65da UH	192	serial_close(serial);
0aba65da UH	193
43376f33	194	return std_scan_complete(di, g_slist_append(NULL, sdi));
0aba65da UH	195	}
0aba65da UH	196
584560f1	197	static int config_get(uint32_t key, GVariant *data, const struct sr_dev_inst sdi,
53b4680f	198	const struct sr_channel_group *cg)
0aba65da UH	199	{
	200	struct dev_context *devc;
	201
53b4680f	202	(void)cg;
8f996b89	203
0c05591a BV	204	if (!sdi)
	205	return SR_ERR_ARG;
	206
	207	devc = sdi->priv;
584560f1	208	switch (key) {
123e1313	209	case SR_CONF_SAMPLERATE:
0c05591a BV	210	*data = g_variant_new_uint64(devc->cur_samplerate);
	211	break;
	212	case SR_CONF_CAPTURE_RATIO:
	213	*data = g_variant_new_uint64(devc->capture_ratio);
	214	break;
	215	case SR_CONF_LIMIT_SAMPLES:
	216	*data = g_variant_new_uint64(devc->limit_samples);
	217	break;
967760a8 MR	218	case SR_CONF_PATTERN_MODE:
	219	if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
	220	*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
	221	else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
	222	*data = g_variant_new_string(STR_PATTERN_INTERNAL);
6d16fdfb BV	223	else
6d16fdfb BV	224	*data = g_variant_new_string(STR_PATTERN_NONE);
967760a8	225	break;
0c05591a BV	226	case SR_CONF_RLE:
0c05591a BV	227	*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
7730e4f0	228	break;
0aba65da	229	default:
bd6fbf62	230	return SR_ERR_NA;
0aba65da UH	231	}
	232
	233	return SR_OK;
	234	}
	235
584560f1	236	static int config_set(uint32_t key, GVariant data, const struct sr_dev_inst sdi,
53b4680f	237	const struct sr_channel_group *cg)
0aba65da UH	238	{
0aba65da UH	239	struct dev_context *devc;
6d16fdfb	240	uint16_t flag;
e46aa4f6	241	uint64_t tmp_u64;
6d16fdfb	242	int ret;
967760a8	243	const char *stropt;
0aba65da	244
53b4680f	245	(void)cg;
8f996b89	246
e73ffd42 BV	247	if (sdi->status != SR_ST_ACTIVE)
	248	return SR_ERR_DEV_CLOSED;
	249
0aba65da UH	250	devc = sdi->priv;
0aba65da UH	251
584560f1	252	switch (key) {
1953564a	253	case SR_CONF_SAMPLERATE:
e46aa4f6 BV	254	tmp_u64 = g_variant_get_uint64(data);
	255	if (tmp_u64 < samplerates[0] \|\| tmp_u64 > samplerates[1])
	256	return SR_ERR_SAMPLERATE;
	257	ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
0aba65da	258	break;
1953564a	259	case SR_CONF_LIMIT_SAMPLES:
e46aa4f6 BV	260	tmp_u64 = g_variant_get_uint64(data);
e46aa4f6 BV	261	if (tmp_u64 < MIN_NUM_SAMPLES)
0aba65da	262	return SR_ERR;
e46aa4f6	263	devc->limit_samples = tmp_u64;
0aba65da UH	264	ret = SR_OK;
0aba65da UH	265	break;
1953564a	266	case SR_CONF_CAPTURE_RATIO:
e46aa4f6	267	devc->capture_ratio = g_variant_get_uint64(data);
a5c38703	268	if (devc->capture_ratio < 0 \|\| devc->capture_ratio > 100)
0aba65da	269	ret = SR_ERR;
a5c38703	270	else
0aba65da UH	271	ret = SR_OK;
0aba65da UH	272	break;
eb1b610b MR	273	case SR_CONF_EXTERNAL_CLOCK:
	274	if (g_variant_get_boolean(data)) {
	275	sr_info("Enabling external clock.");
	276	devc->flag_reg \|= FLAG_CLOCK_EXTERNAL;
	277	} else {
	278	sr_info("Disabled external clock.");
	279	devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
	280	}
	281	ret = SR_OK;
	282	break;
967760a8 MR	283	case SR_CONF_PATTERN_MODE:
	284	stropt = g_variant_get_string(data, NULL);
	285	ret = SR_OK;
6d16fdfb BV	286	flag = 0xffff;
	287	if (!strcmp(stropt, STR_PATTERN_NONE)) {
	288	sr_info("Disabling test modes.");
	289	flag = 0x0000;
	290	}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
967760a8	291	sr_info("Enabling internal test mode.");
6d16fdfb	292	flag = FLAG_INTERNAL_TEST_MODE;
967760a8 MR	293	} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
967760a8 MR	294	sr_info("Enabling external test mode.");
6d16fdfb	295	flag = FLAG_EXTERNAL_TEST_MODE;
967760a8 MR	296	} else {
	297	ret = SR_ERR;
	298	}
6d16fdfb BV	299	if (flag != 0xffff) {
	300	devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE \| FLAG_EXTERNAL_TEST_MODE);
	301	devc->flag_reg \|= flag;
	302	}
967760a8	303	break;
7b0a57fd MR	304	case SR_CONF_SWAP:
	305	if (g_variant_get_boolean(data)) {
	306	sr_info("Enabling channel swapping.");
3f239f08	307	devc->flag_reg \|= FLAG_SWAP_CHANNELS;
7b0a57fd MR	308	} else {
7b0a57fd MR	309	sr_info("Disabling channel swapping.");
3f239f08	310	devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
7b0a57fd MR	311	}
	312	ret = SR_OK;
	313	break;
	314
1953564a	315	case SR_CONF_RLE:
e46aa4f6	316	if (g_variant_get_boolean(data)) {
0aba65da UH	317	sr_info("Enabling RLE.");
0aba65da UH	318	devc->flag_reg \|= FLAG_RLE;
aeea0572 BV	319	} else {
	320	sr_info("Disabling RLE.");
	321	devc->flag_reg &= ~FLAG_RLE;
0aba65da UH	322	}
	323	ret = SR_OK;
	324	break;
	325	default:
bd6fbf62	326	ret = SR_ERR_NA;
0aba65da UH	327	}
	328
	329	return ret;
	330	}
	331
584560f1	332	static int config_list(uint32_t key, GVariant *data, const struct sr_dev_inst sdi,
53b4680f	333	const struct sr_channel_group *cg)
a1c743fc	334	{
f0de2dd0 BV	335	struct dev_context *devc;
f0de2dd0 BV	336	GVariant gvar, grange[2];
e46aa4f6	337	GVariantBuilder gvb;
91fd0f72	338	int num_ols_changrp, i;
a1c743fc	339
53b4680f	340	(void)cg;
a1c743fc BV	341
a1c743fc BV	342	switch (key) {
0d485e30	343	case SR_CONF_SCAN_OPTIONS:
584560f1	344	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
a0e0bb41	345	scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
0d485e30	346	break;
9a6517d1	347	case SR_CONF_DEVICE_OPTIONS:
63ea6141 BV	348	if (!sdi)
	349	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
	350	drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
	351	else
	352	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
	353	devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
9a6517d1	354	break;
a1c743fc	355	case SR_CONF_SAMPLERATE:
e46aa4f6 BV	356	g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
	357	gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
	358	ARRAY_SIZE(samplerates), sizeof(uint64_t));
	359	g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
	360	*data = g_variant_builder_end(&gvb);
a1c743fc	361	break;
91fd0f72 BV	362	case SR_CONF_TRIGGER_MATCH:
	363	*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
	364	trigger_matches, ARRAY_SIZE(trigger_matches),
	365	sizeof(int32_t));
c50277a6	366	break;
7c07a178 UH	367	case SR_CONF_PATTERN_MODE:
	368	*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
	369	break;
f0de2dd0 BV	370	case SR_CONF_LIMIT_SAMPLES:
	371	if (!sdi)
	372	return SR_ERR_ARG;
	373	devc = sdi->priv;
	374	if (devc->flag_reg & FLAG_RLE)
	375	return SR_ERR_NA;
	376	if (devc->max_samples == 0)
	377	/* Device didn't specify sample memory size in metadata. */
	378	return SR_ERR_NA;
	379	/*
ba7dd8bb	380	* Channel groups are turned off if no channels in that group are
f0de2dd0 BV	381	* enabled, making more room for samples for the enabled group.
f0de2dd0 BV	382	*/
91fd0f72 BV	383	ols_channel_mask(sdi);
91fd0f72 BV	384	num_ols_changrp = 0;
f0de2dd0	385	for (i = 0; i < 4; i++) {
ba7dd8bb	386	if (devc->channel_mask & (0xff << (i * 8)))
91fd0f72	387	num_ols_changrp++;
1e1dac0c	388	}
f0de2dd0	389	grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
91fd0f72 BV	390	if (num_ols_changrp)
	391	grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
	392	else
	393	grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
f0de2dd0 BV	394	*data = g_variant_new_tuple(grange, 2);
f0de2dd0 BV	395	break;
a1c743fc	396	default:
bd6fbf62	397	return SR_ERR_NA;
a1c743fc BV	398	}
	399
	400	return SR_OK;
	401	}
	402
016e72f3 BV	403	static int set_trigger(const struct sr_dev_inst *sdi, int stage)
	404	{
	405	struct dev_context *devc;
	406	struct sr_serial_dev_inst *serial;
	407	uint8_t cmd, arg[4];
	408
	409	devc = sdi->priv;
	410	serial = sdi->conn;
	411
	412	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	413	arg[0] = devc->trigger_mask[stage] & 0xff;
	414	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	415	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	416	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	417	if (send_longcommand(serial, cmd, arg) != SR_OK)
	418	return SR_ERR;
	419
	420	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	421	arg[0] = devc->trigger_value[stage] & 0xff;
	422	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	423	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	424	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	425	if (send_longcommand(serial, cmd, arg) != SR_OK)
	426	return SR_ERR;
	427
	428	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	429	arg[0] = arg[1] = arg[3] = 0x00;
	430	arg[2] = stage;
	431	if (stage == devc->num_stages)
	432	/* Last stage, fire when this one matches. */
	433	arg[3] \|= TRIGGER_START;
	434	if (send_longcommand(serial, cmd, arg) != SR_OK)
	435	return SR_ERR;
	436
	437	return SR_OK;
	438	}
	439
695dc859	440	static int dev_acquisition_start(const struct sr_dev_inst *sdi)
0aba65da	441	{
0aba65da	442	struct dev_context *devc;
459a0f26	443	struct sr_serial_dev_inst *serial;
32f09bfd	444	uint16_t samplecount, readcount, delaycount;
91fd0f72 BV	445	uint8_t ols_changrp_mask, arg[4];
91fd0f72 BV	446	int num_ols_changrp;
016e72f3	447	int ret, i;
0aba65da	448
e73ffd42 BV	449	if (sdi->status != SR_ST_ACTIVE)
	450	return SR_ERR_DEV_CLOSED;
	451
0aba65da	452	devc = sdi->priv;
459a0f26	453	serial = sdi->conn;
0aba65da	454
91fd0f72	455	ols_channel_mask(sdi);
0aba65da	456
91fd0f72 BV	457	num_ols_changrp = 0;
91fd0f72 BV	458	ols_changrp_mask = 0;
0aba65da	459	for (i = 0; i < 4; i++) {
ba7dd8bb	460	if (devc->channel_mask & (0xff << (i * 8))) {
91fd0f72 BV	461	ols_changrp_mask \|= (1 << i);
91fd0f72 BV	462	num_ols_changrp++;
0aba65da UH	463	}
	464	}
	465
	466	/*
	467	* Limit readcount to prevent reading past the end of the hardware
	468	* buffer.
	469	*/
91fd0f72	470	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
32f09bfd	471	readcount = samplecount / 4;
016e72f3 BV	472
	473	/* Rather read too many samples than too few. */
	474	if (samplecount % 4 != 0)
32f09bfd	475	readcount++;
0aba65da	476
016e72f3	477	/* Basic triggers. */
91fd0f72 BV	478	if (ols_convert_trigger(sdi) != SR_OK) {
	479	sr_err("Failed to configure channels.");
	480	return SR_ERR;
	481	}
	482	if (devc->num_stages > 0) {
0aba65da UH	483	delaycount = readcount * (1 - devc->capture_ratio / 100.0);
0aba65da UH	484	devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
016e72f3	485	for (i = 0; i <= devc->num_stages; i++) {
91fd0f72	486	sr_dbg("Setting OLS stage %d trigger.", i);
016e72f3 BV	487	if ((ret = set_trigger(sdi, i)) != SR_OK)
	488	return ret;
	489	}
0aba65da	490	} else {
016e72f3 BV	491	/* No triggers configured, force trigger on first stage. */
	492	sr_dbg("Forcing trigger at stage 0.");
	493	if ((ret = set_trigger(sdi, 0)) != SR_OK)
	494	return ret;
0aba65da UH	495	delaycount = readcount;
	496	}
	497
6d16fdfb	498	/* Samplerate. */
016e72f3	499	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
6d16fdfb	500	devc->cur_samplerate, devc->cur_samplerate_divider);
016e72f3 BV	501	arg[0] = devc->cur_samplerate_divider & 0xff;
	502	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	503	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	504	arg[3] = 0x00;
	505	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
0aba65da UH	506	return SR_ERR;
	507
	508	/* Send sample limit and pre/post-trigger capture ratio. */
016e72f3	509	sr_dbg("Setting sample limit %d, trigger point at %d",
6d16fdfb	510	(readcount - 1) * 4, (delaycount - 1) * 4);
016e72f3 BV	511	arg[0] = ((readcount - 1) & 0xff);
	512	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	513	arg[2] = ((delaycount - 1) & 0xff);
	514	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	515	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
0aba65da UH	516	return SR_ERR;
0aba65da UH	517
6d16fdfb	518	/* Flag register. */
625763e2 BV	519	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
625763e2 BV	520	devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
6d16fdfb	521	devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
625763e2 BV	522	devc->flag_reg & FLAG_RLE ? "on" : "off",
	523	devc->flag_reg & FLAG_FILTER ? "on": "off",
	524	devc->flag_reg & FLAG_DEMUX ? "on" : "off");
91fd0f72 BV	525	/*
	526	* Enable/disable OLS channel groups in the flag register according
	527	* to the channel mask. 1 means "disable channel".
	528	*/
	529	devc->flag_reg \|= ~(ols_changrp_mask << 2) & 0x3c;
016e72f3 BV	530	arg[0] = devc->flag_reg & 0xff;
	531	arg[1] = devc->flag_reg >> 8;
	532	arg[2] = arg[3] = 0x00;
	533	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
0aba65da UH	534	return SR_ERR;
	535
	536	/* Start acquisition on the device. */
459a0f26	537	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
0aba65da UH	538	return SR_ERR;
0aba65da UH	539
bf256783	540	/* Reset all operational states. */
6d16fdfb BV	541	devc->rle_count = devc->num_transfers = 0;
6d16fdfb BV	542	devc->num_samples = devc->num_bytes = 0;
625763e2	543	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
abb39e6b	544	memset(devc->sample, 0, 4);
bf256783	545
bee2b016	546	std_session_send_df_header(sdi);
4afdfd46	547
8105e829 DE	548	/* If the device stops sending for longer than it takes to send a byte,
	549	* that means it's finished. But wait at least 100 ms to be safe.
	550	*/
	551	serial_source_add(sdi->session, serial, G_IO_IN, 100,
695dc859	552	ols_receive_data, (struct sr_dev_inst *)sdi);
0aba65da	553
0aba65da UH	554	return SR_OK;
	555	}
	556
695dc859	557	static int dev_acquisition_stop(struct sr_dev_inst *sdi)
0aba65da	558	{
0aba65da UH	559	abort_acquisition(sdi);
	560
	561	return SR_OK;
	562	}
	563
15a5bfe4	564	static struct sr_dev_driver ols_driver_info = {
0aba65da UH	565	.name = "ols",
	566	.longname = "Openbench Logic Sniffer",
	567	.api_version = 1,
c2fdcc25	568	.init = std_init,
700d6b64	569	.cleanup = std_cleanup,
03f4de8c	570	.scan = scan,
c01bf34c	571	.dev_list = std_dev_list,
a6630742	572	.dev_clear = NULL,
035a1078 BV	573	.config_get = config_get,
035a1078 BV	574	.config_set = config_set,
a1c743fc	575	.config_list = config_list,
854434de	576	.dev_open = std_serial_dev_open,
bf2c987f	577	.dev_close = std_serial_dev_close,
03f4de8c BV	578	.dev_acquisition_start = dev_acquisition_start,
03f4de8c BV	579	.dev_acquisition_stop = dev_acquisition_stop,
41812aca	580	.context = NULL,
0aba65da	581	};
dd5c48a6	582	SR_REGISTER_DEV_DRIVER(ols_driver_info);