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ols: use 32bit for handling sample counts
[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c
CommitLineData
0aba65da 1/*
50985c20 2 * This file is part of the libsigrok project.
0aba65da 3 *
13d8e03c 4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
515ab088 21#include "protocol.h"
0aba65da
UH
22
23#define SERIALCOMM "115200/8n1"
24
a0e0bb41 25static const uint32_t scanopts[] = {
1953564a
BV
26 SR_CONF_CONN,
27 SR_CONF_SERIALCOMM,
aeabd308
UH
28};
29
55fb76b3
UH
30static const uint32_t drvopts[] = {
31 SR_CONF_LOGIC_ANALYZER,
32};
33
f254bc4b 34static const uint32_t devopts[] = {
5827f61b
BV
35 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
36 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
37 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
38 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
39 SR_CONF_EXTERNAL_CLOCK | SR_CONF_SET,
40 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
41 SR_CONF_SWAP | SR_CONF_SET,
42 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
0aba65da
UH
43};
44
91fd0f72
BV
45static const int32_t trigger_matches[] = {
46 SR_TRIGGER_ZERO,
47 SR_TRIGGER_ONE,
48};
49
6d16fdfb
BV
50#define STR_PATTERN_NONE "None"
51#define STR_PATTERN_EXTERNAL "External"
52#define STR_PATTERN_INTERNAL "Internal"
967760a8
MR
53
54/* Supported methods of test pattern outputs */
55enum {
56 /**
57 * Capture pins 31:16 (unbuffered wing) output a test pattern
58 * that can captured on pins 0:15.
59 */
60 PATTERN_EXTERNAL,
61
62 /** Route test pattern internally to capture buffer. */
63 PATTERN_INTERNAL,
64};
65
7c07a178 66static const char *patterns[] = {
6d16fdfb 67 STR_PATTERN_NONE,
7c07a178
UH
68 STR_PATTERN_EXTERNAL,
69 STR_PATTERN_INTERNAL,
70};
71
ba7dd8bb 72/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a 73SR_PRIV const char *ols_channel_names[] = {
78693401
UH
74 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
75 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
76 "24", "25", "26", "27", "28", "29", "30", "31",
0aba65da
UH
77};
78
d3b38ad3 79/* Default supported samplerates, can be overridden by device metadata. */
e46aa4f6
BV
80static const uint64_t samplerates[] = {
81 SR_HZ(10),
82 SR_MHZ(200),
83 SR_HZ(1),
0aba65da
UH
84};
85
1a46cc62
UH
86#define RESPONSE_DELAY_US (10 * 1000)
87
4f840ce9 88static GSList *scan(struct sr_dev_driver *di, GSList *options)
0aba65da 89{
1987b8d6 90 struct sr_config *src;
0aba65da 91 struct sr_dev_inst *sdi;
0aba65da 92 struct sr_serial_dev_inst *serial;
43376f33 93 GSList *l;
07ffa5b3
UH
94 int ret;
95 unsigned int i;
0aba65da
UH
96 const char *conn, *serialcomm;
97 char buf[8];
98
0aba65da
UH
99 conn = serialcomm = NULL;
100 for (l = options; l; l = l->next) {
1987b8d6
BV
101 src = l->data;
102 switch (src->key) {
1953564a 103 case SR_CONF_CONN:
e46aa4f6 104 conn = g_variant_get_string(src->data, NULL);
0aba65da 105 break;
1953564a 106 case SR_CONF_SERIALCOMM:
e46aa4f6 107 serialcomm = g_variant_get_string(src->data, NULL);
0aba65da
UH
108 break;
109 }
110 }
111 if (!conn)
112 return NULL;
113
98fec29e 114 if (!serialcomm)
0aba65da
UH
115 serialcomm = SERIALCOMM;
116
91219afc 117 serial = sr_serial_dev_inst_new(conn, serialcomm);
0aba65da
UH
118
119 /* The discovery procedure is like this: first send the Reset
120 * command (0x00) 5 times, since the device could be anywhere
121 * in a 5-byte command. Then send the ID command (0x02).
122 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
123 * have a match.
124 */
125 sr_info("Probing %s.", conn);
4ded59ee 126 if (serial_open(serial, SERIAL_RDWR) != SR_OK)
0aba65da
UH
127 return NULL;
128
244995a2 129 if (ols_send_reset(serial) != SR_OK) {
0aba65da
UH
130 serial_close(serial);
131 sr_err("Could not use port %s. Quitting.", conn);
132 return NULL;
133 }
134 send_shortcommand(serial, CMD_ID);
135
1a46cc62 136 g_usleep(RESPONSE_DELAY_US);
0aba65da 137
ed936ccc
UH
138 if (sp_input_waiting(serial->data) == 0) {
139 sr_dbg("Didn't get any reply.");
0aba65da 140 return NULL;
ed936ccc
UH
141 }
142
143 ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
144 if (ret != 4) {
145 sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
0aba65da 146 return NULL;
ed936ccc
UH
147 }
148
149 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
150 sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
151 "'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
0aba65da 152 return NULL;
ed936ccc 153 }
0aba65da
UH
154
155 /* Definitely using the OLS protocol, check if it supports
156 * the metadata command.
157 */
158 send_shortcommand(serial, CMD_METADATA);
ed936ccc 159
1a46cc62 160 g_usleep(RESPONSE_DELAY_US);
ed936ccc
UH
161
162 if (sp_input_waiting(serial->data) != 0) {
0aba65da
UH
163 /* Got metadata. */
164 sdi = get_metadata(serial);
0aba65da
UH
165 } else {
166 /* Not an OLS -- some other board that uses the sump protocol. */
72cd99b8 167 sr_info("Device does not support metadata.");
aac29cc1 168 sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be
UH
169 sdi->status = SR_ST_INACTIVE;
170 sdi->vendor = g_strdup("Sump");
171 sdi->model = g_strdup("Logic Analyzer");
172 sdi->version = g_strdup("v1.0");
07ffa5b3 173 for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
5e23fcab 174 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
c368e6f3 175 ols_channel_names[i]);
e57057ae 176 sdi->priv = ols_dev_new();
0aba65da 177 }
bf256783
BV
178 /* Configure samplerate and divider. */
179 if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
180 sr_dbg("Failed to set default samplerate (%"PRIu64").",
181 DEFAULT_SAMPLERATE);
459a0f26
BV
182 sdi->inst_type = SR_INST_SERIAL;
183 sdi->conn = serial;
bf256783 184
0aba65da
UH
185 serial_close(serial);
186
43376f33 187 return std_scan_complete(di, g_slist_append(NULL, sdi));
0aba65da
UH
188}
189
dd7a72ea
UH
190static int config_get(uint32_t key, GVariant **data,
191 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
0aba65da
UH
192{
193 struct dev_context *devc;
194
53b4680f 195 (void)cg;
8f996b89 196
0c05591a
BV
197 if (!sdi)
198 return SR_ERR_ARG;
199
200 devc = sdi->priv;
758906aa 201
584560f1 202 switch (key) {
123e1313 203 case SR_CONF_SAMPLERATE:
0c05591a
BV
204 *data = g_variant_new_uint64(devc->cur_samplerate);
205 break;
206 case SR_CONF_CAPTURE_RATIO:
207 *data = g_variant_new_uint64(devc->capture_ratio);
208 break;
209 case SR_CONF_LIMIT_SAMPLES:
210 *data = g_variant_new_uint64(devc->limit_samples);
211 break;
967760a8
MR
212 case SR_CONF_PATTERN_MODE:
213 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
214 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
215 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
216 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
6d16fdfb
BV
217 else
218 *data = g_variant_new_string(STR_PATTERN_NONE);
967760a8 219 break;
0c05591a
BV
220 case SR_CONF_RLE:
221 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
7730e4f0 222 break;
0aba65da 223 default:
bd6fbf62 224 return SR_ERR_NA;
0aba65da
UH
225 }
226
227 return SR_OK;
228}
229
dd7a72ea
UH
230static int config_set(uint32_t key, GVariant *data,
231 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
0aba65da
UH
232{
233 struct dev_context *devc;
6d16fdfb 234 uint16_t flag;
e46aa4f6 235 uint64_t tmp_u64;
967760a8 236 const char *stropt;
0aba65da 237
53b4680f 238 (void)cg;
8f996b89 239
0aba65da
UH
240 devc = sdi->priv;
241
584560f1 242 switch (key) {
1953564a 243 case SR_CONF_SAMPLERATE:
e46aa4f6
BV
244 tmp_u64 = g_variant_get_uint64(data);
245 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
246 return SR_ERR_SAMPLERATE;
758906aa 247 return ols_set_samplerate(sdi, g_variant_get_uint64(data));
1953564a 248 case SR_CONF_LIMIT_SAMPLES:
e46aa4f6
BV
249 tmp_u64 = g_variant_get_uint64(data);
250 if (tmp_u64 < MIN_NUM_SAMPLES)
0aba65da 251 return SR_ERR;
e46aa4f6 252 devc->limit_samples = tmp_u64;
0aba65da 253 break;
1953564a 254 case SR_CONF_CAPTURE_RATIO:
e46aa4f6 255 devc->capture_ratio = g_variant_get_uint64(data);
0aba65da 256 break;
eb1b610b
MR
257 case SR_CONF_EXTERNAL_CLOCK:
258 if (g_variant_get_boolean(data)) {
259 sr_info("Enabling external clock.");
260 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
261 } else {
262 sr_info("Disabled external clock.");
263 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
264 }
eb1b610b 265 break;
967760a8
MR
266 case SR_CONF_PATTERN_MODE:
267 stropt = g_variant_get_string(data, NULL);
6d16fdfb
BV
268 if (!strcmp(stropt, STR_PATTERN_NONE)) {
269 sr_info("Disabling test modes.");
270 flag = 0x0000;
758906aa 271 } else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
967760a8 272 sr_info("Enabling internal test mode.");
6d16fdfb 273 flag = FLAG_INTERNAL_TEST_MODE;
967760a8
MR
274 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
275 sr_info("Enabling external test mode.");
6d16fdfb 276 flag = FLAG_EXTERNAL_TEST_MODE;
967760a8 277 } else {
758906aa 278 return SR_ERR;
967760a8 279 }
b04cbd0b
GS
280 devc->flag_reg &= ~FLAG_INTERNAL_TEST_MODE;
281 devc->flag_reg &= ~FLAG_EXTERNAL_TEST_MODE;
282 devc->flag_reg |= flag;
967760a8 283 break;
7b0a57fd
MR
284 case SR_CONF_SWAP:
285 if (g_variant_get_boolean(data)) {
286 sr_info("Enabling channel swapping.");
3f239f08 287 devc->flag_reg |= FLAG_SWAP_CHANNELS;
7b0a57fd
MR
288 } else {
289 sr_info("Disabling channel swapping.");
3f239f08 290 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
7b0a57fd 291 }
7b0a57fd 292 break;
1953564a 293 case SR_CONF_RLE:
e46aa4f6 294 if (g_variant_get_boolean(data)) {
0aba65da
UH
295 sr_info("Enabling RLE.");
296 devc->flag_reg |= FLAG_RLE;
aeea0572
BV
297 } else {
298 sr_info("Disabling RLE.");
299 devc->flag_reg &= ~FLAG_RLE;
0aba65da 300 }
0aba65da
UH
301 break;
302 default:
758906aa 303 return SR_ERR_NA;
0aba65da
UH
304 }
305
758906aa 306 return SR_OK;
0aba65da
UH
307}
308
dd7a72ea
UH
309static int config_list(uint32_t key, GVariant **data,
310 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
a1c743fc 311{
f0de2dd0 312 struct dev_context *devc;
91fd0f72 313 int num_ols_changrp, i;
a1c743fc 314
a1c743fc 315 switch (key) {
0d485e30 316 case SR_CONF_SCAN_OPTIONS:
9a6517d1 317 case SR_CONF_DEVICE_OPTIONS:
e66d1892 318 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
a1c743fc 319 case SR_CONF_SAMPLERATE:
53012da6 320 *data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates));
a1c743fc 321 break;
91fd0f72 322 case SR_CONF_TRIGGER_MATCH:
53012da6 323 *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
c50277a6 324 break;
7c07a178 325 case SR_CONF_PATTERN_MODE:
53012da6 326 *data = g_variant_new_strv(ARRAY_AND_SIZE(patterns));
7c07a178 327 break;
f0de2dd0
BV
328 case SR_CONF_LIMIT_SAMPLES:
329 if (!sdi)
330 return SR_ERR_ARG;
331 devc = sdi->priv;
332 if (devc->flag_reg & FLAG_RLE)
333 return SR_ERR_NA;
334 if (devc->max_samples == 0)
335 /* Device didn't specify sample memory size in metadata. */
336 return SR_ERR_NA;
337 /*
ba7dd8bb 338 * Channel groups are turned off if no channels in that group are
f0de2dd0
BV
339 * enabled, making more room for samples for the enabled group.
340 */
91fd0f72
BV
341 ols_channel_mask(sdi);
342 num_ols_changrp = 0;
f0de2dd0 343 for (i = 0; i < 4; i++) {
ba7dd8bb 344 if (devc->channel_mask & (0xff << (i * 8)))
91fd0f72 345 num_ols_changrp++;
1e1dac0c 346 }
a162eeb2
UH
347
348 *data = std_gvar_tuple_u64(MIN_NUM_SAMPLES,
349 (num_ols_changrp) ? devc->max_samples / num_ols_changrp : MIN_NUM_SAMPLES);
f0de2dd0 350 break;
a1c743fc 351 default:
bd6fbf62 352 return SR_ERR_NA;
a1c743fc
BV
353 }
354
355 return SR_OK;
356}
357
016e72f3
BV
358static int set_trigger(const struct sr_dev_inst *sdi, int stage)
359{
360 struct dev_context *devc;
361 struct sr_serial_dev_inst *serial;
362 uint8_t cmd, arg[4];
363
364 devc = sdi->priv;
365 serial = sdi->conn;
366
367 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
368 arg[0] = devc->trigger_mask[stage] & 0xff;
369 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
370 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
371 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
372 if (send_longcommand(serial, cmd, arg) != SR_OK)
373 return SR_ERR;
374
375 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
376 arg[0] = devc->trigger_value[stage] & 0xff;
377 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
378 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
379 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
380 if (send_longcommand(serial, cmd, arg) != SR_OK)
381 return SR_ERR;
382
383 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
384 arg[0] = arg[1] = arg[3] = 0x00;
385 arg[2] = stage;
386 if (stage == devc->num_stages)
387 /* Last stage, fire when this one matches. */
388 arg[3] |= TRIGGER_START;
389 if (send_longcommand(serial, cmd, arg) != SR_OK)
390 return SR_ERR;
391
392 return SR_OK;
393}
394
695dc859 395static int dev_acquisition_start(const struct sr_dev_inst *sdi)
0aba65da 396{
0aba65da 397 struct dev_context *devc;
459a0f26 398 struct sr_serial_dev_inst *serial;
6e5a1a01 399 uint32_t samplecount, readcount, delaycount;
91fd0f72
BV
400 uint8_t ols_changrp_mask, arg[4];
401 int num_ols_changrp;
016e72f3 402 int ret, i;
0aba65da
UH
403
404 devc = sdi->priv;
459a0f26 405 serial = sdi->conn;
0aba65da 406
91fd0f72 407 ols_channel_mask(sdi);
0aba65da 408
91fd0f72
BV
409 num_ols_changrp = 0;
410 ols_changrp_mask = 0;
0aba65da 411 for (i = 0; i < 4; i++) {
ba7dd8bb 412 if (devc->channel_mask & (0xff << (i * 8))) {
91fd0f72
BV
413 ols_changrp_mask |= (1 << i);
414 num_ols_changrp++;
0aba65da
UH
415 }
416 }
417
418 /*
419 * Limit readcount to prevent reading past the end of the hardware
420 * buffer.
421 */
91fd0f72 422 samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
32f09bfd 423 readcount = samplecount / 4;
016e72f3
BV
424
425 /* Rather read too many samples than too few. */
426 if (samplecount % 4 != 0)
32f09bfd 427 readcount++;
0aba65da 428
016e72f3 429 /* Basic triggers. */
91fd0f72
BV
430 if (ols_convert_trigger(sdi) != SR_OK) {
431 sr_err("Failed to configure channels.");
432 return SR_ERR;
433 }
434 if (devc->num_stages > 0) {
b853eb76
GGM
435 /*
436 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
437 * reset command must be send prior each arm command
438 */
439 sr_dbg("Send reset command before trigger configure");
440 if (ols_send_reset(serial) != SR_OK)
441 return SR_ERR;
442
0aba65da
UH
443 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
444 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
016e72f3 445 for (i = 0; i <= devc->num_stages; i++) {
91fd0f72 446 sr_dbg("Setting OLS stage %d trigger.", i);
016e72f3
BV
447 if ((ret = set_trigger(sdi, i)) != SR_OK)
448 return ret;
449 }
0aba65da 450 } else {
016e72f3
BV
451 /* No triggers configured, force trigger on first stage. */
452 sr_dbg("Forcing trigger at stage 0.");
453 if ((ret = set_trigger(sdi, 0)) != SR_OK)
454 return ret;
0aba65da
UH
455 delaycount = readcount;
456 }
457
6d16fdfb 458 /* Samplerate. */
016e72f3 459 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
6d16fdfb 460 devc->cur_samplerate, devc->cur_samplerate_divider);
016e72f3
BV
461 arg[0] = devc->cur_samplerate_divider & 0xff;
462 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
463 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
464 arg[3] = 0x00;
465 if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
0aba65da
UH
466 return SR_ERR;
467
468 /* Send sample limit and pre/post-trigger capture ratio. */
016e72f3 469 sr_dbg("Setting sample limit %d, trigger point at %d",
6d16fdfb 470 (readcount - 1) * 4, (delaycount - 1) * 4);
016e72f3
BV
471 arg[0] = ((readcount - 1) & 0xff);
472 arg[1] = ((readcount - 1) & 0xff00) >> 8;
473 arg[2] = ((delaycount - 1) & 0xff);
474 arg[3] = ((delaycount - 1) & 0xff00) >> 8;
475 if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
0aba65da
UH
476 return SR_ERR;
477
6d16fdfb 478 /* Flag register. */
625763e2
BV
479 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
480 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
6d16fdfb 481 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
625763e2
BV
482 devc->flag_reg & FLAG_RLE ? "on" : "off",
483 devc->flag_reg & FLAG_FILTER ? "on": "off",
484 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
91fd0f72
BV
485 /*
486 * Enable/disable OLS channel groups in the flag register according
487 * to the channel mask. 1 means "disable channel".
488 */
489 devc->flag_reg |= ~(ols_changrp_mask << 2) & 0x3c;
016e72f3
BV
490 arg[0] = devc->flag_reg & 0xff;
491 arg[1] = devc->flag_reg >> 8;
492 arg[2] = arg[3] = 0x00;
493 if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
0aba65da
UH
494 return SR_ERR;
495
496 /* Start acquisition on the device. */
459a0f26 497 if (send_shortcommand(serial, CMD_RUN) != SR_OK)
0aba65da
UH
498 return SR_ERR;
499
bf256783 500 /* Reset all operational states. */
6d16fdfb
BV
501 devc->rle_count = devc->num_transfers = 0;
502 devc->num_samples = devc->num_bytes = 0;
625763e2 503 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
abb39e6b 504 memset(devc->sample, 0, 4);
bf256783 505
bee2b016 506 std_session_send_df_header(sdi);
4afdfd46 507
8105e829
DE
508 /* If the device stops sending for longer than it takes to send a byte,
509 * that means it's finished. But wait at least 100 ms to be safe.
510 */
511 serial_source_add(sdi->session, serial, G_IO_IN, 100,
695dc859 512 ols_receive_data, (struct sr_dev_inst *)sdi);
0aba65da 513
0aba65da
UH
514 return SR_OK;
515}
516
695dc859 517static int dev_acquisition_stop(struct sr_dev_inst *sdi)
0aba65da 518{
0aba65da
UH
519 abort_acquisition(sdi);
520
521 return SR_OK;
522}
523
15a5bfe4 524static struct sr_dev_driver ols_driver_info = {
0aba65da
UH
525 .name = "ols",
526 .longname = "Openbench Logic Sniffer",
527 .api_version = 1,
c2fdcc25 528 .init = std_init,
700d6b64 529 .cleanup = std_cleanup,
03f4de8c 530 .scan = scan,
c01bf34c 531 .dev_list = std_dev_list,
f778bf02 532 .dev_clear = std_dev_clear,
035a1078
BV
533 .config_get = config_get,
534 .config_set = config_set,
a1c743fc 535 .config_list = config_list,
854434de 536 .dev_open = std_serial_dev_open,
bf2c987f 537 .dev_close = std_serial_dev_close,
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BV
538 .dev_acquisition_start = dev_acquisition_start,
539 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 540 .context = NULL,
0aba65da 541};
dd5c48a6 542SR_REGISTER_DEV_DRIVER(ols_driver_info);