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hantek-dso: dso2250: Allow setting TRIGGER_LEVEL as well.
[libsigrok.git] / src / hardware / hantek-dso / protocol.h
CommitLineData
3b533202 1/*
50985c20 2 * This file is part of the libsigrok project.
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3 *
4 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
5 * With protocol information from the hantekdso project,
6 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
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22#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H
23#define LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H
3b533202 24
3544f848 25#define LOG_PREFIX "hantek-dso"
cbc6f3b2 26
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27#define USB_INTERFACE 0
28#define USB_CONFIGURATION 1
29#define DSO_EP_IN 0x86
30#define DSO_EP_OUT 0x02
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31
32/* FX2 renumeration delay in ms */
8c971b6e 33#define MAX_RENUM_DELAY_MS 3000
3b533202 34
8c971b6e 35#define MAX_CAPTURE_EMPTY 3
3b533202 36
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37#define DEFAULT_VOLTAGE VDIV_500MV
38#define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
39#define DEFAULT_TIMEBASE TIME_100us
11e33196 40#define DEFAULT_SAMPLERATE SR_KHZ(10)
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41#define DEFAULT_TRIGGER_SOURCE "CH1"
42#define DEFAULT_COUPLING COUPLING_DC
95983cc3 43#define DEFAULT_CAPTURE_RATIO 100
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44#define DEFAULT_VERT_OFFSET 0.5
45#define DEFAULT_VERT_TRIGGERPOS 0.5
3b533202 46
8c971b6e 47#define MAX_VERT_TRIGGER 0xfe
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48
49/* Hantek DSO-specific protocol values */
8c971b6e 50#define EEPROM_CHANNEL_OFFSETS 0x08
3b533202 51
034accb5 52/* All models have this for their "fast" mode. */
1a46cc62 53#define FRAMESIZE_SMALL (10 * 1024)
3b533202 54
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55#define NUM_CHANNELS 2
56
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57enum control_requests {
58 CTRL_READ_EEPROM = 0xa2,
59 CTRL_GETSPEED = 0xb2,
60 CTRL_BEGINCOMMAND = 0xb3,
61 CTRL_SETOFFSET = 0xb4,
e98b7f1b 62 CTRL_SETRELAYS = 0xb5,
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63};
64
65enum dso_commands {
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66 CMD_SET_FILTERS = 0x0,
67 CMD_SET_TRIGGER_SAMPLERATE = 0x1,
68 CMD_FORCE_TRIGGER = 0x2,
69 CMD_CAPTURE_START = 0x3,
70 CMD_ENABLE_TRIGGER = 0x4,
71 CMD_GET_CHANNELDATA = 0x5,
72 CMD_GET_CAPTURESTATE = 0x6,
73 CMD_SET_VOLTAGE = 0x7,
313deed2 74 /* unused */
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75 CMD_SET_LOGICALDATA = 0x8,
76 CMD_GET_LOGICALDATA = 0x9,
77 CMD__UNUSED1 = 0xa,
78 /* For the following and other specials please see
79 * http://openhantek.sourceforge.net/doc/namespaceHantek.html#ac1cd181814cf3da74771c29800b39028 */
80 CMD_2250_SET_CHANNELS = 0xb,
81 CMD_2250_SET_TRIGGERSOURCE = 0xc,
82 CMD_2250_SET_RECORD_LENGTH = 0xd,
83 CMD_2250_SET_SAMPLERATE = 0xe,
84 CMD_2250_SET_TRIGGERPOS_AND_BUFFER = 0xf,
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85};
86
b58fbd99 87/* Must match the coupling table. */
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88enum couplings {
89 COUPLING_AC = 0,
90 COUPLING_DC,
2715c0b8 91 /* TODO not used, how to enable? */
e98b7f1b 92 COUPLING_GND,
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93};
94
b58fbd99 95/* Must match the timebases table. */
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96enum time_bases {
97 TIME_10us = 0,
98 TIME_20us,
99 TIME_40us,
100 TIME_100us,
101 TIME_200us,
102 TIME_400us,
103 TIME_1ms,
104 TIME_2ms,
105 TIME_4ms,
106 TIME_10ms,
107 TIME_20ms,
108 TIME_40ms,
109 TIME_100ms,
110 TIME_200ms,
e98b7f1b 111 TIME_400ms,
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112};
113
b58fbd99 114/* Must match the vdivs table. */
313deed2
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115enum {
116 VDIV_10MV,
117 VDIV_20MV,
118 VDIV_50MV,
119 VDIV_100MV,
120 VDIV_200MV,
121 VDIV_500MV,
122 VDIV_1V,
123 VDIV_2V,
124 VDIV_5V,
125};
126
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127enum trigger_slopes {
128 SLOPE_POSITIVE = 0,
e98b7f1b 129 SLOPE_NEGATIVE,
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130};
131
132enum trigger_sources {
133 TRIGGER_CH2 = 0,
134 TRIGGER_CH1,
3b533202 135 TRIGGER_EXT,
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136};
137
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138enum capturestates {
139 CAPTURE_EMPTY = 0,
140 CAPTURE_FILLING = 1,
141 CAPTURE_READY_8BIT = 2,
87f56d01 142 CAPTURE_READY2250 = 3,
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143 CAPTURE_READY_9BIT = 7,
144 CAPTURE_TIMEOUT = 127,
e98b7f1b 145 CAPTURE_UNKNOWN = 255,
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146};
147
148enum triggermodes {
149 TRIGGERMODE_AUTO,
150 TRIGGERMODE_NORMAL,
e98b7f1b 151 TRIGGERMODE_SINGLE,
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152};
153
154enum states {
155 IDLE,
156 NEW_CAPTURE,
157 CAPTURE,
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158 FETCH_DATA,
159 STOPPING,
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160};
161
162struct dso_profile {
163 /* VID/PID after cold boot */
164 uint16_t orig_vid;
165 uint16_t orig_pid;
166 /* VID/PID after firmware upload */
167 uint16_t fw_vid;
168 uint16_t fw_pid;
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169 const char *vendor;
170 const char *model;
034accb5 171 const uint64_t *buffersizes;
2c240774 172 const char *firmware;
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173};
174
269971dd 175struct dev_context {
62bb8840 176 const struct dso_profile *profile;
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177 uint64_t limit_frames;
178 uint64_t num_frames;
ba7dd8bb 179 GSList *enabled_channels;
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180 /* We can't keep track of an FX2-based device after upgrading
181 * the firmware (it re-enumerates into a different device address
182 * after the upgrade) this is like a global lock. No device will open
183 * until a proper delay after the last device was upgraded.
184 */
fc8fe3e3 185 int64_t fw_updated;
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186 int epin_maxpacketsize;
187 int capture_empty_count;
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188 int dev_state;
189
e749a8cb 190 /* Oscilloscope settings. */
11e33196 191 int samplerate;
3b533202 192 int timebase;
417412c8 193 gboolean ch_enabled[2];
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194 int voltage[2];
195 int coupling[2];
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196 // voltage offset (vertical position)
197 float voffset_ch1;
198 float voffset_ch2;
199 float voffset_trigger;
200 uint16_t channel_levels[2][9][2];
e749a8cb 201 unsigned int framesize;
933defaa 202 gboolean filter[2];
3b533202 203 int triggerslope;
a370ef19 204 char *triggersource;
95983cc3 205 int capture_ratio;
3b533202 206 int triggermode;
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207
208 /* Frame transfer */
209 unsigned int samp_received;
210 unsigned int samp_buffered;
211 unsigned int trigger_offset;
212 unsigned char *framebuf;
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213};
214
25a0f108 215SR_PRIV int dso_open(struct sr_dev_inst *sdi);
3b533202 216SR_PRIV void dso_close(struct sr_dev_inst *sdi);
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217SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi);
218SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi);
219SR_PRIV int dso_init(const struct sr_dev_inst *sdi);
220SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi,
e98b7f1b 221 uint8_t *capturestate, uint32_t *trigger_offset);
c118080b 222SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi);
69e19dd7 223SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi,
e98b7f1b 224 libusb_transfer_cb_fn cb);
11e33196 225SR_PRIV int dso_set_trigger_samplerate(const struct sr_dev_inst *sdi);
12f62ce6 226SR_PRIV int dso_set_voffsets(const struct sr_dev_inst *sdi);
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227
228#endif