]> sigrok.org Git - libsigrok.git/blame - src/hardware/hantek-4032l/protocol.h
hantek-4032l: Set new pwm threshold handling.
[libsigrok.git] / src / hardware / hantek-4032l / protocol.h
CommitLineData
6a25fa42
AZ
1/*
2 * This file is part of the libsigrok project.
3 *
5089a143
AZ
4 * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
5 * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
6 * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
6a25fa42
AZ
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBSIGROK_HARDWARE_HANTEK_4032L_PROTOCOL_H
23#define LIBSIGROK_HARDWARE_HANTEK_4032L_PROTOCOL_H
24
25#include <stdint.h>
26#include <glib.h>
5089a143 27#include <string.h>
6a25fa42
AZ
28#include <libsigrok/libsigrok.h>
29#include "libsigrok-internal.h"
30
31#define LOG_PREFIX "hantek-4032l"
32
5089a143
AZ
33#define H4032L_USB_VENDOR 0x04b5
34#define H4032L_USB_PRODUCT 0x4032
35
2958315d
AV
36#define H4032L_DATA_BUFFER_SIZE (2 * 1024)
37#define H4032L_DATA_TRANSFER_MAX_NUM 32
38
4b75f84c
AV
39#define H4043L_NUM_SAMPLES_MIN (2 * 1024)
40#define H4032L_NUM_SAMPLES_MAX (64 * 1024 * 1024)
41
5089a143
AZ
42#define H4032L_CMD_PKT_MAGIC 0x017f
43#define H4032L_STATUS_PACKET_MAGIC 0x2B1A037F
44#define H4032L_START_PACKET_MAGIC 0x2B1A027F
45#define H4032L_END_PACKET_MAGIC 0x4D3C037F
46
47enum h4032l_trigger_edge_type {
28f2d07f 48 H4032L_TRIGGER_EDGE_TYPE_RISE,
5089a143
AZ
49 H4032L_TRIGGER_EDGE_TYPE_FALL,
50 H4032L_TRIGGER_EDGE_TYPE_TOGGLE,
51 H4032L_TRIGGER_EDGE_TYPE_DISABLED
52};
53
54enum h4032l_trigger_data_range_type {
28f2d07f 55 H4032L_TRIGGER_DATA_RANGE_TYPE_MAX,
5089a143
AZ
56 H4032L_TRIGGER_DATA_RANGE_TYPE_MIN_OR_MAX,
57 H4032L_TRIGGER_DATA_RANGE_TYPE_OUT_OF_RANGE,
58 H4032L_TRIGGER_DATA_RANGE_TYPE_WITHIN_RANGE
59};
60
61enum h4032l_trigger_time_range_type {
28f2d07f 62 H4032L_TRIGGER_TIME_RANGE_TYPE_MAX,
5089a143
AZ
63 H4032L_TRIGGER_TIME_RANGE_TYPE_MIN_OR_MAX,
64 H4032L_TRIGGER_TIME_RANGE_TYPE_OUT_OF_RANGE,
65 H4032L_TRIGGER_TIME_RANGE_TYPE_WITHIN_RANGE
66};
6a25fa42 67
5089a143 68enum h4032l_trigger_data_selection {
28f2d07f 69 H4032L_TRIGGER_DATA_SELECTION_NEXT,
5089a143
AZ
70 H4032L_TRIGGER_DATA_SELECTION_CURRENT,
71 H4032L_TRIGGER_DATA_SELECTION_PREV
72};
6a25fa42 73
5089a143
AZ
74enum h4032l_status {
75 H4032L_STATUS_IDLE,
76 H4032L_STATUS_CMD_CONFIGURE,
77 H4032L_STATUS_CMD_STATUS,
78 H4032L_STATUS_RESPONSE_STATUS,
79 H4032L_STATUS_RESPONSE_STATUS_RETRY,
80 H4032L_STATUS_RESPONSE_STATUS_CONTINUE,
81 H4032L_STATUS_CMD_GET,
82 H4032L_STATUS_FIRST_TRANSFER,
28f2d07f 83 H4032L_STATUS_TRANSFER
5089a143 84};
6a25fa42 85
e80e1858
AV
86#pragma pack(push,2)
87struct h4032l_trigger {
5089a143
AZ
88 struct {
89 uint32_t edge_signal:5;
90 uint32_t edge_type:2;
91 uint32_t :1;
92 uint32_t data_range_type:2;
93 uint32_t time_range_type:2;
94 uint32_t data_range_enabled:1;
95 uint32_t time_range_enabled:1;
96 uint32_t :2;
97 uint32_t data_sel:2;
98 uint32_t combined_enabled:1;
99 } flags;
100 uint32_t data_range_min;
101 uint32_t data_range_max;
102 uint32_t time_range_min;
103 uint32_t time_range_max;
104 uint32_t data_range_mask;
105 uint32_t combine_mask;
106 uint32_t combine_data;
107};
6a25fa42 108
e80e1858 109struct h4032l_cmd_pkt {
5089a143
AZ
110 uint16_t magic; /* 0x017f */
111 uint8_t sample_rate;
112 struct {
113 uint8_t enable_trigger1:1;
114 uint8_t enable_trigger2:1;
115 uint8_t trigger_and_logic:1;
116 } trig_flags;
117 uint16_t pwm_a;
118 uint16_t pwm_b;
119 uint16_t reserved;
120 uint32_t sample_size; /* Sample depth in bits per channel, 2k-64M, must be multiple of 512. */
121 uint32_t pre_trigger_size; /* Pretrigger buffer depth in bits, must be < sample_size. */
122 struct h4032l_trigger trigger[2];
123 uint16_t cmd;
124};
e80e1858 125#pragma pack(pop)
5089a143
AZ
126
127struct dev_context {
128 enum h4032l_status status;
3dc976fe 129 unsigned int sent_samples;
2958315d 130 int submitted_transfers;
5089a143 131 uint32_t remaining_samples;
a5b9880e 132 gboolean acq_aborted;
5089a143 133 struct h4032l_cmd_pkt cmd_pkt;
2958315d
AV
134 unsigned int num_transfers;
135 struct libusb_transfer **transfers;
5089a143
AZ
136 uint8_t buffer[512];
137 uint64_t capture_ratio;
3dc976fe 138 uint32_t trigger_pos;
caad0024 139 double cur_threshold;
7a7afc00 140 uint32_t fpga_version;
6a25fa42
AZ
141};
142
5089a143
AZ
143SR_PRIV int h4032l_receive_data(int fd, int revents, void *cb_data);
144SR_PRIV uint16_t h4032l_voltage2pwm(double voltage);
145SR_PRIV void LIBUSB_CALL h4032l_usb_callback(struct libusb_transfer *transfer);
43d86035
AV
146SR_PRIV void LIBUSB_CALL h4032l_data_transfer_callback(struct libusb_transfer *transfer);
147SR_PRIV int h4032l_start_data_transfers(const struct sr_dev_inst *sdi);
5089a143 148SR_PRIV int h4032l_start(const struct sr_dev_inst *sdi);
2958315d 149SR_PRIV int h4032l_stop(struct sr_dev_inst *sdi);
5089a143 150SR_PRIV int h4032l_dev_open(struct sr_dev_inst *sdi);
7a7afc00 151SR_PRIV int h4032l_get_fpga_version(const struct sr_dev_inst *sdi);
6a25fa42
AZ
152
153#endif