]> sigrok.org Git - libsigrok.git/blame - src/hardware/chronovu-la/protocol.c
dev_acquisition_{start,stop}(): Drop duplicate 'cb_data' parameter.
[libsigrok.git] / src / hardware / chronovu-la / protocol.c
CommitLineData
b908f067 1/*
50985c20 2 * This file is part of the libsigrok project.
b908f067 3 *
b172c130 4 * Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
b908f067
UH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
6ec6c43b 21#include <config.h>
45e080b6 22#include "protocol.h"
b908f067 23
00910580 24SR_PRIV const struct cv_profile cv_profiles[] = {
aeff7fa2
BV
25 { CHRONOVU_LA8, "LA8", "ChronoVu LA8", 8, SR_MHZ(100), 2, 0.8388608 },
26 { CHRONOVU_LA16, "LA16", "ChronoVu LA16", 16, SR_MHZ(200), 4, 0.042 },
9e9dba7b 27 ALL_ZERO
00910580
UH
28};
29
30/* LA8: channels are numbered 0-7. LA16: channels are numbered 0-15. */
31SR_PRIV const char *cv_channel_names[] = {
78693401 32 "0", "1", "2", "3", "4", "5", "6", "7",
00910580 33 "8", "9", "10", "11", "12", "13", "14", "15",
b908f067
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34};
35
00910580
UH
36static int close_usb_reset_sequencer(struct dev_context *devc);
37
38SR_PRIV void cv_fill_samplerates_if_needed(const struct sr_dev_inst *sdi)
b908f067
UH
39{
40 int i;
00910580
UH
41 struct dev_context *devc;
42
43 devc = sdi->priv;
b908f067 44
00910580 45 if (devc->samplerates[0] != 0)
b908f067
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46 return;
47
b908f067 48 for (i = 0; i < 255; i++)
00910580 49 devc->samplerates[254 - i] = devc->prof->max_samplerate / (i + 1);
b908f067
UH
50}
51
52/**
b172c130 53 * Check if the given samplerate is supported by the hardware.
b908f067 54 *
00910580 55 * @param sdi Device instance.
b908f067 56 * @param samplerate The samplerate (in Hz) to check.
00910580 57 *
b908f067
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58 * @return 1 if the samplerate is supported/valid, 0 otherwise.
59 */
00910580
UH
60static int is_valid_samplerate(const struct sr_dev_inst *sdi,
61 uint64_t samplerate)
b908f067
UH
62{
63 int i;
00910580
UH
64 struct dev_context *devc;
65
66 devc = sdi->priv;
b908f067 67
00910580 68 cv_fill_samplerates_if_needed(sdi);
b908f067
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69
70 for (i = 0; i < 255; i++) {
00910580 71 if (devc->samplerates[i] == samplerate)
b908f067
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72 return 1;
73 }
74
f3a35908 75 sr_err("Invalid samplerate (%" PRIu64 "Hz).", samplerate);
b908f067
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76
77 return 0;
78}
79
80/**
b172c130 81 * Convert a samplerate (in Hz) to the 'divcount' value the device wants.
b908f067 82 *
00910580
UH
83 * The divcount value can be 0x00 - 0xfe (0xff is not valid).
84 *
85 * LA8:
86 * sample period = (divcount + 1) * 10ns.
87 * divcount = 0x00: 10ns period, 100MHz samplerate.
88 * divcount = 0xfe: 2550ns period, 392.15kHz samplerate.
89 *
90 * LA16:
91 * sample period = (divcount + 1) * 5ns.
92 * divcount = 0x00: 5ns period, 200MHz samplerate.
93 * divcount = 0xfe: 1275ns period, ~784.31kHz samplerate.
b908f067 94 *
00910580 95 * @param sdi Device instance.
b908f067 96 * @param samplerate The samplerate in Hz.
00910580 97 *
b908f067
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98 * @return The divcount value as needed by the hardware, or 0xff upon errors.
99 */
00910580
UH
100SR_PRIV uint8_t cv_samplerate_to_divcount(const struct sr_dev_inst *sdi,
101 uint64_t samplerate)
b908f067 102{
00910580
UH
103 struct dev_context *devc;
104
105 devc = sdi->priv;
106
b908f067 107 if (samplerate == 0) {
b172c130 108 sr_err("Can't convert invalid samplerate of 0 Hz.");
b908f067
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109 return 0xff;
110 }
111
00910580 112 if (!is_valid_samplerate(sdi, samplerate)) {
b172c130 113 sr_err("Can't get divcount, samplerate invalid.");
b908f067
UH
114 return 0xff;
115 }
116
00910580 117 return (devc->prof->max_samplerate / samplerate) - 1;
b908f067
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118}
119
120/**
b172c130 121 * Write data of a certain length to the FTDI device.
b908f067 122 *
1644fb24 123 * @param devc The struct containing private per-device-instance data. Must not
b172c130 124 * be NULL. devc->ftdic must not be NULL either.
b908f067 125 * @param buf The buffer containing the data to write. Must not be NULL.
b172c130
UH
126 * @param size The number of bytes to write. Must be > 0.
127 *
b908f067
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128 * @return The number of bytes written, or a negative value upon errors.
129 */
b172c130 130SR_PRIV int cv_write(struct dev_context *devc, uint8_t *buf, int size)
b908f067
UH
131{
132 int bytes_written;
133
b172c130 134 /* Note: Caller ensures devc/devc->ftdic/buf != NULL and size > 0. */
b908f067 135
1644fb24 136 bytes_written = ftdi_write_data(devc->ftdic, buf, size);
b908f067
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137
138 if (bytes_written < 0) {
b172c130 139 sr_err("Failed to write data (%d): %s.",
1644fb24 140 bytes_written, ftdi_get_error_string(devc->ftdic));
00910580 141 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067 142 } else if (bytes_written != size) {
b172c130
UH
143 sr_err("Failed to write data, only %d/%d bytes written.",
144 size, bytes_written);
00910580 145 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067
UH
146 }
147
148 return bytes_written;
149}
150
151/**
b172c130 152 * Read a certain amount of bytes from the FTDI device.
b908f067 153 *
1644fb24 154 * @param devc The struct containing private per-device-instance data. Must not
b172c130 155 * be NULL. devc->ftdic must not be NULL either.
b908f067
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156 * @param buf The buffer where the received data will be stored. Must not
157 * be NULL.
158 * @param size The number of bytes to read. Must be >= 1.
b172c130 159 *
b908f067
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160 * @return The number of bytes read, or a negative value upon errors.
161 */
b172c130 162static int cv_read(struct dev_context *devc, uint8_t *buf, int size)
b908f067
UH
163{
164 int bytes_read;
165
b172c130 166 /* Note: Caller ensures devc/devc->ftdic/buf != NULL and size > 0. */
b908f067 167
1644fb24 168 bytes_read = ftdi_read_data(devc->ftdic, buf, size);
b908f067
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169
170 if (bytes_read < 0) {
b172c130 171 sr_err("Failed to read data (%d): %s.",
1644fb24 172 bytes_read, ftdi_get_error_string(devc->ftdic));
b908f067 173 } else if (bytes_read != size) {
b172c130
UH
174 // sr_err("Failed to read data, only %d/%d bytes read.",
175 // bytes_read, size);
b908f067
UH
176 }
177
178 return bytes_read;
179}
180
b908f067 181/**
b172c130 182 * Close the USB port and reset the sequencer logic.
b908f067 183 *
1644fb24 184 * @param devc The struct containing private per-device-instance data.
00910580 185 *
b908f067
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186 * @return SR_OK upon success, SR_ERR_ARG upon invalid arguments.
187 */
00910580 188static int close_usb_reset_sequencer(struct dev_context *devc)
b908f067 189{
b172c130 190 /* Magic sequence of bytes for resetting the sequencer logic. */
b908f067
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191 uint8_t buf[8] = {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01};
192 int ret;
193
00910580 194 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 195
1644fb24 196 if (devc->ftdic->usb_dev) {
b172c130 197 /* Reset the sequencer logic, then wait 100ms. */
f3a35908 198 sr_dbg("Resetting sequencer logic.");
b172c130 199 (void) cv_write(devc, buf, 8); /* Ignore errors. */
b908f067
UH
200 g_usleep(100 * 1000);
201
202 /* Purge FTDI buffers, then reset and close the FTDI device. */
f3a35908 203 sr_dbg("Purging buffers, resetting+closing FTDI device.");
b908f067
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204
205 /* Log errors, but ignore them (i.e., don't abort). */
1644fb24 206 if ((ret = ftdi_usb_purge_buffers(devc->ftdic)) < 0)
00910580
UH
207 sr_err("Failed to purge FTDI buffers (%d): %s.",
208 ret, ftdi_get_error_string(devc->ftdic));
1644fb24 209 if ((ret = ftdi_usb_reset(devc->ftdic)) < 0)
00910580 210 sr_err("Failed to reset FTDI device (%d): %s.",
1644fb24
BV
211 ret, ftdi_get_error_string(devc->ftdic));
212 if ((ret = ftdi_usb_close(devc->ftdic)) < 0)
00910580 213 sr_err("Failed to close FTDI device (%d): %s.",
1644fb24 214 ret, ftdi_get_error_string(devc->ftdic));
b908f067
UH
215 }
216
217 /* Close USB device, deinitialize and free the FTDI context. */
00910580 218 ftdi_free(devc->ftdic);
1644fb24 219 devc->ftdic = NULL;
b908f067
UH
220
221 return SR_OK;
222}
223
224/**
b172c130 225 * Reset the ChronoVu device.
b908f067 226 *
b172c130 227 * A reset is required after a failed read/write operation or upon timeouts.
b908f067 228 *
1644fb24 229 * @param devc The struct containing private per-device-instance data.
00910580 230 *
b908f067
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231 * @return SR_OK upon success, SR_ERR upon failure.
232 */
00910580 233static int reset_device(struct dev_context *devc)
b908f067
UH
234{
235 uint8_t buf[BS];
00910580 236 gint64 done, now;
b908f067
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237 int bytes_read;
238
00910580 239 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 240
f3a35908 241 sr_dbg("Resetting the device.");
b908f067
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242
243 /*
244 * Purge pending read data from the FTDI hardware FIFO until
245 * no more data is left, or a timeout occurs (after 20s).
246 */
00910580 247 done = (20 * G_TIME_SPAN_SECOND) + g_get_monotonic_time();
b908f067 248 do {
b172c130
UH
249 /* Try to read bytes until none are left (or errors occur). */
250 bytes_read = cv_read(devc, (uint8_t *)&buf, BS);
00910580 251 now = g_get_monotonic_time();
b908f067
UH
252 } while ((done > now) && (bytes_read > 0));
253
b172c130 254 /* Reset the sequencer logic and close the USB port. */
00910580 255 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067 256
f3a35908 257 sr_dbg("Device reset finished.");
b908f067
UH
258
259 return SR_OK;
260}
261
aeff7fa2 262SR_PRIV int cv_convert_trigger(const struct sr_dev_inst *sdi)
b908f067 263{
014359e3 264 struct dev_context *devc;
aeff7fa2
BV
265 struct sr_trigger *trigger;
266 struct sr_trigger_stage *stage;
267 struct sr_trigger_match *match;
268 const GSList *l, *m;
00910580 269 uint16_t channel_bit;
b908f067 270
014359e3 271 devc = sdi->priv;
00910580
UH
272 devc->trigger_pattern = 0x0000; /* Default to "low" trigger. */
273 devc->trigger_mask = 0x0000; /* Default to "don't care". */
274 devc->trigger_edgemask = 0x0000; /* Default to "state triggered". */
b908f067 275
0812c40e 276 if (!(trigger = sr_session_trigger_get(sdi->session)))
aeff7fa2 277 return SR_OK;
b908f067 278
aeff7fa2
BV
279 if (g_slist_length(trigger->stages) > 1) {
280 sr_err("This device only supports 1 trigger stage.");
281 return SR_ERR;
282 }
b908f067 283
aeff7fa2
BV
284 for (l = trigger->stages; l; l = l->next) {
285 stage = l->data;
286 for (m = stage->matches; m; m = m->next) {
287 match = m->data;
288 if (!match->channel->enabled)
289 /* Ignore disabled channels with a trigger. */
290 continue;
291 if (devc->prof->model == CHRONOVU_LA8 &&
292 (match->match == SR_TRIGGER_RISING
293 || match->match == SR_TRIGGER_FALLING)) {
294 sr_err("This model supports only simple triggers.");
b908f067
UH
295 return SR_ERR;
296 }
aeff7fa2 297 channel_bit = (1 << (match->channel->index));
b908f067 298
00910580 299 /* state: 1 == high, edge: 1 == rising edge. */
aeff7fa2
BV
300 if (match->match == SR_TRIGGER_ONE
301 || match->match == SR_TRIGGER_RISING)
ba7dd8bb 302 devc->trigger_pattern |= channel_bit;
00910580
UH
303
304 /* LA16 (but not LA8) supports edge triggering. */
305 if ((devc->prof->model == CHRONOVU_LA16)) {
aeff7fa2
BV
306 if (match->match == SR_TRIGGER_RISING
307 || match->match == SR_TRIGGER_FALLING)
308 devc->trigger_edgemask |= channel_bit;
00910580 309 }
b908f067
UH
310 }
311 }
312
00910580 313 sr_dbg("Trigger pattern/mask/edgemask = 0x%04x / 0x%04x / 0x%04x.",
aeff7fa2
BV
314 devc->trigger_pattern, devc->trigger_mask,
315 devc->trigger_edgemask);
b908f067
UH
316
317 return SR_OK;
318}
319
b172c130 320SR_PRIV int cv_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
b908f067 321{
1644fb24 322 struct dev_context *devc;
b908f067
UH
323
324 /* Note: Caller checked that sdi and sdi->priv != NULL. */
325
1644fb24 326 devc = sdi->priv;
b908f067 327
f3a35908 328 sr_spew("Trying to set samplerate to %" PRIu64 "Hz.", samplerate);
b908f067 329
00910580 330 cv_fill_samplerates_if_needed(sdi);
b908f067
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331
332 /* Check if this is a samplerate supported by the hardware. */
00910580 333 if (!is_valid_samplerate(sdi, samplerate)) {
b172c130
UH
334 sr_dbg("Failed to set invalid samplerate (%" PRIu64 "Hz).",
335 samplerate);
b908f067 336 return SR_ERR;
b172c130 337 }
b908f067 338
1644fb24 339 devc->cur_samplerate = samplerate;
b908f067 340
f3a35908 341 sr_dbg("Samplerate set to %" PRIu64 "Hz.", devc->cur_samplerate);
b908f067
UH
342
343 return SR_OK;
344}
345
346/**
b172c130 347 * Get a block of data from the device.
b908f067 348 *
1644fb24 349 * @param devc The struct containing private per-device-instance data. Must not
b172c130
UH
350 * be NULL. devc->ftdic must not be NULL either.
351 *
b908f067
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352 * @return SR_OK upon success, or SR_ERR upon errors.
353 */
b172c130 354SR_PRIV int cv_read_block(struct dev_context *devc)
b908f067 355{
00910580
UH
356 int i, byte_offset, m, mi, p, q, index, bytes_read;
357 gint64 now;
b908f067 358
1644fb24 359 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 360
f3a35908 361 sr_spew("Reading block %d.", devc->block_counter);
b908f067 362
b172c130 363 bytes_read = cv_read(devc, devc->mangled_buf, BS);
b908f067
UH
364
365 /* If first block read got 0 bytes, retry until success or timeout. */
1644fb24 366 if ((bytes_read == 0) && (devc->block_counter == 0)) {
b908f067 367 do {
f3a35908 368 sr_spew("Reading block 0 (again).");
00910580 369 /* Note: If bytes_read < 0 cv_read() will log errors. */
b172c130 370 bytes_read = cv_read(devc, devc->mangled_buf, BS);
00910580 371 now = g_get_monotonic_time();
1644fb24 372 } while ((devc->done > now) && (bytes_read == 0));
b908f067
UH
373 }
374
f3f19d11 375 /* Check if block read was successful or a timeout occurred. */
b908f067 376 if (bytes_read != BS) {
f3a35908 377 sr_err("Trigger timed out. Bytes read: %d.", bytes_read);
00910580 378 (void) reset_device(devc); /* Ignore errors. */
b908f067
UH
379 return SR_ERR;
380 }
381
382 /* De-mangle the data. */
f3a35908 383 sr_spew("Demangling block %d.", devc->block_counter);
1644fb24 384 byte_offset = devc->block_counter * BS;
b908f067
UH
385 m = byte_offset / (1024 * 1024);
386 mi = m * (1024 * 1024);
387 for (i = 0; i < BS; i++) {
00910580
UH
388 if (devc->prof->model == CHRONOVU_LA8) {
389 p = i & (1 << 0);
390 index = m * 2 + (((byte_offset + i) - mi) / 2) * 16;
391 index += (devc->divcount == 0) ? p : (1 - p);
392 } else {
393 p = i & (1 << 0);
394 q = i & (1 << 1);
395 index = m * 4 + (((byte_offset + i) - mi) / 4) * 32;
396 index += q + (1 - p);
397 }
1644fb24 398 devc->final_buf[index] = devc->mangled_buf[i];
b908f067
UH
399 }
400
401 return SR_OK;
402}
403
695dc859 404SR_PRIV void cv_send_block_to_session_bus(const struct sr_dev_inst *sdi, int block)
b908f067 405{
05266f36
UH
406 int i, idx;
407 uint8_t sample, expected_sample, tmp8;
b908f067
UH
408 struct sr_datafeed_packet packet;
409 struct sr_datafeed_logic logic;
410 int trigger_point; /* Relative trigger point (in this block). */
695dc859 411 struct dev_context *devc;
b908f067 412
00910580
UH
413 /* Note: Caller ensures devc/devc->ftdic != NULL and block > 0. */
414
695dc859
UH
415 devc = sdi->priv;
416
00910580 417 /* TODO: Implement/test proper trigger support for the LA16. */
b908f067
UH
418
419 /* Check if we can find the trigger condition in this block. */
420 trigger_point = -1;
1644fb24 421 expected_sample = devc->trigger_pattern & devc->trigger_mask;
b908f067
UH
422 for (i = 0; i < BS; i++) {
423 /* Don't continue if the trigger was found previously. */
1644fb24 424 if (devc->trigger_found)
b908f067
UH
425 break;
426
427 /*
428 * Also, don't continue if triggers are "don't care", i.e. if
429 * no trigger conditions were specified by the user. In that
430 * case we don't want to send an SR_DF_TRIGGER packet at all.
431 */
00910580 432 if (devc->trigger_mask == 0x0000)
b908f067
UH
433 break;
434
1644fb24 435 sample = *(devc->final_buf + (block * BS) + i);
b908f067 436
1644fb24 437 if ((sample & devc->trigger_mask) == expected_sample) {
b908f067 438 trigger_point = i;
1644fb24 439 devc->trigger_found = 1;
b908f067
UH
440 break;
441 }
442 }
443
05266f36
UH
444 /* Swap low and high bytes of the 16-bit LA16 samples. */
445 if (devc->prof->model == CHRONOVU_LA16) {
446 for (i = 0; i < BS; i += 2) {
447 idx = (block * BS) + i;
448 tmp8 = devc->final_buf[idx];
449 devc->final_buf[idx] = devc->final_buf[idx + 1];
450 devc->final_buf[idx + 1] = tmp8;
451 }
452 }
453
b908f067
UH
454 /* If no trigger was found, send one SR_DF_LOGIC packet. */
455 if (trigger_point == -1) {
456 /* Send an SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
457 sr_spew("Sending SR_DF_LOGIC packet (%d bytes) for "
458 "block %d.", BS, block);
b908f067
UH
459 packet.type = SR_DF_LOGIC;
460 packet.payload = &logic;
461 logic.length = BS;
00910580 462 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 463 logic.data = devc->final_buf + (block * BS);
695dc859 464 sr_session_send(sdi, &packet);
b908f067
UH
465 return;
466 }
467
468 /*
469 * We found the trigger, so some special handling is needed. We have
470 * to send an SR_DF_LOGIC packet with the samples before the trigger
471 * (if any), then the SD_DF_TRIGGER packet itself, then another
472 * SR_DF_LOGIC packet with the samples after the trigger (if any).
473 */
474
475 /* TODO: Send SR_DF_TRIGGER packet before or after the actual sample? */
476
477 /* If at least one sample is located before the trigger... */
478 if (trigger_point > 0) {
479 /* Send pre-trigger SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
480 sr_spew("Sending pre-trigger SR_DF_LOGIC packet, "
481 "start = %d, length = %d.", block * BS, trigger_point);
b908f067
UH
482 packet.type = SR_DF_LOGIC;
483 packet.payload = &logic;
484 logic.length = trigger_point;
00910580 485 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 486 logic.data = devc->final_buf + (block * BS);
695dc859 487 sr_session_send(sdi, &packet);
b908f067
UH
488 }
489
490 /* Send the SR_DF_TRIGGER packet to the session bus. */
f3a35908 491 sr_spew("Sending SR_DF_TRIGGER packet, sample = %d.",
b908f067
UH
492 (block * BS) + trigger_point);
493 packet.type = SR_DF_TRIGGER;
494 packet.payload = NULL;
695dc859 495 sr_session_send(sdi, &packet);
b908f067
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496
497 /* If at least one sample is located after the trigger... */
498 if (trigger_point < (BS - 1)) {
499 /* Send post-trigger SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
500 sr_spew("Sending post-trigger SR_DF_LOGIC packet, "
501 "start = %d, length = %d.",
b908f067
UH
502 (block * BS) + trigger_point, BS - trigger_point);
503 packet.type = SR_DF_LOGIC;
504 packet.payload = &logic;
505 logic.length = BS - trigger_point;
00910580 506 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 507 logic.data = devc->final_buf + (block * BS) + trigger_point;
695dc859 508 sr_session_send(sdi, &packet);
b908f067
UH
509 }
510}