]> sigrok.org Git - libsigrok.git/blame - src/hardware/chronovu-la/protocol.c
uni-t-ut181a: silence compiler warning, use of uninitialized variable
[libsigrok.git] / src / hardware / chronovu-la / protocol.c
CommitLineData
b908f067 1/*
50985c20 2 * This file is part of the libsigrok project.
b908f067 3 *
b172c130 4 * Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
b908f067
UH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
2ea1fdf1 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
b908f067
UH
18 */
19
6ec6c43b 20#include <config.h>
45e080b6 21#include "protocol.h"
b908f067 22
00910580 23SR_PRIV const struct cv_profile cv_profiles[] = {
aeff7fa2
BV
24 { CHRONOVU_LA8, "LA8", "ChronoVu LA8", 8, SR_MHZ(100), 2, 0.8388608 },
25 { CHRONOVU_LA16, "LA16", "ChronoVu LA16", 16, SR_MHZ(200), 4, 0.042 },
9e9dba7b 26 ALL_ZERO
00910580
UH
27};
28
29/* LA8: channels are numbered 0-7. LA16: channels are numbered 0-15. */
30SR_PRIV const char *cv_channel_names[] = {
78693401 31 "0", "1", "2", "3", "4", "5", "6", "7",
00910580 32 "8", "9", "10", "11", "12", "13", "14", "15",
b908f067
UH
33};
34
00910580
UH
35static int close_usb_reset_sequencer(struct dev_context *devc);
36
37SR_PRIV void cv_fill_samplerates_if_needed(const struct sr_dev_inst *sdi)
b908f067
UH
38{
39 int i;
00910580
UH
40 struct dev_context *devc;
41
42 devc = sdi->priv;
b908f067 43
00910580 44 if (devc->samplerates[0] != 0)
b908f067
UH
45 return;
46
b908f067 47 for (i = 0; i < 255; i++)
00910580 48 devc->samplerates[254 - i] = devc->prof->max_samplerate / (i + 1);
b908f067
UH
49}
50
51/**
b172c130 52 * Check if the given samplerate is supported by the hardware.
b908f067 53 *
00910580 54 * @param sdi Device instance.
b908f067 55 * @param samplerate The samplerate (in Hz) to check.
00910580 56 *
b908f067
UH
57 * @return 1 if the samplerate is supported/valid, 0 otherwise.
58 */
00910580
UH
59static int is_valid_samplerate(const struct sr_dev_inst *sdi,
60 uint64_t samplerate)
b908f067
UH
61{
62 int i;
00910580
UH
63 struct dev_context *devc;
64
65 devc = sdi->priv;
b908f067 66
00910580 67 cv_fill_samplerates_if_needed(sdi);
b908f067
UH
68
69 for (i = 0; i < 255; i++) {
00910580 70 if (devc->samplerates[i] == samplerate)
b908f067
UH
71 return 1;
72 }
73
f3a35908 74 sr_err("Invalid samplerate (%" PRIu64 "Hz).", samplerate);
b908f067
UH
75
76 return 0;
77}
78
79/**
b172c130 80 * Convert a samplerate (in Hz) to the 'divcount' value the device wants.
b908f067 81 *
00910580
UH
82 * The divcount value can be 0x00 - 0xfe (0xff is not valid).
83 *
84 * LA8:
85 * sample period = (divcount + 1) * 10ns.
86 * divcount = 0x00: 10ns period, 100MHz samplerate.
87 * divcount = 0xfe: 2550ns period, 392.15kHz samplerate.
88 *
89 * LA16:
90 * sample period = (divcount + 1) * 5ns.
91 * divcount = 0x00: 5ns period, 200MHz samplerate.
92 * divcount = 0xfe: 1275ns period, ~784.31kHz samplerate.
b908f067 93 *
00910580 94 * @param sdi Device instance.
b908f067 95 * @param samplerate The samplerate in Hz.
00910580 96 *
b908f067
UH
97 * @return The divcount value as needed by the hardware, or 0xff upon errors.
98 */
00910580
UH
99SR_PRIV uint8_t cv_samplerate_to_divcount(const struct sr_dev_inst *sdi,
100 uint64_t samplerate)
b908f067 101{
00910580
UH
102 struct dev_context *devc;
103
104 devc = sdi->priv;
105
b908f067 106 if (samplerate == 0) {
b172c130 107 sr_err("Can't convert invalid samplerate of 0 Hz.");
b908f067
UH
108 return 0xff;
109 }
110
00910580 111 if (!is_valid_samplerate(sdi, samplerate)) {
b172c130 112 sr_err("Can't get divcount, samplerate invalid.");
b908f067
UH
113 return 0xff;
114 }
115
00910580 116 return (devc->prof->max_samplerate / samplerate) - 1;
b908f067
UH
117}
118
119/**
b172c130 120 * Write data of a certain length to the FTDI device.
b908f067 121 *
1644fb24 122 * @param devc The struct containing private per-device-instance data. Must not
b172c130 123 * be NULL. devc->ftdic must not be NULL either.
b908f067 124 * @param buf The buffer containing the data to write. Must not be NULL.
b172c130
UH
125 * @param size The number of bytes to write. Must be > 0.
126 *
b908f067
UH
127 * @return The number of bytes written, or a negative value upon errors.
128 */
b172c130 129SR_PRIV int cv_write(struct dev_context *devc, uint8_t *buf, int size)
b908f067
UH
130{
131 int bytes_written;
132
b172c130 133 /* Note: Caller ensures devc/devc->ftdic/buf != NULL and size > 0. */
b908f067 134
1644fb24 135 bytes_written = ftdi_write_data(devc->ftdic, buf, size);
b908f067
UH
136
137 if (bytes_written < 0) {
b172c130 138 sr_err("Failed to write data (%d): %s.",
1644fb24 139 bytes_written, ftdi_get_error_string(devc->ftdic));
00910580 140 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067 141 } else if (bytes_written != size) {
b172c130
UH
142 sr_err("Failed to write data, only %d/%d bytes written.",
143 size, bytes_written);
00910580 144 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067
UH
145 }
146
147 return bytes_written;
148}
149
150/**
b172c130 151 * Read a certain amount of bytes from the FTDI device.
b908f067 152 *
1644fb24 153 * @param devc The struct containing private per-device-instance data. Must not
b172c130 154 * be NULL. devc->ftdic must not be NULL either.
b908f067
UH
155 * @param buf The buffer where the received data will be stored. Must not
156 * be NULL.
157 * @param size The number of bytes to read. Must be >= 1.
b172c130 158 *
b908f067
UH
159 * @return The number of bytes read, or a negative value upon errors.
160 */
b172c130 161static int cv_read(struct dev_context *devc, uint8_t *buf, int size)
b908f067
UH
162{
163 int bytes_read;
164
b172c130 165 /* Note: Caller ensures devc/devc->ftdic/buf != NULL and size > 0. */
b908f067 166
1644fb24 167 bytes_read = ftdi_read_data(devc->ftdic, buf, size);
b908f067
UH
168
169 if (bytes_read < 0) {
b172c130 170 sr_err("Failed to read data (%d): %s.",
1644fb24 171 bytes_read, ftdi_get_error_string(devc->ftdic));
b908f067 172 } else if (bytes_read != size) {
b172c130
UH
173 // sr_err("Failed to read data, only %d/%d bytes read.",
174 // bytes_read, size);
b908f067
UH
175 }
176
177 return bytes_read;
178}
179
b908f067 180/**
b172c130 181 * Close the USB port and reset the sequencer logic.
b908f067 182 *
1644fb24 183 * @param devc The struct containing private per-device-instance data.
00910580 184 *
b908f067
UH
185 * @return SR_OK upon success, SR_ERR_ARG upon invalid arguments.
186 */
00910580 187static int close_usb_reset_sequencer(struct dev_context *devc)
b908f067 188{
b172c130 189 /* Magic sequence of bytes for resetting the sequencer logic. */
b908f067
UH
190 uint8_t buf[8] = {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01};
191 int ret;
192
00910580 193 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 194
1644fb24 195 if (devc->ftdic->usb_dev) {
b172c130 196 /* Reset the sequencer logic, then wait 100ms. */
f3a35908 197 sr_dbg("Resetting sequencer logic.");
b172c130 198 (void) cv_write(devc, buf, 8); /* Ignore errors. */
b908f067
UH
199 g_usleep(100 * 1000);
200
201 /* Purge FTDI buffers, then reset and close the FTDI device. */
f3a35908 202 sr_dbg("Purging buffers, resetting+closing FTDI device.");
b908f067
UH
203
204 /* Log errors, but ignore them (i.e., don't abort). */
1644fb24 205 if ((ret = ftdi_usb_purge_buffers(devc->ftdic)) < 0)
00910580
UH
206 sr_err("Failed to purge FTDI buffers (%d): %s.",
207 ret, ftdi_get_error_string(devc->ftdic));
1644fb24 208 if ((ret = ftdi_usb_reset(devc->ftdic)) < 0)
00910580 209 sr_err("Failed to reset FTDI device (%d): %s.",
1644fb24
BV
210 ret, ftdi_get_error_string(devc->ftdic));
211 if ((ret = ftdi_usb_close(devc->ftdic)) < 0)
00910580 212 sr_err("Failed to close FTDI device (%d): %s.",
1644fb24 213 ret, ftdi_get_error_string(devc->ftdic));
b908f067
UH
214 }
215
216 /* Close USB device, deinitialize and free the FTDI context. */
00910580 217 ftdi_free(devc->ftdic);
1644fb24 218 devc->ftdic = NULL;
b908f067
UH
219
220 return SR_OK;
221}
222
223/**
b172c130 224 * Reset the ChronoVu device.
b908f067 225 *
b172c130 226 * A reset is required after a failed read/write operation or upon timeouts.
b908f067 227 *
1644fb24 228 * @param devc The struct containing private per-device-instance data.
00910580 229 *
b908f067
UH
230 * @return SR_OK upon success, SR_ERR upon failure.
231 */
00910580 232static int reset_device(struct dev_context *devc)
b908f067
UH
233{
234 uint8_t buf[BS];
00910580 235 gint64 done, now;
b908f067
UH
236 int bytes_read;
237
00910580 238 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 239
f3a35908 240 sr_dbg("Resetting the device.");
b908f067
UH
241
242 /*
243 * Purge pending read data from the FTDI hardware FIFO until
244 * no more data is left, or a timeout occurs (after 20s).
245 */
00910580 246 done = (20 * G_TIME_SPAN_SECOND) + g_get_monotonic_time();
b908f067 247 do {
b172c130
UH
248 /* Try to read bytes until none are left (or errors occur). */
249 bytes_read = cv_read(devc, (uint8_t *)&buf, BS);
00910580 250 now = g_get_monotonic_time();
b908f067
UH
251 } while ((done > now) && (bytes_read > 0));
252
b172c130 253 /* Reset the sequencer logic and close the USB port. */
00910580 254 (void) close_usb_reset_sequencer(devc); /* Ignore errors. */
b908f067 255
f3a35908 256 sr_dbg("Device reset finished.");
b908f067
UH
257
258 return SR_OK;
259}
260
aeff7fa2 261SR_PRIV int cv_convert_trigger(const struct sr_dev_inst *sdi)
b908f067 262{
014359e3 263 struct dev_context *devc;
aeff7fa2
BV
264 struct sr_trigger *trigger;
265 struct sr_trigger_stage *stage;
266 struct sr_trigger_match *match;
267 const GSList *l, *m;
00910580 268 uint16_t channel_bit;
b908f067 269
014359e3 270 devc = sdi->priv;
00910580
UH
271 devc->trigger_pattern = 0x0000; /* Default to "low" trigger. */
272 devc->trigger_mask = 0x0000; /* Default to "don't care". */
273 devc->trigger_edgemask = 0x0000; /* Default to "state triggered". */
b908f067 274
0812c40e 275 if (!(trigger = sr_session_trigger_get(sdi->session)))
aeff7fa2 276 return SR_OK;
b908f067 277
aeff7fa2
BV
278 if (g_slist_length(trigger->stages) > 1) {
279 sr_err("This device only supports 1 trigger stage.");
280 return SR_ERR;
281 }
b908f067 282
aeff7fa2
BV
283 for (l = trigger->stages; l; l = l->next) {
284 stage = l->data;
285 for (m = stage->matches; m; m = m->next) {
286 match = m->data;
287 if (!match->channel->enabled)
288 /* Ignore disabled channels with a trigger. */
289 continue;
290 if (devc->prof->model == CHRONOVU_LA8 &&
291 (match->match == SR_TRIGGER_RISING
292 || match->match == SR_TRIGGER_FALLING)) {
293 sr_err("This model supports only simple triggers.");
b908f067
UH
294 return SR_ERR;
295 }
aeff7fa2 296 channel_bit = (1 << (match->channel->index));
b908f067 297
00910580 298 /* state: 1 == high, edge: 1 == rising edge. */
aeff7fa2
BV
299 if (match->match == SR_TRIGGER_ONE
300 || match->match == SR_TRIGGER_RISING)
ba7dd8bb 301 devc->trigger_pattern |= channel_bit;
00910580 302
d025fce9
UH
303 /* LA8 and LA16 support state triggering. */
304 if (match->match == SR_TRIGGER_ONE
305 || match->match == SR_TRIGGER_ZERO)
306 devc->trigger_mask |= channel_bit;
307
00910580
UH
308 /* LA16 (but not LA8) supports edge triggering. */
309 if ((devc->prof->model == CHRONOVU_LA16)) {
aeff7fa2
BV
310 if (match->match == SR_TRIGGER_RISING
311 || match->match == SR_TRIGGER_FALLING)
312 devc->trigger_edgemask |= channel_bit;
00910580 313 }
b908f067
UH
314 }
315 }
316
00910580 317 sr_dbg("Trigger pattern/mask/edgemask = 0x%04x / 0x%04x / 0x%04x.",
aeff7fa2
BV
318 devc->trigger_pattern, devc->trigger_mask,
319 devc->trigger_edgemask);
b908f067
UH
320
321 return SR_OK;
322}
323
b172c130 324SR_PRIV int cv_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
b908f067 325{
1644fb24 326 struct dev_context *devc;
b908f067
UH
327
328 /* Note: Caller checked that sdi and sdi->priv != NULL. */
329
1644fb24 330 devc = sdi->priv;
b908f067 331
f3a35908 332 sr_spew("Trying to set samplerate to %" PRIu64 "Hz.", samplerate);
b908f067 333
00910580 334 cv_fill_samplerates_if_needed(sdi);
b908f067
UH
335
336 /* Check if this is a samplerate supported by the hardware. */
00910580 337 if (!is_valid_samplerate(sdi, samplerate)) {
b172c130
UH
338 sr_dbg("Failed to set invalid samplerate (%" PRIu64 "Hz).",
339 samplerate);
b908f067 340 return SR_ERR;
b172c130 341 }
b908f067 342
1644fb24 343 devc->cur_samplerate = samplerate;
b908f067 344
f3a35908 345 sr_dbg("Samplerate set to %" PRIu64 "Hz.", devc->cur_samplerate);
b908f067
UH
346
347 return SR_OK;
348}
349
350/**
b172c130 351 * Get a block of data from the device.
b908f067 352 *
1644fb24 353 * @param devc The struct containing private per-device-instance data. Must not
b172c130
UH
354 * be NULL. devc->ftdic must not be NULL either.
355 *
b908f067
UH
356 * @return SR_OK upon success, or SR_ERR upon errors.
357 */
b172c130 358SR_PRIV int cv_read_block(struct dev_context *devc)
b908f067 359{
00910580
UH
360 int i, byte_offset, m, mi, p, q, index, bytes_read;
361 gint64 now;
b908f067 362
1644fb24 363 /* Note: Caller checked that devc and devc->ftdic != NULL. */
b908f067 364
f3a35908 365 sr_spew("Reading block %d.", devc->block_counter);
b908f067 366
b172c130 367 bytes_read = cv_read(devc, devc->mangled_buf, BS);
b908f067
UH
368
369 /* If first block read got 0 bytes, retry until success or timeout. */
1644fb24 370 if ((bytes_read == 0) && (devc->block_counter == 0)) {
b908f067 371 do {
f3a35908 372 sr_spew("Reading block 0 (again).");
00910580 373 /* Note: If bytes_read < 0 cv_read() will log errors. */
b172c130 374 bytes_read = cv_read(devc, devc->mangled_buf, BS);
00910580 375 now = g_get_monotonic_time();
1644fb24 376 } while ((devc->done > now) && (bytes_read == 0));
b908f067
UH
377 }
378
f3f19d11 379 /* Check if block read was successful or a timeout occurred. */
b908f067 380 if (bytes_read != BS) {
f3a35908 381 sr_err("Trigger timed out. Bytes read: %d.", bytes_read);
00910580 382 (void) reset_device(devc); /* Ignore errors. */
b908f067
UH
383 return SR_ERR;
384 }
385
386 /* De-mangle the data. */
f3a35908 387 sr_spew("Demangling block %d.", devc->block_counter);
1644fb24 388 byte_offset = devc->block_counter * BS;
b908f067
UH
389 m = byte_offset / (1024 * 1024);
390 mi = m * (1024 * 1024);
391 for (i = 0; i < BS; i++) {
00910580
UH
392 if (devc->prof->model == CHRONOVU_LA8) {
393 p = i & (1 << 0);
394 index = m * 2 + (((byte_offset + i) - mi) / 2) * 16;
395 index += (devc->divcount == 0) ? p : (1 - p);
396 } else {
397 p = i & (1 << 0);
398 q = i & (1 << 1);
399 index = m * 4 + (((byte_offset + i) - mi) / 4) * 32;
400 index += q + (1 - p);
401 }
1644fb24 402 devc->final_buf[index] = devc->mangled_buf[i];
b908f067
UH
403 }
404
405 return SR_OK;
406}
407
695dc859 408SR_PRIV void cv_send_block_to_session_bus(const struct sr_dev_inst *sdi, int block)
b908f067 409{
05266f36
UH
410 int i, idx;
411 uint8_t sample, expected_sample, tmp8;
b908f067
UH
412 struct sr_datafeed_packet packet;
413 struct sr_datafeed_logic logic;
414 int trigger_point; /* Relative trigger point (in this block). */
695dc859 415 struct dev_context *devc;
b908f067 416
00910580
UH
417 /* Note: Caller ensures devc/devc->ftdic != NULL and block > 0. */
418
695dc859
UH
419 devc = sdi->priv;
420
00910580 421 /* TODO: Implement/test proper trigger support for the LA16. */
b908f067
UH
422
423 /* Check if we can find the trigger condition in this block. */
424 trigger_point = -1;
1644fb24 425 expected_sample = devc->trigger_pattern & devc->trigger_mask;
b908f067
UH
426 for (i = 0; i < BS; i++) {
427 /* Don't continue if the trigger was found previously. */
1644fb24 428 if (devc->trigger_found)
b908f067
UH
429 break;
430
431 /*
432 * Also, don't continue if triggers are "don't care", i.e. if
433 * no trigger conditions were specified by the user. In that
434 * case we don't want to send an SR_DF_TRIGGER packet at all.
435 */
00910580 436 if (devc->trigger_mask == 0x0000)
b908f067
UH
437 break;
438
1644fb24 439 sample = *(devc->final_buf + (block * BS) + i);
b908f067 440
1644fb24 441 if ((sample & devc->trigger_mask) == expected_sample) {
b908f067 442 trigger_point = i;
1644fb24 443 devc->trigger_found = 1;
b908f067
UH
444 break;
445 }
446 }
447
05266f36
UH
448 /* Swap low and high bytes of the 16-bit LA16 samples. */
449 if (devc->prof->model == CHRONOVU_LA16) {
450 for (i = 0; i < BS; i += 2) {
451 idx = (block * BS) + i;
452 tmp8 = devc->final_buf[idx];
453 devc->final_buf[idx] = devc->final_buf[idx + 1];
454 devc->final_buf[idx + 1] = tmp8;
455 }
456 }
457
b908f067
UH
458 /* If no trigger was found, send one SR_DF_LOGIC packet. */
459 if (trigger_point == -1) {
460 /* Send an SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
461 sr_spew("Sending SR_DF_LOGIC packet (%d bytes) for "
462 "block %d.", BS, block);
b908f067
UH
463 packet.type = SR_DF_LOGIC;
464 packet.payload = &logic;
465 logic.length = BS;
00910580 466 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 467 logic.data = devc->final_buf + (block * BS);
695dc859 468 sr_session_send(sdi, &packet);
b908f067
UH
469 return;
470 }
471
472 /*
473 * We found the trigger, so some special handling is needed. We have
474 * to send an SR_DF_LOGIC packet with the samples before the trigger
475 * (if any), then the SD_DF_TRIGGER packet itself, then another
476 * SR_DF_LOGIC packet with the samples after the trigger (if any).
477 */
478
479 /* TODO: Send SR_DF_TRIGGER packet before or after the actual sample? */
480
481 /* If at least one sample is located before the trigger... */
482 if (trigger_point > 0) {
483 /* Send pre-trigger SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
484 sr_spew("Sending pre-trigger SR_DF_LOGIC packet, "
485 "start = %d, length = %d.", block * BS, trigger_point);
b908f067
UH
486 packet.type = SR_DF_LOGIC;
487 packet.payload = &logic;
488 logic.length = trigger_point;
00910580 489 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 490 logic.data = devc->final_buf + (block * BS);
695dc859 491 sr_session_send(sdi, &packet);
b908f067
UH
492 }
493
494 /* Send the SR_DF_TRIGGER packet to the session bus. */
f3a35908 495 sr_spew("Sending SR_DF_TRIGGER packet, sample = %d.",
b908f067 496 (block * BS) + trigger_point);
0fa71943 497 std_session_send_df_trigger(sdi);
b908f067
UH
498
499 /* If at least one sample is located after the trigger... */
500 if (trigger_point < (BS - 1)) {
501 /* Send post-trigger SR_DF_LOGIC packet to the session bus. */
f3a35908
UH
502 sr_spew("Sending post-trigger SR_DF_LOGIC packet, "
503 "start = %d, length = %d.",
b908f067
UH
504 (block * BS) + trigger_point, BS - trigger_point);
505 packet.type = SR_DF_LOGIC;
506 packet.payload = &logic;
507 logic.length = BS - trigger_point;
00910580 508 logic.unitsize = devc->prof->num_channels / 8;
1644fb24 509 logic.data = devc->final_buf + (block * BS) + trigger_point;
695dc859 510 sr_session_send(sdi, &packet);
b908f067
UH
511 }
512}