]> sigrok.org Git - libsigrok.git/blame - hardware/hantek-dso/dso.h
hantek-dso: get rid of broken GTV_TO_MSEC firmware upload timeout
[libsigrok.git] / hardware / hantek-dso / dso.h
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
5 * With protocol information from the hantekdso project,
6 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H
23#define LIBSIGROK_HARDWARE_HANTEK_DSO_H
24
25#define USB_INTERFACE 0
26#define USB_CONFIGURATION 1
27#define DSO_EP_IN 0x86
28#define DSO_EP_OUT 0x02
29
30/* FX2 renumeration delay in ms */
fc8fe3e3 31#define MAX_RENUM_DELAY_MS 3000
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32
33#define MAX_CAPTURE_EMPTY 3
34
313deed2 35#define DEFAULT_VOLTAGE VDIV_500MV
3b533202 36#define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
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37#define DEFAULT_TIMEBASE TIME_100us
38#define DEFAULT_TRIGGER_SOURCE "CH1"
a10c8056 39#define DEFAULT_COUPLING COUPLING_DC
bc79e906 40#define DEFAULT_HORIZ_TRIGGERPOS 0.5
3b533202 41#define DEFAULT_VERT_OFFSET 0.5
2715c0b8 42#define DEFAULT_VERT_TRIGGERPOS 0.5
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43
44#define MAX_VERT_TRIGGER 0xfe
45
46/* Hantek DSO-specific protocol values */
47#define EEPROM_CHANNEL_OFFSETS 0x08
48
49#define FRAMESIZE_SMALL 10240
50#define FRAMESIZE_LARGE 32768
51
52
53enum control_requests {
54 CTRL_READ_EEPROM = 0xa2,
55 CTRL_GETSPEED = 0xb2,
56 CTRL_BEGINCOMMAND = 0xb3,
57 CTRL_SETOFFSET = 0xb4,
58 CTRL_SETRELAYS = 0xb5
59};
60
61enum dso_commands {
62 CMD_SET_FILTERS = 0,
63 CMD_SET_TRIGGER_SAMPLERATE,
64 CMD_FORCE_TRIGGER,
65 CMD_CAPTURE_START,
66 CMD_ENABLE_TRIGGER,
67 CMD_GET_CHANNELDATA,
68 CMD_GET_CAPTURESTATE,
69 CMD_SET_VOLTAGE,
313deed2 70 /* unused */
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71 cmdSetLogicalData,
72 cmdGetLogicalData
73};
74
b58fbd99 75/* Must match the coupling table. */
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76enum couplings {
77 COUPLING_AC = 0,
78 COUPLING_DC,
2715c0b8 79 /* TODO not used, how to enable? */
b58fbd99 80 COUPLING_GND
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81};
82
b58fbd99 83/* Must match the timebases table. */
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84enum time_bases {
85 TIME_10us = 0,
86 TIME_20us,
87 TIME_40us,
88 TIME_100us,
89 TIME_200us,
90 TIME_400us,
91 TIME_1ms,
92 TIME_2ms,
93 TIME_4ms,
94 TIME_10ms,
95 TIME_20ms,
96 TIME_40ms,
97 TIME_100ms,
98 TIME_200ms,
99 TIME_400ms
100};
101
b58fbd99 102/* Must match the vdivs table. */
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103enum {
104 VDIV_10MV,
105 VDIV_20MV,
106 VDIV_50MV,
107 VDIV_100MV,
108 VDIV_200MV,
109 VDIV_500MV,
110 VDIV_1V,
111 VDIV_2V,
112 VDIV_5V,
113};
114
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115enum trigger_slopes {
116 SLOPE_POSITIVE = 0,
117 SLOPE_NEGATIVE
118};
119
120enum trigger_sources {
121 TRIGGER_CH2 = 0,
122 TRIGGER_CH1,
3b533202 123 TRIGGER_EXT,
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124};
125
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126enum capturestates {
127 CAPTURE_EMPTY = 0,
128 CAPTURE_FILLING = 1,
129 CAPTURE_READY_8BIT = 2,
130 CAPTURE_READY_9BIT = 7,
131 CAPTURE_TIMEOUT = 127,
132 CAPTURE_UNKNOWN = 255
133};
134
135enum triggermodes {
136 TRIGGERMODE_AUTO,
137 TRIGGERMODE_NORMAL,
138 TRIGGERMODE_SINGLE
139};
140
141enum states {
142 IDLE,
143 NEW_CAPTURE,
144 CAPTURE,
145 FETCH_DATA
146};
147
148struct dso_profile {
149 /* VID/PID after cold boot */
150 uint16_t orig_vid;
151 uint16_t orig_pid;
152 /* VID/PID after firmware upload */
153 uint16_t fw_vid;
154 uint16_t fw_pid;
155 char *vendor;
156 char *model;
157 char *model_version;
158 int num_probes;
159 char *firmware;
160};
161
162struct context {
62bb8840 163 const struct dso_profile *profile;
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164 struct sr_usb_dev_inst *usb;
165 void *cb_data;
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166 uint64_t limit_frames;
167 uint64_t num_frames;
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168 /* We can't keep track of an FX2-based device after upgrading
169 * the firmware (it re-enumerates into a different device address
170 * after the upgrade) this is like a global lock. No device will open
171 * until a proper delay after the last device was upgraded.
172 */
fc8fe3e3 173 int64_t fw_updated;
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174 int epin_maxpacketsize;
175 int capture_empty_count;
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176 int dev_state;
177
e749a8cb 178 /* Oscilloscope settings. */
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179 int timebase;
180 gboolean ch1_enabled;
181 gboolean ch2_enabled;
182 int voltage_ch1;
183 int voltage_ch2;
184 int coupling_ch1;
185 int coupling_ch2;
186 // voltage offset (vertical position)
187 float voffset_ch1;
188 float voffset_ch2;
189 float voffset_trigger;
190 uint16_t channel_levels[2][9][2];
e749a8cb 191 unsigned int framesize;
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192 gboolean filter_ch1;
193 gboolean filter_ch2;
194 gboolean filter_trigger;
195 int triggerslope;
a370ef19 196 char *triggersource;
bc79e906 197 float triggerposition;
3b533202 198 int triggermode;
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199
200 /* Frame transfer */
201 unsigned int samp_received;
202 unsigned int samp_buffered;
203 unsigned int trigger_offset;
204 unsigned char *framebuf;
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205};
206
207SR_PRIV int dso_open(int dev_index);
208SR_PRIV void dso_close(struct sr_dev_inst *sdi);
209SR_PRIV int dso_enable_trigger(struct context *ctx);
210SR_PRIV int dso_force_trigger(struct context *ctx);
211SR_PRIV int dso_init(struct context *ctx);
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212SR_PRIV int dso_get_capturestate(struct context *ctx, uint8_t *capturestate,
213 uint32_t *trigger_offset);
214SR_PRIV int dso_capture_start(struct context *ctx);
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215SR_PRIV int dso_get_channeldata(struct context *ctx, libusb_transfer_cb_fn cb);
216
217#endif