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hantek-dso: add profiles for all five models in the series
[libsigrok.git] / hardware / hantek-dso / dso.h
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
5 * With protocol information from the hantekdso project,
6 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H
23#define LIBSIGROK_HARDWARE_HANTEK_DSO_H
24
25#define USB_INTERFACE 0
26#define USB_CONFIGURATION 1
27#define DSO_EP_IN 0x86
28#define DSO_EP_OUT 0x02
88a13f30 29#define NUM_PROBES 2
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30
31/* FX2 renumeration delay in ms */
fc8fe3e3 32#define MAX_RENUM_DELAY_MS 3000
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33
34#define MAX_CAPTURE_EMPTY 3
35
313deed2 36#define DEFAULT_VOLTAGE VDIV_500MV
3b533202 37#define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
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38#define DEFAULT_TIMEBASE TIME_100us
39#define DEFAULT_TRIGGER_SOURCE "CH1"
a10c8056 40#define DEFAULT_COUPLING COUPLING_DC
bc79e906 41#define DEFAULT_HORIZ_TRIGGERPOS 0.5
3b533202 42#define DEFAULT_VERT_OFFSET 0.5
2715c0b8 43#define DEFAULT_VERT_TRIGGERPOS 0.5
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44
45#define MAX_VERT_TRIGGER 0xfe
46
47/* Hantek DSO-specific protocol values */
48#define EEPROM_CHANNEL_OFFSETS 0x08
49
50#define FRAMESIZE_SMALL 10240
51#define FRAMESIZE_LARGE 32768
52
53
54enum control_requests {
55 CTRL_READ_EEPROM = 0xa2,
56 CTRL_GETSPEED = 0xb2,
57 CTRL_BEGINCOMMAND = 0xb3,
58 CTRL_SETOFFSET = 0xb4,
59 CTRL_SETRELAYS = 0xb5
60};
61
62enum dso_commands {
63 CMD_SET_FILTERS = 0,
64 CMD_SET_TRIGGER_SAMPLERATE,
65 CMD_FORCE_TRIGGER,
66 CMD_CAPTURE_START,
67 CMD_ENABLE_TRIGGER,
68 CMD_GET_CHANNELDATA,
69 CMD_GET_CAPTURESTATE,
70 CMD_SET_VOLTAGE,
313deed2 71 /* unused */
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72 cmdSetLogicalData,
73 cmdGetLogicalData
74};
75
b58fbd99 76/* Must match the coupling table. */
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77enum couplings {
78 COUPLING_AC = 0,
79 COUPLING_DC,
2715c0b8 80 /* TODO not used, how to enable? */
b58fbd99 81 COUPLING_GND
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82};
83
b58fbd99 84/* Must match the timebases table. */
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85enum time_bases {
86 TIME_10us = 0,
87 TIME_20us,
88 TIME_40us,
89 TIME_100us,
90 TIME_200us,
91 TIME_400us,
92 TIME_1ms,
93 TIME_2ms,
94 TIME_4ms,
95 TIME_10ms,
96 TIME_20ms,
97 TIME_40ms,
98 TIME_100ms,
99 TIME_200ms,
100 TIME_400ms
101};
102
b58fbd99 103/* Must match the vdivs table. */
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104enum {
105 VDIV_10MV,
106 VDIV_20MV,
107 VDIV_50MV,
108 VDIV_100MV,
109 VDIV_200MV,
110 VDIV_500MV,
111 VDIV_1V,
112 VDIV_2V,
113 VDIV_5V,
114};
115
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116enum trigger_slopes {
117 SLOPE_POSITIVE = 0,
118 SLOPE_NEGATIVE
119};
120
121enum trigger_sources {
122 TRIGGER_CH2 = 0,
123 TRIGGER_CH1,
3b533202 124 TRIGGER_EXT,
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125};
126
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127enum capturestates {
128 CAPTURE_EMPTY = 0,
129 CAPTURE_FILLING = 1,
130 CAPTURE_READY_8BIT = 2,
131 CAPTURE_READY_9BIT = 7,
132 CAPTURE_TIMEOUT = 127,
133 CAPTURE_UNKNOWN = 255
134};
135
136enum triggermodes {
137 TRIGGERMODE_AUTO,
138 TRIGGERMODE_NORMAL,
139 TRIGGERMODE_SINGLE
140};
141
142enum states {
143 IDLE,
144 NEW_CAPTURE,
145 CAPTURE,
146 FETCH_DATA
147};
148
149struct dso_profile {
150 /* VID/PID after cold boot */
151 uint16_t orig_vid;
152 uint16_t orig_pid;
153 /* VID/PID after firmware upload */
154 uint16_t fw_vid;
155 uint16_t fw_pid;
156 char *vendor;
157 char *model;
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158 char *firmware;
159};
160
161struct context {
62bb8840 162 const struct dso_profile *profile;
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163 struct sr_usb_dev_inst *usb;
164 void *cb_data;
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165 uint64_t limit_frames;
166 uint64_t num_frames;
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167 /* We can't keep track of an FX2-based device after upgrading
168 * the firmware (it re-enumerates into a different device address
169 * after the upgrade) this is like a global lock. No device will open
170 * until a proper delay after the last device was upgraded.
171 */
fc8fe3e3 172 int64_t fw_updated;
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173 int epin_maxpacketsize;
174 int capture_empty_count;
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175 int dev_state;
176
e749a8cb 177 /* Oscilloscope settings. */
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178 int timebase;
179 gboolean ch1_enabled;
180 gboolean ch2_enabled;
181 int voltage_ch1;
182 int voltage_ch2;
183 int coupling_ch1;
184 int coupling_ch2;
185 // voltage offset (vertical position)
186 float voffset_ch1;
187 float voffset_ch2;
188 float voffset_trigger;
189 uint16_t channel_levels[2][9][2];
e749a8cb 190 unsigned int framesize;
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191 gboolean filter_ch1;
192 gboolean filter_ch2;
193 gboolean filter_trigger;
194 int triggerslope;
a370ef19 195 char *triggersource;
bc79e906 196 float triggerposition;
3b533202 197 int triggermode;
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198
199 /* Frame transfer */
200 unsigned int samp_received;
201 unsigned int samp_buffered;
202 unsigned int trigger_offset;
203 unsigned char *framebuf;
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204};
205
206SR_PRIV int dso_open(int dev_index);
207SR_PRIV void dso_close(struct sr_dev_inst *sdi);
208SR_PRIV int dso_enable_trigger(struct context *ctx);
209SR_PRIV int dso_force_trigger(struct context *ctx);
210SR_PRIV int dso_init(struct context *ctx);
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211SR_PRIV int dso_get_capturestate(struct context *ctx, uint8_t *capturestate,
212 uint32_t *trigger_offset);
213SR_PRIV int dso_capture_start(struct context *ctx);
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214SR_PRIV int dso_get_channeldata(struct context *ctx, libusb_transfer_cb_fn cb);
215
216#endif