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drivers: use new sr_config struct
[libsigrok.git] / hardware / hantek-dso / dso.h
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
5 * With protocol information from the hantekdso project,
6 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H
23#define LIBSIGROK_HARDWARE_HANTEK_DSO_H
24
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25#define USB_INTERFACE 0
26#define USB_CONFIGURATION 1
27#define DSO_EP_IN 0x86
28#define DSO_EP_OUT 0x02
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29
30/* FX2 renumeration delay in ms */
e98b7f1b 31#define MAX_RENUM_DELAY_MS 3000
3b533202 32
e98b7f1b 33#define MAX_CAPTURE_EMPTY 3
3b533202 34
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35#define DEFAULT_VOLTAGE VDIV_500MV
36#define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
37#define DEFAULT_TIMEBASE TIME_100us
38#define DEFAULT_TRIGGER_SOURCE "CH1"
39#define DEFAULT_COUPLING COUPLING_DC
40#define DEFAULT_HORIZ_TRIGGERPOS 0.5
41#define DEFAULT_VERT_OFFSET 0.5
42#define DEFAULT_VERT_TRIGGERPOS 0.5
3b533202 43
e98b7f1b 44#define MAX_VERT_TRIGGER 0xfe
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45
46/* Hantek DSO-specific protocol values */
e98b7f1b 47#define EEPROM_CHANNEL_OFFSETS 0x08
3b533202 48
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49#define FRAMESIZE_SMALL 10240
50#define FRAMESIZE_LARGE 32768
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51
52enum control_requests {
53 CTRL_READ_EEPROM = 0xa2,
54 CTRL_GETSPEED = 0xb2,
55 CTRL_BEGINCOMMAND = 0xb3,
56 CTRL_SETOFFSET = 0xb4,
e98b7f1b 57 CTRL_SETRELAYS = 0xb5,
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58};
59
60enum dso_commands {
61 CMD_SET_FILTERS = 0,
62 CMD_SET_TRIGGER_SAMPLERATE,
63 CMD_FORCE_TRIGGER,
64 CMD_CAPTURE_START,
65 CMD_ENABLE_TRIGGER,
66 CMD_GET_CHANNELDATA,
67 CMD_GET_CAPTURESTATE,
68 CMD_SET_VOLTAGE,
313deed2 69 /* unused */
3b533202 70 cmdSetLogicalData,
e98b7f1b 71 cmdGetLogicalData,
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72};
73
b58fbd99 74/* Must match the coupling table. */
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75enum couplings {
76 COUPLING_AC = 0,
77 COUPLING_DC,
2715c0b8 78 /* TODO not used, how to enable? */
e98b7f1b 79 COUPLING_GND,
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80};
81
b58fbd99 82/* Must match the timebases table. */
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83enum time_bases {
84 TIME_10us = 0,
85 TIME_20us,
86 TIME_40us,
87 TIME_100us,
88 TIME_200us,
89 TIME_400us,
90 TIME_1ms,
91 TIME_2ms,
92 TIME_4ms,
93 TIME_10ms,
94 TIME_20ms,
95 TIME_40ms,
96 TIME_100ms,
97 TIME_200ms,
e98b7f1b 98 TIME_400ms,
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99};
100
b58fbd99 101/* Must match the vdivs table. */
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102enum {
103 VDIV_10MV,
104 VDIV_20MV,
105 VDIV_50MV,
106 VDIV_100MV,
107 VDIV_200MV,
108 VDIV_500MV,
109 VDIV_1V,
110 VDIV_2V,
111 VDIV_5V,
112};
113
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114enum trigger_slopes {
115 SLOPE_POSITIVE = 0,
e98b7f1b 116 SLOPE_NEGATIVE,
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117};
118
119enum trigger_sources {
120 TRIGGER_CH2 = 0,
121 TRIGGER_CH1,
3b533202 122 TRIGGER_EXT,
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123};
124
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125enum capturestates {
126 CAPTURE_EMPTY = 0,
127 CAPTURE_FILLING = 1,
128 CAPTURE_READY_8BIT = 2,
129 CAPTURE_READY_9BIT = 7,
130 CAPTURE_TIMEOUT = 127,
e98b7f1b 131 CAPTURE_UNKNOWN = 255,
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132};
133
134enum triggermodes {
135 TRIGGERMODE_AUTO,
136 TRIGGERMODE_NORMAL,
e98b7f1b 137 TRIGGERMODE_SINGLE,
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138};
139
140enum states {
141 IDLE,
142 NEW_CAPTURE,
143 CAPTURE,
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144 FETCH_DATA,
145 STOPPING,
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146};
147
148struct dso_profile {
149 /* VID/PID after cold boot */
150 uint16_t orig_vid;
151 uint16_t orig_pid;
152 /* VID/PID after firmware upload */
153 uint16_t fw_vid;
154 uint16_t fw_pid;
155 char *vendor;
156 char *model;
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157 char *firmware;
158};
159
269971dd 160struct dev_context {
62bb8840 161 const struct dso_profile *profile;
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162 struct sr_usb_dev_inst *usb;
163 void *cb_data;
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164 uint64_t limit_frames;
165 uint64_t num_frames;
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166 /* We can't keep track of an FX2-based device after upgrading
167 * the firmware (it re-enumerates into a different device address
168 * after the upgrade) this is like a global lock. No device will open
169 * until a proper delay after the last device was upgraded.
170 */
fc8fe3e3 171 int64_t fw_updated;
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172 int epin_maxpacketsize;
173 int capture_empty_count;
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174 int dev_state;
175
e749a8cb 176 /* Oscilloscope settings. */
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177 int timebase;
178 gboolean ch1_enabled;
179 gboolean ch2_enabled;
180 int voltage_ch1;
181 int voltage_ch2;
182 int coupling_ch1;
183 int coupling_ch2;
184 // voltage offset (vertical position)
185 float voffset_ch1;
186 float voffset_ch2;
187 float voffset_trigger;
188 uint16_t channel_levels[2][9][2];
e749a8cb 189 unsigned int framesize;
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190 gboolean filter_ch1;
191 gboolean filter_ch2;
192 gboolean filter_trigger;
193 int triggerslope;
a370ef19 194 char *triggersource;
bc79e906 195 float triggerposition;
3b533202 196 int triggermode;
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197
198 /* Frame transfer */
199 unsigned int samp_received;
200 unsigned int samp_buffered;
201 unsigned int trigger_offset;
202 unsigned char *framebuf;
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203};
204
25a0f108 205SR_PRIV int dso_open(struct sr_dev_inst *sdi);
3b533202 206SR_PRIV void dso_close(struct sr_dev_inst *sdi);
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207SR_PRIV int dso_enable_trigger(struct dev_context *devc);
208SR_PRIV int dso_force_trigger(struct dev_context *devc);
209SR_PRIV int dso_init(struct dev_context *devc);
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210SR_PRIV int dso_get_capturestate(struct dev_context *devc,
211 uint8_t *capturestate, uint32_t *trigger_offset);
269971dd 212SR_PRIV int dso_capture_start(struct dev_context *devc);
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213SR_PRIV int dso_get_channeldata(struct dev_context *devc,
214 libusb_transfer_cb_fn cb);
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215
216#endif