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2016-05-16	Diego Asanza	dslogic: Fix sampling for high samplerates. Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Add support for long captures at high samplerates. Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Add support for external clock edge selection. Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Implement continuous mode Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	Change type of SR_CONF_CONTINUOUS from SR_T_UINT64... Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Implement acquisition with external clock. Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Add support for voltage threshold Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-05-16	Diego Asanza	dslogic: Implement trigger functionality Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree
2016-04-13	Diego Asanza	Fix DSLogic FPGA binary image upload and signal acquisition. Signed-off-by: Diego Asanza <redacted>	commit \| commitdiff \| tree

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