output/csv: use intermediate time_t var, silence compiler warning

[libsigrok.git] / src / hardware / zeroplus-logic-cube / analyzer.c

diff --git a/src/hardware/zeroplus-logic-cube/analyzer.c b/src/hardware/zeroplus-logic-cube/analyzer.c
index 2130692f589dacde768663c4d0cf7857d9127e13..0617d227467e840548a93c823678c89c0c199ca1 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/analyzer.c
+++ b/src/hardware/zeroplus-logic-cube/analyzer.c
@@ -505,6 +505,9 @@ SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
        if (!(trigger = sr_session_trigger_get(sdi->session)))
                return SR_OK;
 
+       memset(g_trigger_status, 0, sizeof(g_trigger_status));
+       g_trigger_edge = 0;
+
        for (l = trigger->stages; l; l = l->next) {
                stage = l->data;
                for (m = stage->matches; m; m = m->next) {