xy2-100: Add two dumps

[sigrok-dumps.git] / i2c / edid / README

diff --git a/i2c/edid/README b/i2c/edid/README
index 8c9ec329073ff73a406f194645ea81a7793dbfe8..422ec5343e17b70479d988deaa8e0e76dde71a2c 100644 (file)
--- a/i2c/edid/README
+++ b/i2c/edid/README
@@ -1,7 +1,58 @@
-The captures in this directory were taken from a VGA cable, connected to
-various displays, as the EDID data was sent across the I2C bus.
+-------------------------------------------------------------------------------
+EDID
+-------------------------------------------------------------------------------
+
+The captures in this directory were taken from the DDC/I2C bus.
+
+For the two Samsung displays below, the logic analyzer was attached to a
+VGA cable, which connects the computer and the display while the EDID data
+was sent across the I2C bus.
 
 To decode these, set up a protocol decoder stack like this:
 
-       i2c -> ddc -> edid
+       i2c -> edid
+
+Details:
+https://en.wikipedia.org/wiki/Extended_display_identification_data
+https://en.wikipedia.org/wiki/Display_Data_Channel
+
+
+samsung_le46b620r3p.sr / samsung_syncmaster245b.sr
+--------------------------------------------------
+
+The logic analyzer used was a Saleae Logic (at 500kHz):
+
+  Probe       I2C pin
+  -------------------
+  1 (black)   SDA
+  2 (brown)   SCL
+
+
+samsung_syncmaster203b.sr
+-------------------------
+
+The logic analyzer used was a Saleae Logic (at 1MHz):
+
+  Probe       I2C pin
+  -------------------
+  1 (black)   SCL
+  2 (brown)   SDA
+
+
+acer_al711_on_dp_dm_hdmi_vga.sr
+-------------------------------
+
+This setup is somewhat more evolved, as it used a computer with a
+dual-mode displayport (DP++), a DP-HDMI (Type 1) adapter, a HDMI DDC
+breakout cable, a HDMI-VGA adapter, and a CRT screen with VGA input.
+
+The logic analyzer was connected to the DDC bus between the two adapters
+above, i.e. on the HDMI connection. As the DP-HDMI adapter uses a level
+shifter between DP and HDMI DDC busses, also the communication between
+computer and the DP adapter is visible (the DDC busses on both side are
+physically connected). The DP-HDMI adapter is visible at I2C address
+0x40 and responds with the readonly identifier 'DP-HDMI Adaptor<EOT>'.
 
+The HDMI-VGA adapter modifies the EDID contents from the VGA moniter,
+it adds an CEA extension block at offset 0x80 and notifies the existence
+of the extension block in the first block.