- 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
- 'PARITY ERROR': The data is a tuple with two entries. The first one is
the expected parity value, the second is the actual parity value.
- - TODO: Frame error?
- 'BREAK': The data is always 0.
+ - 'FRAME': The data is always a tuple containing two items: The (integer)
+ value of the UART data, and a boolean which reflects the validity of the
+ UART frame.
The <rxtx> field is 0 for RX packets, 1 for TX packets.
'''
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
+ tags = ['Embedded/industrial']
optional_channels = (
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
'values': ('yes', 'no')},
{'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
'values': ('yes', 'no')},
+ {'id': 'rx_packet_delimiter', 'desc': 'RX packet delimiter (decimal)',
+ 'default': -1},
+ {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)',
+ 'default': -1},
+ {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
+ {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
)
annotations = (
('rx-data', 'RX data'),
('tx-data-bits', 'TX data bits'),
('rx-break', 'RX break'),
('tx-break', 'TX break'),
+ ('rx-packet', 'RX packet'),
+ ('tx-packet', 'TX packet'),
)
annotation_rows = (
('rx-data', 'RX', (0, 2, 4, 6, 8)),
('rx-data-bits', 'RX bits', (12,)),
('rx-warnings', 'RX warnings', (10,)),
('rx-break', 'RX break', (14,)),
+ ('rx-packets', 'RX packets', (16,)),
('tx-data', 'TX', (1, 3, 5, 7, 9)),
('tx-data-bits', 'TX bits', (13,)),
('tx-warnings', 'TX warnings', (11,)),
('tx-break', 'TX break', (15,)),
+ ('tx-packets', 'TX packets', (17,)),
)
binary = (
('rx', 'RX dump'),
s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+ def putx_packet(self, rxtx, data):
+ s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+
def putpx(self, rxtx, data):
s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
+ self.frame_valid = [None, None]
self.startbit = [-1, -1]
self.cur_data_bit = [0, 0]
self.datavalue = [0, 0]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
self.databits = [[], []]
self.break_start = [None, None]
+ self.packet_cache = [[], []]
+ self.ss_packet, self.es_packet = [None, None], [None, None]
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
def wait_for_start_bit(self, rxtx, signal):
# Save the sample number where the start bit begins.
self.frame_start[rxtx] = self.samplenum
+ self.frame_valid[rxtx] = True
self.state[rxtx] = 'GET START BIT'
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.frame_valid[rxtx] = False
+ es = self.samplenum + ceil(self.bit_width / 2.0)
+ self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
+ (self.datavalue[rxtx], self.frame_valid[rxtx])])
self.state[rxtx] = 'WAIT FOR START BIT'
return
self.state[rxtx] = 'GET DATA BITS'
+ def handle_packet(self, rxtx):
+ d = 'rx' if (rxtx == RX) else 'tx'
+ delim = self.options[d + '_packet_delimiter']
+ plen = self.options[d + '_packet_len']
+ if delim == -1 and plen == -1:
+ return
+
+ # Cache data values until we see the delimiter and/or the specified
+ # packet length has been reached (whichever happens first).
+ if len(self.packet_cache[rxtx]) == 0:
+ self.ss_packet[rxtx] = self.startsample[rxtx]
+ self.packet_cache[rxtx].append(self.datavalue[rxtx])
+ if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
+ self.es_packet[rxtx] = self.samplenum
+ s = ''
+ for b in self.packet_cache[rxtx]:
+ s += self.format_value(b)
+ if self.options['format'] != 'ascii':
+ s += ' '
+ if self.options['format'] != 'ascii' and s[-1] == ' ':
+ s = s[:-1] # Drop trailing space.
+ self.putx_packet(rxtx, [16 + rxtx, [s]])
+ self.packet_cache[rxtx] = []
+
def get_data_bits(self, rxtx, signal):
# Save the sample number of the middle of the first data bit.
if self.startsample[rxtx] == -1:
self.putbin(rxtx, [rxtx, bdata])
self.putbin(rxtx, [2, bdata])
+ self.handle_packet(rxtx)
+
self.databits[rxtx] = []
# Advance to either reception of the parity bit, or reception of
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
+ self.frame_valid[rxtx] = False
self.state[rxtx] = 'GET STOP BITS'
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
- # TODO: Abort? Ignore the frame? Other?
+ self.frame_valid[rxtx] = False
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
+ # Pass the complete UART frame to upper layers.
+ es = self.samplenum + ceil(self.bit_width / 2.0)
+ self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
+ (self.datavalue[rxtx], self.frame_valid[rxtx])])
+
self.state[rxtx] = 'WAIT FOR START BIT'
def handle_break(self, rxtx):
projects / libsigrokdecode.git / blobdiff