# 'signals': [{'SCL': }]}
#
+import sigrok
+
+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
class Sample():
def __init__(self, data):
self.data = data
for i in range(0, len(data), unitsize):
yield(Sample(data[i:i+unitsize]))
-class Decoder():
+class Decoder(sigrok.Decoder):
+ id = 'i2c'
name = 'I2C'
longname = 'Inter-Integrated Circuit (I2C) bus'
desc = 'I2C is a two-wire, multi-master, serial bus.'
self.startsample = -1
self.is_repeat_start = 0
- self.FIND_START, self.FIND_ADDRESS, self.FIND_DATA = range(3)
- self.state = self.FIND_START
+ self.state = FIND_START
# Get the channel/probe number of the SCL/SDA signals.
self.scl_bit = self.probes['scl']['ch']
# 'data': None, 'ann': None},
o = (self.is_repeat_start == 1) and 'Sr' or 'S'
out.append(o)
- self.state = self.FIND_ADDRESS
+ self.state = FIND_ADDRESS
self.bitcount = self.databyte = 0
self.is_repeat_start = 1
self.wr = -1
# We received 8 address/data bits and the ACK/NACK bit.
self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
+ ack = 'N' if (sda == 1) else 'A'
- if self.state == self.FIND_ADDRESS:
+ if self.state == FIND_ADDRESS:
d = self.databyte & 0xfe
# The READ/WRITE bit is only in address bytes, not data bytes.
- self.wr = (self.databyte & 1) and 1 or 0
- elif self.state == self.FIND_DATA:
+ self.wr = 1 if (self.databyte & 1) else 0
+ elif self.state == FIND_DATA:
d = self.databyte
else:
# TODO: Error?
o = {'data': '0x%02x' % d}
# TODO: Simplify.
- if self.state == self.FIND_ADDRESS and self.wr == 1:
+ if self.state == FIND_ADDRESS and self.wr == 1:
o['type'] = 'AW'
- elif self.state == self.FIND_ADDRESS and self.wr == 0:
+ elif self.state == FIND_ADDRESS and self.wr == 0:
o['type'] = 'AR'
- elif self.state == self.FIND_DATA and self.wr == 1:
+ elif self.state == FIND_DATA and self.wr == 1:
o['type'] = 'DW'
- elif self.state == self.FIND_DATA and self.wr == 0:
+ elif self.state == FIND_DATA and self.wr == 0:
o['type'] = 'DR'
out.append(o)
self.bitcount = self.databyte = 0
self.startsample = -1
- if self.state == self.FIND_ADDRESS:
- self.state = self.FIND_DATA
- elif self.state == self.FIND_DATA:
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
# There could be multiple data bytes in a row.
# So, either find a STOP condition or another data byte next.
pass
# 'data': None, 'ann': None},
o = 'P'
out.append(o)
- self.state = self.FIND_START
+ self.state = FIND_START
self.is_repeat_start = 0
self.wr = -1
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.
- if self.state == self.FIND_START:
+ if self.state == FIND_START:
if self.is_start_condition(scl, sda):
out += self.find_start(scl, sda)
- elif self.state == self.FIND_ADDRESS:
+ elif self.state == FIND_ADDRESS:
if self.is_data_bit(scl, sda):
out += self.find_address_or_data(scl, sda)
- elif self.state == self.FIND_DATA:
+ elif self.state == FIND_DATA:
if self.is_data_bit(scl, sda):
out += self.find_address_or_data(scl, sda)
elif self.is_start_condition(scl, sda):
self.oldsda = sda
if out != []:
- sigrok.put(out)
-
-import sigrok
+ self.put(out)