adf435x: Python list idioms in bits sequence accumulation

[libsigrokdecode.git] / decoders / adf435x / pd.py

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 9ba88ca9c698d49907224c675a9a828ab5a36e9a..7810190d90f390bde596ae97c3a06fe172430290 100644 (file)
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -18,6 +18,7 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import bitpack_lsb
 
 def disabled_enabled(v):
     return ['Disabled', 'Enabled'][v]
@@ -118,8 +119,10 @@ class Decoder(srd.Decoder):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def decode_bits(self, offset, width):
-        return (sum([(1 << i) if self.bits[offset + i][0] else 0 for i in range(width)]),
-            (self.bits[offset + width - 1][1], self.bits[offset][2]))
+        bits = self.bits[offset:][:width]
+        ss, es = bits[-1][1], bits[0][2]
+        value = bitpack_lsb(bits, 0)
+        return ( value, ( ss, es, ))
 
     def decode_field(self, name, offset, width, parser):
         val, pos = self.decode_bits(offset, width)
@@ -132,6 +135,7 @@ class Decoder(srd.Decoder):
 
         if ptype == 'TRANSFER':
             if len(self.bits) == 32:
+                self.bits.reverse()
                 reg_value, reg_pos = self.decode_bits(0, 3)
                 self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
                     ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
@@ -143,8 +147,14 @@ class Decoder(srd.Decoder):
             else:
                 error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
                 self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
-            self.bits = []
+            self.bits.clear()
 
         if ptype == 'BITS':
             _, mosi_bits, miso_bits = data
-            self.bits = mosi_bits + self.bits
+            # Cope with the lower layer SPI decoder's output convention:
+            # Regardless of wire transfer's frame format, .decode() input
+            # provides BITS in the LE order. Accumulate in MSB order here,
+            # and reverse before data processing when 'TRANSFER' is seen.
+            mosi_bits = mosi_bits.copy()
+            mosi_bits.reverse()
+            self.bits.extend(mosi_bits)