- # Data is transmitted LSB-first.
- self.databyte |= (io << self.bitcount)
-
- # Remember the start of the first data/address bit.
- if self.bitcount == 0:
- self.ss_byte = self.samplenum
-
- # Store individual bits and their start/end samplenumbers.
- # In the list, index 0 represents the LSB (SLE44xx transmits LSB-first).
- self.bits.insert(0, [io, self.samplenum, self.samplenum])
- if self.bitcount > 0:
- self.bits[1][2] = self.samplenum
- if self.bitcount == 7:
- self.bitwidth = self.bits[1][2] - self.bits[2][2]
- self.bits[0][2] += self.bitwidth
-
- # Return if we haven't collected all 8 bits, yet.
- if self.bitcount < 7:
- self.bitcount += 1
+ # Remember the start of the first data/address bit. Collect
+ # bits in LSB first order. "Estimate" the bit's width at first,
+ # update end times as better data becomes available.
+ # TODO This estimation logic is imprecise and fragile. A single
+ # slightly stretched clock period throws off the following bit
+ # annotation. Better look for more reliable conditions. Available
+ # documentation suggests bit values are valid during high CLK.
+ bit_val = io
+ bit_ss = self.samplenum
+ bit_es = bit_ss # self.bitwidth is not known yet.
+ if self.bits:
+ self.bits[-1][2] = bit_ss
+ self.bits.append([bit_val, bit_ss, bit_es])
+ if len(self.bits) < 8: