(0, 1): 'LS_J',
(1, 1): 'SE1',
},
+ # After a PREamble PID, the bus segment between Host and Hub uses LS
+ # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
+ # both upstream and downstream low-speed data, the hub is responsible for
+ # inverting the polarity of the data before transmitting to/from a
+ # low-speed port.").
+ 'low-speed-rp': {
+ # (<dp>, <dm>): <symbol/state>
+ (0, 0): 'SE0',
+ (1, 0): 'J',
+ (0, 1): 'K',
+ (1, 1): 'SE1',
+ },
}
bitrates = {
- 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
'automatic': None
}
self.oldpins = None
self.edgepins = None
self.consecutive_ones = 0
+ self.bits = None
self.state = 'INIT'
def start(self):
if sym != 'K' or self.oldsym != 'J':
return
self.consecutive_ones = 0
+ self.bits = ''
self.update_bitrate()
self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
self.set_new_target_samplenum()
# Got an EOP.
self.putpm(['EOP', None])
self.putm([5, ['EOP', 'E']])
- self.state = 'IDLE'
+ self.state = 'WAIT IDLE'
else:
self.putpm(['ERR', None])
self.putm([8, ['EOP Error', 'EErr', 'E']])
def get_bit(self, sym):
self.set_new_target_samplenum()
+ b = '0' if self.oldsym != sym else '1'
+ self.oldsym = sym
if sym == 'SE0':
# Start of an EOP. Change state, save edge
self.state = 'GET EOP'
self.ss_block = self.samplenum_lastedge
else:
- b = '0' if self.oldsym != sym else '1'
self.handle_bit(b)
self.putpb(['SYM', sym])
self.putb(sym_annotation[sym])
- if self.oldsym != sym:
+ if len(self.bits) <= 16:
+ self.bits += b
+ if len(self.bits) == 16 and self.bits == '0000000100111100':
+ # Sync and low-speed PREamble seen
+ self.putpx(['EOP', None])
+ self.state = 'IDLE'
+ self.signalling = 'low-speed-rp'
+ self.update_bitrate()
+ self.oldsym = 'J'
+ if b == '0':
edgesym = symbols[self.signalling][tuple(self.edgepins)]
if edgesym not in ('SE0', 'SE1'):
if edgesym == sym:
else:
self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
self.samplepos = self.samplepos + (0.01 * self.bitwidth)
- self.oldsym = sym
def handle_idle(self, sym):
self.samplenum_edge = self.samplenum