Use self.out_binary naming consistently across all PDs.

diff --git a/decoders/eeprom24xx/pd.py b/decoders/eeprom24xx/pd.py
index 928a1f7756d8ed61b1ab79124ca6d94c7a49ff36..386431e12419144f53e7c7359e9e968a04d489e4 100644 (file)
--- a/decoders/eeprom24xx/pd.py
+++ b/decoders/eeprom24xx/pd.py
@@ -78,7 +78,7 @@ class Decoder(srd.Decoder):
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.chip = chips[self.options['chip']]
         self.addr_counter = self.options['addr_counter']
 
@@ -86,7 +86,7 @@ class Decoder(srd.Decoder):
         self.put(self.ss_block, self.es_block, self.out_ann, data)
 
     def putbin(self, data):
-        self.put(self.ss_block, self.es_block, self.out_bin, data)
+        self.put(self.ss_block, self.es_block, self.out_binary, data)
 
     def putbits(self, bit1, bit2, bits, data):
         self.put(bits[bit1][1], bits[bit2][2], self.out_ann, data)

diff --git a/decoders/i2s/pd.py b/decoders/i2s/pd.py
index eeeea2012d6e80211711faca7db7792498ba602a..6b94c1052ed031a223d42a9ec33ce5068ebcfa8a 100644 (file)
--- a/decoders/i2s/pd.py
+++ b/decoders/i2s/pd.py
@@ -73,7 +73,7 @@ class Decoder(srd.Decoder):
 
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def metadata(self, key, value):
@@ -84,7 +84,7 @@ class Decoder(srd.Decoder):
         self.put(self.ss_block, self.samplenum, self.out_python, data)
 
     def putbin(self, data):
-        self.put(self.ss_block, self.samplenum, self.out_bin, data)
+        self.put(self.ss_block, self.samplenum, self.out_binary, data)
 
     def putb(self, data):
         self.put(self.ss_block, self.samplenum, self.out_ann, data)
@@ -154,7 +154,7 @@ class Decoder(srd.Decoder):
             if self.ss_block is not None:
 
                 if not self.wrote_wav_header:
-                    self.put(0, 0, self.out_bin, [0, self.wav_header()])
+                    self.put(0, 0, self.out_binary, [0, self.wav_header()])
                     self.wrote_wav_header = True
 
                 self.samplesreceived += 1

diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py
index d40c643ed64303fe7cffdc32f5c9822181c6010a..ba1bffacb48b55c2925143f201446d59ff71864e 100644 (file)
--- a/decoders/jitter/pd.py
+++ b/decoders/jitter/pd.py
@@ -77,7 +77,7 @@ class Decoder(srd.Decoder):
         self.clk_edge = edge_detector[self.options['clk_polarity']]
         self.sig_edge = edge_detector[self.options['sig_polarity']]
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_clk_missed = self.register(srd.OUTPUT_META,
             meta=(int, 'Clock missed', 'Clock transition missed'))
         self.out_sig_missed = self.register(srd.OUTPUT_META,
@@ -111,7 +111,7 @@ class Decoder(srd.Decoder):
             return
         # Format the delta to an ASCII float value terminated by a newline.
         x = str(delta) + '\n'
-        self.put(self.clk_start, self.sig_start, self.out_bin,
+        self.put(self.clk_start, self.sig_start, self.out_binary,
                  [0, x.encode('UTF-8')])
 
     # Helper function for missed clock and signal annotations.

diff --git a/decoders/pwm/pd.py b/decoders/pwm/pd.py
index 7b10d977525426d93ec591863f0654574ba1d67d..7bf21f4637aec242f21758b161ec6705c4c210eb 100644 (file)
--- a/decoders/pwm/pd.py
+++ b/decoders/pwm/pd.py
@@ -66,7 +66,7 @@ class Decoder(srd.Decoder):
     def start(self):
         self.startedge = 0 if self.options['polarity'] == 'active-low' else 1
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_average = \
             self.register(srd.OUTPUT_META,
                           meta=(float, 'Average', 'PWM base (cycle) frequency'))
@@ -92,7 +92,7 @@ class Decoder(srd.Decoder):
         self.put(self.ss, self.es, self.out_ann, [1, [period_s]])
 
     def putb(self, data):
-        self.put(self.num_cycles, self.num_cycles, self.out_bin, data)
+        self.put(self.num_cycles, self.num_cycles, self.out_binary, data)
 
     def decode(self, ss, es, data):
 

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 864bca6795d55d0e3ca9ffcfbc2196c61e0e41f6..fc8c7d0024bf8169c431566cb87245211b6d2ed0 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -149,7 +149,7 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
 
@@ -165,10 +165,10 @@ class Decoder(srd.Decoder):
 
         if self.have_miso:
             ss, es = self.misobits[-1][1], self.misobits[0][2]
-            self.put(ss, es, self.out_bin, [0, bytes([so])])
+            self.put(ss, es, self.out_binary, [0, bytes([so])])
         if self.have_mosi:
             ss, es = self.mosibits[-1][1], self.mosibits[0][2]
-            self.put(ss, es, self.out_bin, [1, bytes([si])])
+            self.put(ss, es, self.out_binary, [1, bytes([si])])
 
         self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
         self.put(ss, es, self.out_python, ['DATA', si, so])

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 4c37c344ecf341a72f777713c512d0078738d552..d42a5d42a4c9a89537e4b78b773dcc1cf24db3fb 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -157,7 +157,7 @@ class Decoder(srd.Decoder):
 
     def putbin(self, rxtx, data):
         s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
-        self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_bin, data)
+        self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
 
     def __init__(self, **kwargs):
         self.samplerate = None
@@ -176,7 +176,7 @@ class Decoder(srd.Decoder):
 
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def metadata(self, key, value):

diff --git a/decoders/usb_request/pd.py b/decoders/usb_request/pd.py
index fa2e674880565799f2b91fc4caf33610bac4f6a3..79539c6b9deea853caefccb2eac8ca0fe1631e98 100644 (file)
--- a/decoders/usb_request/pd.py
+++ b/decoders/usb_request/pd.py
@@ -152,7 +152,7 @@ class Decoder(srd.Decoder):
         self.put(ss, es, self.out_ann, data)
 
     def putb(self, ts, data):
-        self.put(ts, ts, self.out_bin, data)
+        self.put(ts, ts, self.out_binary, data)
 
     def pcap_global_header(self):
         # See https://wiki.wireshark.org/Development/LibpcapFileFormat.
@@ -173,7 +173,7 @@ class Decoder(srd.Decoder):
             self.secs_per_sample = float(1) / float(self.samplerate)
 
     def start(self):
-        self.out_bin = self.register(srd.OUTPUT_BINARY)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_transfer(self):
@@ -242,7 +242,7 @@ class Decoder(srd.Decoder):
 
     def write_pcap_header(self):
         if not self.wrote_pcap_header:
-            self.put(0, 0, self.out_bin, [0, self.pcap_global_header()])
+            self.put(0, 0, self.out_binary, [0, self.pcap_global_header()])
             self.wrote_pcap_header = True
 
     def request_summary(self, request):