2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 /* Initialize the logic analyzer mode. */
84 static uint8_t logic_mode_start[] = {
85 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
86 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
89 static const char *sigma_firmware_files[] = {
90 /* 50 MHz, supports 8 bit fractions */
91 FIRMWARE_DIR "/asix-sigma-50.fw",
93 FIRMWARE_DIR "/asix-sigma-100.fw",
95 FIRMWARE_DIR "/asix-sigma-200.fw",
96 /* Synchronous clock from pin */
97 FIRMWARE_DIR "/asix-sigma-50sync.fw",
98 /* Frequency counter */
99 FIRMWARE_DIR "/asix-sigma-phasor.fw",
102 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
108 sr_err("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&devc->ftdic));
115 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
121 sr_err("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&devc->ftdic));
123 } else if ((size_t) ret != size) {
124 sr_err("ftdi_write_data did not complete write.");
130 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
134 uint8_t buf[len + 2];
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
140 for (i = 0; i < len; ++i) {
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
145 return sigma_write(buf, idx, devc);
148 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
150 return sigma_write_register(reg, &value, 1, devc);
153 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
154 struct dev_context *devc)
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
160 buf[2] = REG_READ_ADDR;
162 sigma_write(buf, sizeof(buf), devc);
164 return sigma_read(data, len, devc);
167 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
172 sr_err("sigma_get_register: 1 byte expected");
179 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
180 struct dev_context *devc)
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
194 sigma_write(buf, sizeof(buf), devc);
196 sigma_read(result, sizeof(result), devc);
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
211 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
212 uint8_t *data, struct dev_context *devc)
218 /* Send the startchunk. Index start with 1. */
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
227 for (i = 0; i < numchunks; ++i) {
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_WAIT_ACK;
238 sigma_write(buf, idx, devc);
240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
243 /* Upload trigger look-up tables to Sigma. */
244 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
256 if (lut->m2d[0] & bit)
258 if (lut->m2d[1] & bit)
260 if (lut->m2d[2] & bit)
262 if (lut->m2d[3] & bit)
272 if (lut->m0d[0] & bit)
274 if (lut->m0d[1] & bit)
276 if (lut->m0d[2] & bit)
278 if (lut->m0d[3] & bit)
281 if (lut->m1d[0] & bit)
283 if (lut->m1d[1] & bit)
285 if (lut->m1d[2] & bit)
287 if (lut->m1d[3] & bit)
290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
297 sizeof(lut->params), devc);
302 static void clear_helper(void *priv)
304 struct dev_context *devc;
308 ftdi_deinit(&devc->ftdic);
311 static int dev_clear(void)
313 return std_dev_clear(di, clear_helper);
316 static int init(struct sr_context *sr_ctx)
318 return std_init(sr_ctx, di, LOG_PREFIX);
321 static GSList *scan(GSList *options)
323 struct sr_dev_inst *sdi;
324 struct sr_channel *ch;
325 struct drv_context *drvc;
326 struct dev_context *devc;
328 struct ftdi_device_list *devlist;
340 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
341 sr_err("%s: devc malloc failed", __func__);
345 ftdi_init(&devc->ftdic);
347 /* Look for SIGMAs. */
349 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
350 USB_VENDOR, USB_PRODUCT)) <= 0) {
352 sr_err("ftdi_usb_find_all(): %d", ret);
356 /* Make sure it's a version 1 or 2 SIGMA. */
357 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
358 serial_txt, sizeof(serial_txt));
359 sscanf(serial_txt, "%x", &serial);
361 if (serial < 0xa6010000 || serial > 0xa602ffff) {
362 sr_err("Only SIGMA and SIGMA2 are supported "
363 "in this version of libsigrok.");
367 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
369 devc->cur_samplerate = 0;
371 devc->limit_msec = 0;
372 devc->cur_firmware = -1;
373 devc->num_channels = 0;
374 devc->samples_per_event = 0;
375 devc->capture_ratio = 50;
376 devc->use_triggers = 0;
378 /* Register SIGMA device. */
379 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
380 USB_MODEL_NAME, NULL))) {
381 sr_err("%s: sdi was NULL", __func__);
386 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
387 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
391 sdi->channels = g_slist_append(sdi->channels, ch);
394 devices = g_slist_append(devices, sdi);
395 drvc->instances = g_slist_append(drvc->instances, sdi);
398 /* We will open the device again when we need it. */
399 ftdi_list_free(&devlist);
404 ftdi_deinit(&devc->ftdic);
409 static GSList *dev_list(void)
411 return ((struct drv_context *)(di->priv))->instances;
415 * Configure the FPGA for bitbang mode.
416 * This sequence is documented in section 2. of the ASIX Sigma programming
417 * manual. This sequence is necessary to configure the FPGA in the Sigma
418 * into Bitbang mode, in which it can be programmed with the firmware.
420 static int sigma_fpga_init_bitbang(struct dev_context *devc)
422 uint8_t suicide[] = {
423 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
425 uint8_t init_array[] = {
426 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
429 int i, ret, timeout = 10000;
432 /* Section 2. part 1), do the FPGA suicide. */
433 sigma_write(suicide, sizeof(suicide), devc);
434 sigma_write(suicide, sizeof(suicide), devc);
435 sigma_write(suicide, sizeof(suicide), devc);
436 sigma_write(suicide, sizeof(suicide), devc);
438 /* Section 2. part 2), do pulse on D1. */
439 sigma_write(init_array, sizeof(init_array), devc);
440 ftdi_usb_purge_buffers(&devc->ftdic);
442 /* Wait until the FPGA asserts D6/INIT_B. */
443 for (i = 0; i < timeout; i++) {
444 ret = sigma_read(&data, 1, devc);
447 /* Test if pin D6 got asserted. */
450 /* The D6 was not asserted yet, wait a bit. */
454 return SR_ERR_TIMEOUT;
458 * Read the firmware from a file and transform it into a series of bitbang
459 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
460 * by the caller of this function.
462 static int sigma_fw_2_bitbang(const char *filename,
463 uint8_t **bb_cmd, gsize *bb_cmd_size)
467 gsize i, file_size, bb_size;
469 uint8_t *bb_stream, *bbs;
475 * Map the file and make the mapped buffer writable.
476 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
477 * will be modified. It will not be modified until someone uses
478 * g_file_set_contents() on it.
481 file = g_mapped_file_new(filename, TRUE, &error);
482 g_assert_no_error(error);
484 file_size = g_mapped_file_get_length(file);
485 firmware = g_mapped_file_get_contents(file);
488 /* Weird magic transformation below, I have no idea what it does. */
490 for (i = 0; i < file_size; i++) {
491 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
492 firmware[i] ^= imm & 0xff;
496 * Now that the firmware is "transformed", we will transcribe the
497 * firmware blob into a sequence of toggles of the Dx wires. This
498 * sequence will be fed directly into the Sigma, which must be in
499 * the FPGA bitbang programming mode.
502 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
503 bb_size = file_size * 8 * 2;
504 bb_stream = (uint8_t *)g_try_malloc(bb_size);
506 sr_err("%s: Failed to allocate bitbang stream", __func__);
512 for (i = 0; i < file_size; i++) {
513 for (bit = 7; bit >= 0; bit--) {
514 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
520 /* The transformation completed successfully, return the result. */
522 *bb_cmd_size = bb_size;
525 g_mapped_file_unref(file);
529 static int upload_firmware(int firmware_idx, struct dev_context *devc)
535 unsigned char result[32];
536 const char *firmware = sigma_firmware_files[firmware_idx];
537 struct ftdi_context *ftdic = &devc->ftdic;
539 /* Make sure it's an ASIX SIGMA. */
540 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
541 USB_DESCRIPTION, NULL);
543 sr_err("ftdi_usb_open failed: %s",
544 ftdi_get_error_string(ftdic));
548 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
550 sr_err("ftdi_set_bitmode failed: %s",
551 ftdi_get_error_string(ftdic));
555 /* Four times the speed of sigmalogan - Works well. */
556 ret = ftdi_set_baudrate(ftdic, 750000);
558 sr_err("ftdi_set_baudrate failed: %s",
559 ftdi_get_error_string(ftdic));
563 /* Initialize the FPGA for firmware upload. */
564 ret = sigma_fpga_init_bitbang(devc);
568 /* Prepare firmware. */
569 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
571 sr_err("An error occured while reading the firmware: %s",
576 /* Upload firmare. */
577 sr_info("Uploading firmware file '%s'.", firmware);
578 sigma_write(buf, buf_size, devc);
582 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
584 sr_err("ftdi_set_bitmode failed: %s",
585 ftdi_get_error_string(ftdic));
589 ftdi_usb_purge_buffers(ftdic);
591 /* Discard garbage. */
592 while (sigma_read(&pins, 1, devc) == 1)
595 /* Initialize the logic analyzer mode. */
596 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
598 /* Expect a 3 byte reply. */
599 ret = sigma_read(result, 3, devc);
601 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
602 sr_err("Configuration failed. Invalid reply received.");
606 devc->cur_firmware = firmware_idx;
608 sr_info("Firmware uploaded.");
613 static int dev_open(struct sr_dev_inst *sdi)
615 struct dev_context *devc;
620 /* Make sure it's an ASIX SIGMA. */
621 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
622 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
624 sr_err("ftdi_usb_open failed: %s",
625 ftdi_get_error_string(&devc->ftdic));
630 sdi->status = SR_ST_ACTIVE;
635 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
637 struct dev_context *devc;
644 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
645 if (samplerates[i] == samplerate)
648 if (samplerates[i] == 0)
649 return SR_ERR_SAMPLERATE;
651 if (samplerate <= SR_MHZ(50)) {
652 ret = upload_firmware(0, devc);
653 devc->num_channels = 16;
655 if (samplerate == SR_MHZ(100)) {
656 ret = upload_firmware(1, devc);
657 devc->num_channels = 8;
659 else if (samplerate == SR_MHZ(200)) {
660 ret = upload_firmware(2, devc);
661 devc->num_channels = 4;
664 devc->cur_samplerate = samplerate;
665 devc->period_ps = 1000000000000ULL / samplerate;
666 devc->samples_per_event = 16 / devc->num_channels;
667 devc->state.state = SIGMA_IDLE;
673 * In 100 and 200 MHz mode, only a single pin rising/falling can be
674 * set as trigger. In other modes, two rising/falling triggers can be set,
675 * in addition to value/mask trigger for any number of channels.
677 * The Sigma supports complex triggers using boolean expressions, but this
678 * has not been implemented yet.
680 static int configure_channels(const struct sr_dev_inst *sdi)
682 struct dev_context *devc = sdi->priv;
683 const struct sr_channel *ch;
688 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
690 for (l = sdi->channels; l; l = l->next) {
691 ch = (struct sr_channel *)l->data;
692 channelbit = 1 << (ch->index);
694 if (!ch->enabled || !ch->trigger)
697 if (devc->cur_samplerate >= SR_MHZ(100)) {
698 /* Fast trigger support. */
700 sr_err("Only a single pin trigger in 100 and "
701 "200MHz mode is supported.");
704 if (ch->trigger[0] == 'f')
705 devc->trigger.fallingmask |= channelbit;
706 else if (ch->trigger[0] == 'r')
707 devc->trigger.risingmask |= channelbit;
709 sr_err("Only rising/falling trigger in 100 "
710 "and 200MHz mode is supported.");
716 /* Simple trigger support (event). */
717 if (ch->trigger[0] == '1') {
718 devc->trigger.simplevalue |= channelbit;
719 devc->trigger.simplemask |= channelbit;
721 else if (ch->trigger[0] == '0') {
722 devc->trigger.simplevalue &= ~channelbit;
723 devc->trigger.simplemask |= channelbit;
725 else if (ch->trigger[0] == 'f') {
726 devc->trigger.fallingmask |= channelbit;
729 else if (ch->trigger[0] == 'r') {
730 devc->trigger.risingmask |= channelbit;
735 * Actually, Sigma supports 2 rising/falling triggers,
736 * but they are ORed and the current trigger syntax
737 * does not permit ORed triggers.
739 if (trigger_set > 1) {
740 sr_err("Only 1 rising/falling trigger "
747 devc->use_triggers = 1;
753 static int dev_close(struct sr_dev_inst *sdi)
755 struct dev_context *devc;
760 if (sdi->status == SR_ST_ACTIVE)
761 ftdi_usb_close(&devc->ftdic);
763 sdi->status = SR_ST_INACTIVE;
768 static int cleanup(void)
773 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
774 const struct sr_channel_group *cg)
776 struct dev_context *devc;
781 case SR_CONF_SAMPLERATE:
784 *data = g_variant_new_uint64(devc->cur_samplerate);
795 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
796 const struct sr_channel_group *cg)
798 struct dev_context *devc;
799 uint64_t num_samples;
804 if (sdi->status != SR_ST_ACTIVE)
805 return SR_ERR_DEV_CLOSED;
810 case SR_CONF_SAMPLERATE:
811 ret = set_samplerate(sdi, g_variant_get_uint64(data));
813 case SR_CONF_LIMIT_MSEC:
814 devc->limit_msec = g_variant_get_uint64(data);
815 if (devc->limit_msec > 0)
820 case SR_CONF_LIMIT_SAMPLES:
821 num_samples = g_variant_get_uint64(data);
822 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
824 case SR_CONF_CAPTURE_RATIO:
825 devc->capture_ratio = g_variant_get_uint64(data);
826 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
838 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
839 const struct sr_channel_group *cg)
848 case SR_CONF_DEVICE_OPTIONS:
849 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
850 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
852 case SR_CONF_SAMPLERATE:
853 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
854 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
855 ARRAY_SIZE(samplerates), sizeof(uint64_t));
856 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
857 *data = g_variant_builder_end(&gvb);
859 case SR_CONF_TRIGGER_TYPE:
860 *data = g_variant_new_string(TRIGGER_TYPE);
869 /* Software trigger to determine exact trigger position. */
870 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
871 struct sigma_trigger *t)
875 for (i = 0; i < 8; ++i) {
877 last_sample = samples[i-1];
879 /* Simple triggers. */
880 if ((samples[i] & t->simplemask) != t->simplevalue)
884 if ((last_sample & t->risingmask) != 0 || (samples[i] &
885 t->risingmask) != t->risingmask)
889 if ((last_sample & t->fallingmask) != t->fallingmask ||
890 (samples[i] & t->fallingmask) != 0)
896 /* If we did not match, return original trigger pos. */
901 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
902 * Each event is 20ns apart, and can contain multiple samples.
904 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
905 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
906 * For 50 MHz and below, events contain one sample for each channel,
907 * spread 20 ns apart.
909 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
910 uint16_t *lastsample, int triggerpos,
911 uint16_t limit_chunk, void *cb_data)
913 struct sr_dev_inst *sdi = cb_data;
914 struct dev_context *devc = sdi->priv;
916 uint16_t samples[65536 * devc->samples_per_event];
917 struct sr_datafeed_packet packet;
918 struct sr_datafeed_logic logic;
919 int i, j, k, l, numpad, tosend;
920 size_t n = 0, sent = 0;
921 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
926 /* Check if trigger is in this chunk. */
927 if (triggerpos != -1) {
928 if (devc->cur_samplerate <= SR_MHZ(50))
929 triggerpos -= EVENTS_PER_CLUSTER - 1;
934 /* Find in which cluster the trigger occured. */
935 triggerts = triggerpos / 7;
939 for (i = 0; i < 64; ++i) {
940 ts = *(uint16_t *) &buf[i * 16];
941 tsdiff = ts - *lastts;
944 /* Decode partial chunk. */
945 if (limit_chunk && ts > limit_chunk)
948 /* Pad last sample up to current point. */
949 numpad = tsdiff * devc->samples_per_event - clustersize;
951 for (j = 0; j < numpad; ++j)
952 samples[j] = *lastsample;
957 /* Send samples between previous and this timestamp to sigrok. */
960 tosend = MIN(2048, n - sent);
962 packet.type = SR_DF_LOGIC;
963 packet.payload = &logic;
964 logic.length = tosend * sizeof(uint16_t);
966 logic.data = samples + sent;
967 sr_session_send(devc->cb_data, &packet);
973 event = (uint16_t *) &buf[i * 16 + 2];
976 /* For each event in cluster. */
977 for (j = 0; j < 7; ++j) {
979 /* For each sample in event. */
980 for (k = 0; k < devc->samples_per_event; ++k) {
983 /* For each channel. */
984 for (l = 0; l < devc->num_channels; ++l)
985 cur_sample |= (!!(event[j] & (1 << (l *
986 devc->samples_per_event + k)))) << l;
988 samples[n++] = cur_sample;
992 /* Send data up to trigger point (if triggered). */
994 if (i == triggerts) {
996 * Trigger is not always accurate to sample because of
997 * pipeline delay. However, it always triggers before
998 * the actual event. We therefore look at the next
999 * samples to pinpoint the exact position of the trigger.
1001 tosend = get_trigger_offset(samples, *lastsample,
1005 packet.type = SR_DF_LOGIC;
1006 packet.payload = &logic;
1007 logic.length = tosend * sizeof(uint16_t);
1009 logic.data = samples;
1010 sr_session_send(devc->cb_data, &packet);
1015 /* Only send trigger if explicitly enabled. */
1016 if (devc->use_triggers) {
1017 packet.type = SR_DF_TRIGGER;
1018 sr_session_send(devc->cb_data, &packet);
1022 /* Send rest of the chunk to sigrok. */
1026 packet.type = SR_DF_LOGIC;
1027 packet.payload = &logic;
1028 logic.length = tosend * sizeof(uint16_t);
1030 logic.data = samples + sent;
1031 sr_session_send(devc->cb_data, &packet);
1034 *lastsample = samples[n - 1];
1040 static void download_capture(struct sr_dev_inst *sdi)
1042 struct dev_context *devc;
1043 const int chunks_per_read = 32;
1044 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1045 int bufsz, i, numchunks, newchunks;
1047 sr_info("Downloading sample data.");
1050 devc->state.chunks_downloaded = 0;
1051 numchunks = (devc->state.stoppos + 511) / 512;
1052 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1054 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1055 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1058 /* Find first ts. */
1059 if (devc->state.chunks_downloaded == 0) {
1060 devc->state.lastts = RL16(buf) - 1;
1061 devc->state.lastsample = 0;
1064 /* Decode chunks and send them to sigrok. */
1065 for (i = 0; i < newchunks; ++i) {
1066 int limit_chunk = 0;
1068 /* The last chunk may potentially be only in part. */
1069 if (devc->state.chunks_downloaded == numchunks - 1) {
1070 /* Find the last valid timestamp */
1071 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1074 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1075 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1076 &devc->state.lastts,
1077 &devc->state.lastsample,
1078 devc->state.triggerpos & 0x1ff,
1081 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1082 &devc->state.lastts,
1083 &devc->state.lastsample,
1084 -1, limit_chunk, sdi);
1086 ++devc->state.chunks_downloaded;
1091 static int receive_data(int fd, int revents, void *cb_data)
1093 struct sr_dev_inst *sdi;
1094 struct dev_context *devc;
1095 struct sr_datafeed_packet packet;
1096 uint64_t running_msec;
1107 /* Get the current position. */
1108 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1110 if (devc->state.state == SIGMA_IDLE)
1113 if (devc->state.state == SIGMA_CAPTURE) {
1114 numchunks = (devc->state.stoppos + 511) / 512;
1116 /* Check if the timer has expired, or memory is full. */
1117 gettimeofday(&tv, 0);
1118 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1119 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1121 if (running_msec < devc->limit_msec && numchunks < 32767)
1122 /* Still capturing. */
1125 /* Stop acquisition. */
1126 sigma_set_register(WRITE_MODE, 0x11, devc);
1128 /* Set SDRAM Read Enable. */
1129 sigma_set_register(WRITE_MODE, 0x02, devc);
1131 /* Get the current position. */
1132 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1134 /* Check if trigger has fired. */
1135 modestatus = sigma_get_register(READ_MODE, devc);
1136 if (modestatus & 0x20)
1137 devc->state.triggerchunk = devc->state.triggerpos / 512;
1139 devc->state.triggerchunk = -1;
1141 /* Transfer captured data from device. */
1142 download_capture(sdi);
1145 packet.type = SR_DF_END;
1146 sr_session_send(sdi, &packet);
1148 dev_acquisition_stop(sdi, sdi);
1154 /* Build a LUT entry used by the trigger functions. */
1155 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1159 /* For each quad channel. */
1160 for (i = 0; i < 4; ++i) {
1163 /* For each bit in LUT. */
1164 for (j = 0; j < 16; ++j)
1166 /* For each channel in quad. */
1167 for (k = 0; k < 4; ++k) {
1168 bit = 1 << (i * 4 + k);
1170 /* Set bit in entry */
1172 ((!(value & bit)) !=
1174 entry[i] &= ~(1 << j);
1179 /* Add a logical function to LUT mask. */
1180 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1181 int index, int neg, uint16_t *mask)
1184 int x[2][2], tmp, a, b, aset, bset, rset;
1186 memset(x, 0, 4 * sizeof(int));
1188 /* Trigger detect condition. */
1218 case OP_NOTRISEFALL:
1224 /* Transpose if neg is set. */
1226 for (i = 0; i < 2; ++i) {
1227 for (j = 0; j < 2; ++j) {
1229 x[i][j] = x[1-i][1-j];
1235 /* Update mask with function. */
1236 for (i = 0; i < 16; ++i) {
1237 a = (i >> (2 * index + 0)) & 1;
1238 b = (i >> (2 * index + 1)) & 1;
1240 aset = (*mask >> i) & 1;
1243 if (func == FUNC_AND || func == FUNC_NAND)
1245 else if (func == FUNC_OR || func == FUNC_NOR)
1247 else if (func == FUNC_XOR || func == FUNC_NXOR)
1250 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1261 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1262 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1263 * set at any time, but a full mask and value can be set (0/1).
1265 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1268 uint16_t masks[2] = { 0, 0 };
1270 memset(lut, 0, sizeof(struct triggerlut));
1272 /* Contant for simple triggers. */
1275 /* Value/mask trigger support. */
1276 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1279 /* Rise/fall trigger support. */
1280 for (i = 0, j = 0; i < 16; ++i) {
1281 if (devc->trigger.risingmask & (1 << i) ||
1282 devc->trigger.fallingmask & (1 << i))
1283 masks[j++] = 1 << i;
1286 build_lut_entry(masks[0], masks[0], lut->m0d);
1287 build_lut_entry(masks[1], masks[1], lut->m1d);
1289 /* Add glue logic */
1290 if (masks[0] || masks[1]) {
1291 /* Transition trigger. */
1292 if (masks[0] & devc->trigger.risingmask)
1293 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1294 if (masks[0] & devc->trigger.fallingmask)
1295 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1296 if (masks[1] & devc->trigger.risingmask)
1297 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1298 if (masks[1] & devc->trigger.fallingmask)
1299 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1301 /* Only value/mask trigger. */
1305 /* Triggertype: event. */
1306 lut->params.selres = 3;
1311 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1313 struct dev_context *devc;
1314 struct clockselect_50 clockselect;
1315 int frac, triggerpin, ret;
1316 uint8_t triggerselect = 0;
1317 struct triggerinout triggerinout_conf;
1318 struct triggerlut lut;
1320 if (sdi->status != SR_ST_ACTIVE)
1321 return SR_ERR_DEV_CLOSED;
1325 if (configure_channels(sdi) != SR_OK) {
1326 sr_err("Failed to configure channels.");
1330 /* If the samplerate has not been set, default to 200 kHz. */
1331 if (devc->cur_firmware == -1) {
1332 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1336 /* Enter trigger programming mode. */
1337 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1339 /* 100 and 200 MHz mode. */
1340 if (devc->cur_samplerate >= SR_MHZ(100)) {
1341 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1343 /* Find which pin to trigger on from mask. */
1344 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1345 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1349 /* Set trigger pin and light LED on trigger. */
1350 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1352 /* Default rising edge. */
1353 if (devc->trigger.fallingmask)
1354 triggerselect |= 1 << 3;
1356 /* All other modes. */
1357 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1358 build_basic_trigger(&lut, devc);
1360 sigma_write_trigger_lut(&lut, devc);
1362 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1365 /* Setup trigger in and out pins to default values. */
1366 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1367 triggerinout_conf.trgout_bytrigger = 1;
1368 triggerinout_conf.trgout_enable = 1;
1370 sigma_write_register(WRITE_TRIGGER_OPTION,
1371 (uint8_t *) &triggerinout_conf,
1372 sizeof(struct triggerinout), devc);
1374 /* Go back to normal mode. */
1375 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1377 /* Set clock select register. */
1378 if (devc->cur_samplerate == SR_MHZ(200))
1379 /* Enable 4 channels. */
1380 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1381 else if (devc->cur_samplerate == SR_MHZ(100))
1382 /* Enable 8 channels. */
1383 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1386 * 50 MHz mode (or fraction thereof). Any fraction down to
1387 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1389 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1391 clockselect.async = 0;
1392 clockselect.fraction = frac;
1393 clockselect.disabled_channels = 0;
1395 sigma_write_register(WRITE_CLOCK_SELECT,
1396 (uint8_t *) &clockselect,
1397 sizeof(clockselect), devc);
1400 /* Setup maximum post trigger time. */
1401 sigma_set_register(WRITE_POST_TRIGGER,
1402 (devc->capture_ratio * 255) / 100, devc);
1404 /* Start acqusition. */
1405 gettimeofday(&devc->start_tv, 0);
1406 sigma_set_register(WRITE_MODE, 0x0d, devc);
1408 devc->cb_data = cb_data;
1410 /* Send header packet to the session bus. */
1411 std_session_send_df_header(cb_data, LOG_PREFIX);
1413 /* Add capture source. */
1414 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1416 devc->state.state = SIGMA_CAPTURE;
1421 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1423 struct dev_context *devc;
1428 devc->state.state = SIGMA_IDLE;
1430 sr_source_remove(0);
1435 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1436 .name = "asix-sigma",
1437 .longname = "ASIX SIGMA/SIGMA2",
1442 .dev_list = dev_list,
1443 .dev_clear = dev_clear,
1444 .config_get = config_get,
1445 .config_set = config_set,
1446 .config_list = config_list,
1447 .dev_open = dev_open,
1448 .dev_close = dev_close,
1449 .dev_acquisition_start = dev_acquisition_start,
1450 .dev_acquisition_stop = dev_acquisition_stop,