2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Return the specified BCD number (max. 8 bits) as integer.
25 return (b & 0x0f) + ((b >> 4) * 10)
27 class Decoder(srd.Decoder):
31 longname = 'Epson RTC-8564 JE/NB'
32 desc = 'Realtime clock module protocol.'
38 {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'TODO.'},
39 {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'TODO.'},
40 {'id': 'int', 'name': 'INT#', 'desc': 'TODO.'},
44 ['text', 'Human-readable text'],
47 def __init__(self, **kwargs):
57 # self.out_proto = self.register(srd.OUTPUT_PYTHON)
58 self.out_ann = self.register(srd.OUTPUT_ANN)
61 self.put(self.ss, self.es, self.out_ann, data)
63 def handle_reg_0x00(self, b): # Control register 1
66 def handle_reg_0x01(self, b): # Control register 2
67 ti_tp = 1 if (b & (1 << 4)) else 0
68 af = 1 if (b & (1 << 3)) else 0
69 tf = 1 if (b & (1 << 2)) else 0
70 aie = 1 if (b & (1 << 1)) else 0
71 tie = 1 if (b & (1 << 0)) else 0
75 s = 'repeated' if ti_tp else 'single-shot'
76 ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
77 'events\n' % (ti_tp, s)
78 s = '' if af else 'no '
79 ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
80 s = '' if tf else 'no '
81 ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
82 s = 'enabled' if aie else 'prohibited'
83 ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
85 s = 'enabled' if tie else 'prohibited'
86 ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
87 'event occurs\n' % (tie, s)
91 def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
92 self.seconds = bcd2int(b & 0x7f)
93 self.putx([0, ['Seconds: %d' % self.seconds]])
94 vl = 1 if (b & (1 << 7)) else 0
95 self.putx([0, ['Voltage low (VL) bit: %d' % vl]])
97 def handle_reg_0x03(self, b): # Minutes
98 self.minutes = bcd2int(b & 0x7f)
99 self.putx([0, ['Minutes: %d' % self.minutes]])
101 def handle_reg_0x04(self, b): # Hours
102 self.hours = bcd2int(b & 0x3f)
103 self.putx([0, ['Hours: %d' % self.hours]])
105 def handle_reg_0x05(self, b): # Days
106 self.days = bcd2int(b & 0x3f)
107 self.putx([0, ['Days: %d' % self.days]])
109 def handle_reg_0x06(self, b): # Day counter
112 def handle_reg_0x07(self, b): # Months / century
113 # TODO: Handle century bit.
114 self.months = bcd2int(b & 0x1f)
115 self.putx([0, ['Months: %d' % self.months]])
117 def handle_reg_0x08(self, b): # Years
118 self.years = bcd2int(b & 0xff)
119 self.putx([0, ['Years: %d' % self.years]])
121 def handle_reg_0x09(self, b): # Alarm, minute
124 def handle_reg_0x0a(self, b): # Alarm, hour
127 def handle_reg_0x0b(self, b): # Alarm, day
130 def handle_reg_0x0c(self, b): # Alarm, weekday
133 def handle_reg_0x0d(self, b): # CLKOUT output
136 def handle_reg_0x0e(self, b): # Timer setting
139 def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
142 def decode(self, ss, es, data):
145 # Store the start/end samples of this I²C packet.
146 self.ss, self.es = ss, es
149 if self.state == 'IDLE':
150 # Wait for an I²C START condition.
153 self.state = 'GET SLAVE ADDR'
154 self.block_start_sample = ss
155 elif self.state == 'GET SLAVE ADDR':
156 # Wait for an address write operation.
157 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
158 if cmd != 'ADDRESS WRITE':
160 self.state = 'GET REG ADDR'
161 elif self.state == 'GET REG ADDR':
162 # Wait for a data write (master selects the slave register).
163 if cmd != 'DATA WRITE':
166 self.state = 'WRITE RTC REGS'
167 elif self.state == 'WRITE RTC REGS':
168 # If we see a Repeated Start here, it's probably an RTC read.
169 if cmd == 'START REPEAT':
170 self.state = 'READ RTC REGS'
172 # Otherwise: Get data bytes until a STOP condition occurs.
173 if cmd == 'DATA WRITE':
174 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
177 # TODO: Check for NACK!
179 # TODO: Handle read/write of only parts of these items.
180 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
181 self.years, self.hours, self.minutes, self.seconds)
182 self.put(self.block_start_sample, es, self.out_ann,
183 [0, ['Written date/time: %s' % d]])
187 elif self.state == 'READ RTC REGS':
188 # Wait for an address read operation.
189 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
190 if cmd == 'ADDRESS READ':
191 self.state = 'READ RTC REGS2'
195 elif self.state == 'READ RTC REGS2':
196 if cmd == 'DATA READ':
197 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
200 # TODO: Check for NACK!
202 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
203 self.years, self.hours, self.minutes, self.seconds)
204 self.put(self.block_start_sample, es, self.out_ann,
205 [0, ['Read date/time: %s' % d]])
210 raise Exception('Invalid state: %s' % self.state)