2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Return the specified BCD number (max. 8 bits) as integer.
25 return (b & 0x0f) + ((b >> 4) * 10)
27 class Decoder(srd.Decoder):
31 longname = 'Epson RTC-8564 JE/NB'
32 desc = 'Realtime clock module protocol.'
38 {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
39 {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
40 {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
44 ['reg-0x00', 'Register 0x00'],
45 ['reg-0x01', 'Register 0x01'],
46 ['reg-0x02', 'Register 0x02'],
47 ['reg-0x03', 'Register 0x03'],
48 ['reg-0x04', 'Register 0x04'],
49 ['reg-0x05', 'Register 0x05'],
50 ['reg-0x06', 'Register 0x06'],
51 ['reg-0x07', 'Register 0x07'],
52 ['reg-0x08', 'Register 0x08'],
53 ['read', 'Read date/time'],
54 ['write', 'Write date/time'],
58 ('bits', 'Bits', (11,)),
59 ('regs', 'Registers', tuple(range(0, 8 + 1))),
60 ('date-time', 'Date/time', (9, 10)),
63 def __init__(self, **kwargs):
73 # self.out_python = self.register(srd.OUTPUT_PYTHON)
74 self.out_ann = self.register(srd.OUTPUT_ANN)
77 self.put(self.ss, self.es, self.out_ann, data)
79 def handle_reg_0x00(self, b): # Control register 1
82 def handle_reg_0x01(self, b): # Control register 2
83 ti_tp = 1 if (b & (1 << 4)) else 0
84 af = 1 if (b & (1 << 3)) else 0
85 tf = 1 if (b & (1 << 2)) else 0
86 aie = 1 if (b & (1 << 1)) else 0
87 tie = 1 if (b & (1 << 0)) else 0
91 s = 'repeated' if ti_tp else 'single-shot'
92 ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
93 'events\n' % (ti_tp, s)
94 s = '' if af else 'no '
95 ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
96 s = '' if tf else 'no '
97 ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
98 s = 'enabled' if aie else 'prohibited'
99 ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
100 'occurs\n' % (aie, s)
101 s = 'enabled' if tie else 'prohibited'
102 ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
103 'event occurs\n' % (tie, s)
105 self.putx([1, [ann]])
107 def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
108 self.seconds = bcd2int(b & 0x7f)
109 self.putx([2, ['Seconds: %d' % self.seconds]])
110 vl = 1 if (b & (1 << 7)) else 0
111 self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
113 def handle_reg_0x03(self, b): # Minutes
114 self.minutes = bcd2int(b & 0x7f)
115 self.putx([3, ['Minutes: %d' % self.minutes]])
117 def handle_reg_0x04(self, b): # Hours
118 self.hours = bcd2int(b & 0x3f)
119 self.putx([4, ['Hours: %d' % self.hours]])
121 def handle_reg_0x05(self, b): # Days
122 self.days = bcd2int(b & 0x3f)
123 self.putx([5, ['Days: %d' % self.days]])
125 def handle_reg_0x06(self, b): # Day counter
128 def handle_reg_0x07(self, b): # Months / century
129 # TODO: Handle century bit.
130 self.months = bcd2int(b & 0x1f)
131 self.putx([7, ['Months: %d' % self.months]])
133 def handle_reg_0x08(self, b): # Years
134 self.years = bcd2int(b & 0xff)
135 self.putx([8, ['Years: %d' % self.years]])
137 def handle_reg_0x09(self, b): # Alarm, minute
140 def handle_reg_0x0a(self, b): # Alarm, hour
143 def handle_reg_0x0b(self, b): # Alarm, day
146 def handle_reg_0x0c(self, b): # Alarm, weekday
149 def handle_reg_0x0d(self, b): # CLKOUT output
152 def handle_reg_0x0e(self, b): # Timer setting
155 def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
158 def decode(self, ss, es, data):
161 # Store the start/end samples of this I²C packet.
162 self.ss, self.es = ss, es
165 if self.state == 'IDLE':
166 # Wait for an I²C START condition.
169 self.state = 'GET SLAVE ADDR'
170 self.block_start_sample = ss
171 elif self.state == 'GET SLAVE ADDR':
172 # Wait for an address write operation.
173 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
174 if cmd != 'ADDRESS WRITE':
176 self.state = 'GET REG ADDR'
177 elif self.state == 'GET REG ADDR':
178 # Wait for a data write (master selects the slave register).
179 if cmd != 'DATA WRITE':
182 self.state = 'WRITE RTC REGS'
183 elif self.state == 'WRITE RTC REGS':
184 # If we see a Repeated Start here, it's probably an RTC read.
185 if cmd == 'START REPEAT':
186 self.state = 'READ RTC REGS'
188 # Otherwise: Get data bytes until a STOP condition occurs.
189 if cmd == 'DATA WRITE':
190 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
193 # TODO: Check for NACK!
195 # TODO: Handle read/write of only parts of these items.
196 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
197 self.years, self.hours, self.minutes, self.seconds)
198 self.put(self.block_start_sample, es, self.out_ann,
199 [9, ['Write date/time: %s' % d]])
203 elif self.state == 'READ RTC REGS':
204 # Wait for an address read operation.
205 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
206 if cmd == 'ADDRESS READ':
207 self.state = 'READ RTC REGS2'
211 elif self.state == 'READ RTC REGS2':
212 if cmd == 'DATA READ':
213 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
216 # TODO: Check for NACK!
218 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
219 self.years, self.hours, self.minutes, self.seconds)
220 self.put(self.block_start_sample, es, self.out_ann,
221 [10, ['Read date/time: %s' % d]])
226 raise Exception('Invalid state: %s' % self.state)