2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
24 # START field (indicates start or stop of a transaction)
26 0b0000: 'Start of cycle for a target',
28 0b0010: 'Grant for bus master 0',
29 0b0011: 'Grant for bus master 1',
39 0b1101: 'Start of cycle for a Firmware Memory Read cycle',
40 0b1110: 'Start of cycle for a Firmware Memory Write cycle',
41 0b1111: 'Stop/abort (end of a cycle for a target)',
43 # Cycle type / direction field
44 # Bit 0 (LAD[0]) is unused, should always be 0.
45 # Neither host nor peripheral are allowed to drive 0b11x0.
49 0b0100: 'Memory read',
50 0b0110: 'Memory write',
53 0b1100: 'Reserved / not allowed',
54 0b1110: 'Reserved / not allowed',
56 # SIZE field (determines how many bytes are to be transferred)
57 # Bits[3:2] are reserved, must be driven to 0b00.
58 # Neither host nor peripheral are allowed to drive 0b0010.
60 0b0000: '8 bits (1 byte)',
61 0b0001: '16 bits (2 bytes)',
62 0b0010: 'Reserved / not allowed',
63 0b0011: '32 bits (4 bytes)',
65 # CHANNEL field (bits[2:0] contain the DMA channel number)
76 # SYNC field (used to add wait states)
87 0b1001: 'Ready more (DMA only)',
97 class Decoder(srd.Decoder):
101 longname = 'Low Pin Count'
102 desc = 'Protocol for low-bandwidth devices on PC mainboards.'
108 {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
109 {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'},
110 {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'},
111 {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'},
112 {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'},
113 {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'},
115 optional_channels = (
116 {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
117 {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'},
118 {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'},
119 {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'},
120 {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'},
121 {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'},
122 {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'},
125 ('warning', 'Warning'),
127 ('cycle-type', 'Cycle-type/direction'),
129 ('tar1', 'Turn-around cycle 1'),
132 ('tar2', 'Turn-around cycle 2'),
135 ('data-vals', 'Data', (1, 2, 3, 4, 5, 6, 7)),
136 ('warnings', 'Warnings', (0,)),
153 self.ss_block = self.es_block = None
156 self.out_ann = self.register(srd.OUTPUT_ANN)
158 def putb(self, data):
159 self.put(self.ss_block, self.es_block, self.out_ann, data)
161 def handle_get_start(self, lad, lad_bits, lframe):
162 # LAD[3:0]: START field (1 clock cycle).
164 # The last value of LAD[3:0] before LFRAME# gets de-asserted is what
165 # the peripherals must use. However, the host can keep LFRAME# asserted
166 # multiple clocks, and we output all START fields that occur, even
167 # though the peripherals are supposed to ignore all but the last one.
168 self.es_block = self.samplenum
169 self.putb([1, [fields['START'][lad], 'START', 'St', 'S']])
170 self.ss_block = self.samplenum
172 # Output a warning if LAD[3:0] changes while LFRAME# is low.
174 if (self.lad != -1 and self.lad != lad):
175 self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']])
177 # LFRAME# is asserted (low). Wait until it gets de-asserted again
178 # (the host is allowed to keep it asserted multiple clocks).
182 self.start_field = self.lad
183 self.state = 'GET CT/DR'
185 def handle_get_ct_dr(self, lad, lad_bits):
186 # LAD[3:0]: Cycle type / direction field (1 clock cycle).
188 self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown')
190 # TODO: Warning/error on invalid cycle types.
191 if 'Reserved' in self.cycle_type:
192 self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
194 self.es_block = self.samplenum
195 self.putb([2, ['Cycle type: %s' % self.cycle_type]])
196 self.ss_block = self.samplenum
198 self.state = 'GET ADDR'
202 def handle_get_addr(self, lad, lad_bits):
203 # LAD[3:0]: ADDR field (4/8/0 clock cycles).
205 # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
206 # DMA cycles: no ADDR clocks at all.
207 if self.cycle_type in ('I/O read', 'I/O write'):
208 addr_nibbles = 4 # Address is 16bits.
209 elif self.cycle_type in ('Memory read', 'Memory write'):
210 addr_nibbles = 8 # Address is 32bits.
212 addr_nibbles = 0 # TODO: How to handle later on?
214 # Addresses are driven MSN-first.
215 offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
216 self.addr |= (lad << offset)
218 # Continue if we haven't seen all ADDR cycles, yet.
219 if (self.cur_nibble < addr_nibbles - 1):
223 self.es_block = self.samplenum
224 s = 'Address: 0x%%0%dx' % addr_nibbles
225 self.putb([3, [s % self.addr]])
226 self.ss_block = self.samplenum
228 self.state = 'GET TAR'
231 def handle_get_tar(self, lad, lad_bits):
232 # LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
234 self.es_block = self.samplenum
235 self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
236 self.ss_block = self.samplenum
238 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
239 # either the host or peripheral. On the second clock cycle,
240 # the host or peripheral tri-states LAD[3:0], but its value
241 # should still be 1111, due to pull-ups on the LAD lines.
242 if lad_bits != '1111':
243 self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \
244 (self.tarcount, lad_bits)]])
246 if (self.tarcount != 1):
251 self.state = 'GET SYNC'
253 def handle_get_sync(self, lad, lad_bits):
254 # LAD[3:0]: SYNC field (1-n clock cycles).
256 self.sync_val = lad_bits
257 self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown')
259 # TODO: Warnings if reserved value are seen?
260 if 'Reserved' in self.cycle_type:
261 self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
262 (self.synccount, self.sync_val)]])
264 self.es_block = self.samplenum
265 self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]])
266 self.ss_block = self.samplenum
271 self.state = 'GET DATA'
273 def handle_get_data(self, lad, lad_bits):
274 # LAD[3:0]: DATA field (2 clock cycles).
276 # Data is driven LSN-first.
277 if (self.cycle_count == 0):
279 elif (self.cycle_count == 1):
280 self.databyte |= (lad << 4)
282 raise Exception('Invalid cycle_count: %d' % self.cycle_count)
284 if (self.cycle_count != 1):
285 self.cycle_count += 1
288 self.es_block = self.samplenum
289 self.putb([6, ['DATA: 0x%02x' % self.databyte]])
290 self.ss_block = self.samplenum
293 self.state = 'GET TAR2'
295 def handle_get_tar2(self, lad, lad_bits):
296 # LAD[3:0]: Second TAR field (2 clock cycles).
298 self.es_block = self.samplenum
299 self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
300 self.ss_block = self.samplenum
302 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
303 # either the host or peripheral. On the second clock cycle,
304 # the host or peripheral tri-states LAD[3:0], but its value
305 # should still be 1111, due to pull-ups on the LAD lines.
306 if lad_bits != '1111':
307 self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)'
308 % (self.tarcount, lad_bits)]])
310 if (self.tarcount != 1):
318 conditions = [{i: 'e'} for i in range(6)]
320 pins = self.wait(conditions)
322 # Store current pin values for the next round.
325 # Get individual pin values into local variables.
326 (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6]
327 (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:]
329 # Only look at the signals upon rising LCLK edges. The LPC clock
330 # is the same as the PCI clock (which is sampled at rising edges).
331 if not (self.oldlclk == 0 and lclk == 1):
335 # Store LAD[3:0] bit values (one nibble) in local variables.
336 # Most (but not all) states need this.
337 if self.state != 'IDLE':
338 lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
339 lad_bits = '{:04b}'.format(lad)
340 # self.putb([0, ['LAD: %s' % lad_bits]])
342 # TODO: Only memory read/write is currently supported/tested.
345 if self.state == 'IDLE':
346 # A valid LPC cycle starts with LFRAME# being asserted (low).
349 self.ss_block = self.samplenum
350 self.state = 'GET START'
352 elif self.state == 'GET START':
353 self.handle_get_start(lad, lad_bits, lframe)
354 elif self.state == 'GET CT/DR':
355 self.handle_get_ct_dr(lad, lad_bits)
356 elif self.state == 'GET ADDR':
357 self.handle_get_addr(lad, lad_bits)
358 elif self.state == 'GET TAR':
359 self.handle_get_tar(lad, lad_bits)
360 elif self.state == 'GET SYNC':
361 self.handle_get_sync(lad, lad_bits)
362 elif self.state == 'GET DATA':
363 self.handle_get_data(lad, lad_bits)
364 elif self.state == 'GET TAR2':
365 self.handle_get_tar2(lad, lad_bits)