2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # I2C protocol decoder
26 # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
27 # bus using two signals (SCL = serial clock line, SDA = serial data line).
29 # There can be many devices on the same bus. Each device can potentially be
30 # master or slave (and that can change during runtime). Both slave and master
31 # can potentially play the transmitter or receiver role (this can also
34 # Possible maximum data rates:
35 # - Standard mode: 100 kbit/s
36 # - Fast mode: 400 kbit/s
37 # - Fast-mode Plus: 1 Mbit/s
38 # - High-speed mode: 3.4 Mbit/s
40 # START condition (S): SDA = falling, SCL = high
41 # Repeated START condition (Sr): same as S
42 # Data bit sampling: SCL = rising
43 # STOP condition (P): SDA = rising, SCL = high
45 # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
46 # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
47 # that indicates an ACK, if it's high that indicates a NACK.
49 # After the first START condition, a master sends the device address of the
50 # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
51 # After those 7 bits, a data direction bit is sent. If the bit is low that
52 # indicates a WRITE operation, if it's high that indicates a READ operation.
54 # Later an optional 10bit slave addressing scheme was added.
57 # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
58 # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
59 # http://en.wikipedia.org/wiki/I2C
62 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
63 # TODO: Handle clock stretching.
64 # TODO: Handle combined messages / repeated START.
65 # TODO: Implement support for 7bit and 10bit slave addresses.
66 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
67 # TODO: Implement support for detecting various bus errors.
68 # TODO: I2C address of slaves.
69 # TODO: Handle multiple different I2C devices on same bus
70 # -> we need to decode multiple protocols at the same time.
73 # I2C protocol output format:
75 # The protocol output consists of a (Python) list of I2C "packets", each of
76 # which is of the form
78 # [<i2c_command>, <data>, <ack_bit>]
80 # <i2c_command> is one of:
81 # - 'START' (START condition)
82 # - 'START_REPEAT' (Repeated START)
83 # - 'ADDRESS_READ' (Slave address, read)
84 # - 'ADDRESS_WRITE' (Slave address, write)
85 # - 'DATA_READ' (Data, read)
86 # - 'DATA_WRITE' (Data, write)
87 # - 'STOP' (STOP condition)
89 # <data> is the data or address byte associated with the ADDRESS_* and DATA_*
90 # command. For START, START_REPEAT and STOP, this is None.
92 # <ack_bit> is either 'ACK' or 'NACK', but may also be None.
95 import sigrokdecode as srd
97 # Annotation feed formats
102 # Values are verbose and short annotation, respectively.
104 'START': ['START', 'S'],
105 'START_REPEAT': ['START REPEAT', 'Sr'],
106 'STOP': ['STOP', 'P'],
108 'NACK': ['NACK', 'N'],
109 'ADDRESS_READ': ['ADDRESS READ', 'AR'],
110 'ADDRESS_WRITE': ['ADDRESS WRITE', 'AW'],
111 'DATA_READ': ['DATA READ', 'DR'],
112 'DATA_WRITE': ['DATA WRITE', 'DW'],
120 class Decoder(srd.Decoder):
123 longname = 'Inter-Integrated Circuit (I2C) bus'
124 desc = 'I2C is a two-wire, multi-master, serial bus.'
126 author = 'Uwe Hermann'
127 email = 'uwe@hermann-uwe.de'
132 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
133 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
136 'address-space': ['Address space (in bits)', 7],
140 ['7-bit shifted hex',
141 'Read/write bit shifted out from the 8-bit I2C slave address'],
143 ['7-bit shifted hex (short)',
144 'Read/write bit shifted out from the 8-bit I2C slave address'],
146 ['Raw hex', 'Unaltered raw data'],
149 def __init__(self, **kwargs):
154 self.startsample = -1
155 self.is_repeat_start = 0
156 self.state = FIND_START
160 def start(self, metadata):
161 self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
162 self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
167 def is_start_condition(self, scl, sda):
168 # START condition (S): SDA = falling, SCL = high
169 if (self.oldsda == 1 and sda == 0) and scl == 1:
173 def is_data_bit(self, scl, sda):
174 # Data sampling of receiver: SCL = rising
175 if self.oldscl == 0 and scl == 1:
179 def is_stop_condition(self, scl, sda):
180 # STOP condition (P): SDA = rising, SCL = high
181 if (self.oldsda == 0 and sda == 1) and scl == 1:
185 def found_start(self, scl, sda):
186 if self.is_repeat_start == 1:
191 self.put(self.out_proto, [cmd, None, None])
192 self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
193 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
195 self.state = FIND_ADDRESS
196 self.bitcount = self.databyte = 0
197 self.is_repeat_start = 1
200 def found_address_or_data(self, scl, sda):
201 # Gather 8 bits of data plus the ACK/NACK bit.
203 if self.startsample == -1:
204 # TODO: Should be samplenum, as received from the feed.
205 self.startsample = self.samplecnt
208 # Address and data are transmitted MSB-first.
212 # Return if we haven't collected all 8 + 1 bits, yet.
213 if self.bitcount != 9:
216 # Send raw output annotation before we start shifting out
217 # read/write and ack/nack bits.
218 self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
220 # We received 8 address/data bits and the ACK/NACK bit.
221 self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
223 if self.state == FIND_ADDRESS:
224 # The READ/WRITE bit is only in address bytes, not data bytes.
225 if self.databyte & 1:
229 d = self.databyte >> 1
230 elif self.state == FIND_DATA:
236 # Last bit that came in was the ACK/NACK bit (1 = NACK).
242 if self.state == FIND_ADDRESS and self.wr == 1:
243 cmd = 'ADDRESS_WRITE'
244 elif self.state == FIND_ADDRESS and self.wr == 0:
246 elif self.state == FIND_DATA and self.wr == 1:
248 elif self.state == FIND_DATA and self.wr == 0:
251 self.put(self.out_proto, [cmd, d, ack_bit])
252 self.put(self.out_ann, [ANN_SHIFTED, [
253 '%s' % protocol[cmd][0],
255 '%s' % protocol[ack_bit][0]]
257 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [
258 '%s' % protocol[cmd][1],
260 '%s' % protocol[ack_bit][1]]
263 self.bitcount = self.databyte = 0
264 self.startsample = -1
266 if self.state == FIND_ADDRESS:
267 self.state = FIND_DATA
268 elif self.state == FIND_DATA:
269 # There could be multiple data bytes in a row.
270 # So, either find a STOP condition or another data byte next.
273 def found_stop(self, scl, sda):
274 self.put(self.out_proto, ['STOP', None, None])
275 self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
276 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
278 self.state = FIND_START
279 self.is_repeat_start = 0
282 def put(self, output_id, data):
283 # Inject sample range into the call up to sigrok.
284 # TODO: 0-0 sample range for now.
285 super(Decoder, self).put(0, 0, output_id, data)
287 def decode(self, timeoffset, duration, data):
288 for samplenum, (scl, sda) in data:
291 # First sample: Save SCL/SDA value.
292 if self.oldscl == None:
297 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
300 if self.state == FIND_START:
301 if self.is_start_condition(scl, sda):
302 self.found_start(scl, sda)
303 elif self.state == FIND_ADDRESS:
304 if self.is_data_bit(scl, sda):
305 self.found_address_or_data(scl, sda)
306 elif self.state == FIND_DATA:
307 if self.is_data_bit(scl, sda):
308 self.found_address_or_data(scl, sda)
309 elif self.is_start_condition(scl, sda):
310 self.found_start(scl, sda)
311 elif self.is_stop_condition(scl, sda):
312 self.found_stop(scl, sda)
317 # Save current SDA/SCL values for the next round.