2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # I2C protocol decoder
26 # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
27 # bus using two signals (SCL = serial clock line, SDA = serial data line).
29 # There can be many devices on the same bus. Each device can potentially be
30 # master or slave (and that can change during runtime). Both slave and master
31 # can potentially play the transmitter or receiver role (this can also
34 # Possible maximum data rates:
35 # - Standard mode: 100 kbit/s
36 # - Fast mode: 400 kbit/s
37 # - Fast-mode Plus: 1 Mbit/s
38 # - High-speed mode: 3.4 Mbit/s
40 # START condition (S): SDA = falling, SCL = high
41 # Repeated START condition (Sr): same as S
42 # Data bit sampling: SCL = rising
43 # STOP condition (P): SDA = rising, SCL = high
45 # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
46 # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
47 # that indicates an ACK, if it's high that indicates a NACK.
49 # After the first START condition, a master sends the device address of the
50 # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
51 # After those 7 bits, a data direction bit is sent. If the bit is low that
52 # indicates a WRITE operation, if it's high that indicates a READ operation.
54 # Later an optional 10bit slave addressing scheme was added.
57 # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
58 # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
59 # http://en.wikipedia.org/wiki/I2C
62 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
63 # TODO: Handle clock stretching.
64 # TODO: Handle combined messages / repeated START.
65 # TODO: Implement support for 7bit and 10bit slave addresses.
66 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
67 # TODO: Implement support for detecting various bus errors.
68 # TODO: I2C address of slaves.
69 # TODO: Handle multiple different I2C devices on same bus
70 # -> we need to decode multiple protocols at the same time.
73 Protocol output format:
76 [<i2c_command>, <data>, <ack_bit>]
78 <i2c_command> is one of:
79 - 'START' (START condition)
80 - 'START REPEAT' (Repeated START)
81 - 'ADDRESS READ' (Address, read)
82 - 'ADDRESS WRITE' (Address, write)
83 - 'DATA READ' (Data, read)
84 - 'DATA WRITE' (Data, write)
85 - 'STOP' (STOP condition)
87 <data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
88 command. For 'START', 'START REPEAT' and 'STOP', this is None.
90 <ack_bit> is either 'ACK' or 'NACK', but may also be None.
93 import sigrokdecode as srd
95 # Annotation feed formats
100 # Values are verbose and short annotation, respectively.
102 'START': ['START', 'S'],
103 'START REPEAT': ['START REPEAT', 'Sr'],
104 'STOP': ['STOP', 'P'],
106 'NACK': ['NACK', 'N'],
107 'ADDRESS READ': ['ADDRESS READ', 'AR'],
108 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'],
109 'DATA READ': ['DATA READ', 'DR'],
110 'DATA WRITE': ['DATA WRITE', 'DW'],
118 class Decoder(srd.Decoder):
122 longname = 'Inter-Integrated Circuit'
123 desc = 'I2C is a two-wire, multi-master, serial bus.'
129 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
130 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
134 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
138 ['7-bit shifted hex',
139 'Read/write bit shifted out from the 8-bit I2C slave address'],
141 ['7-bit shifted hex (short)',
142 'Read/write bit shifted out from the 8-bit I2C slave address'],
144 ['Raw hex', 'Unaltered raw data'],
147 def __init__(self, **kwargs):
148 self.startsample = -1
149 self.samplenum = None
153 self.is_repeat_start = 0
154 self.state = FIND_START
158 def start(self, metadata):
159 self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
160 self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
165 def is_start_condition(self, scl, sda):
166 # START condition (S): SDA = falling, SCL = high
167 if (self.oldsda == 1 and sda == 0) and scl == 1:
171 def is_data_bit(self, scl, sda):
172 # Data sampling of receiver: SCL = rising
173 if self.oldscl == 0 and scl == 1:
177 def is_stop_condition(self, scl, sda):
178 # STOP condition (P): SDA = rising, SCL = high
179 if (self.oldsda == 0 and sda == 1) and scl == 1:
183 def found_start(self, scl, sda):
184 self.startsample = self.samplenum
186 cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
187 self.put(self.out_proto, [cmd, None, None])
188 self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
189 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
191 self.state = FIND_ADDRESS
192 self.bitcount = self.databyte = 0
193 self.is_repeat_start = 1
196 # Gather 8 bits of data plus the ACK/NACK bit.
197 def found_address_or_data(self, scl, sda):
198 # Address and data are transmitted MSB-first.
202 if self.bitcount == 0:
203 self.startsample = self.samplenum
205 # Return if we haven't collected all 8 + 1 bits, yet.
207 if self.bitcount != 9:
210 # Send raw output annotation before we start shifting out
211 # read/write and ack/nack bits.
212 self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
214 # We received 8 address/data bits and the ACK/NACK bit.
215 self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
217 if self.state == FIND_ADDRESS:
218 # The READ/WRITE bit is only in address bytes, not data bytes.
219 self.wr = 0 if (self.databyte & 1) else 1
220 d = self.databyte >> 1
221 elif self.state == FIND_DATA:
227 # Last bit that came in was the ACK/NACK bit (1 = NACK).
228 ack_bit = 'NACK' if (sda == 1) else 'ACK'
230 if self.state == FIND_ADDRESS and self.wr == 1:
231 cmd = 'ADDRESS WRITE'
232 elif self.state == FIND_ADDRESS and self.wr == 0:
234 elif self.state == FIND_DATA and self.wr == 1:
236 elif self.state == FIND_DATA and self.wr == 0:
239 self.put(self.out_proto, [cmd, d, ack_bit])
240 self.put(self.out_ann, [ANN_SHIFTED,
241 [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]])
242 self.put(self.out_ann, [ANN_SHIFTED_SHORT,
243 [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]])
245 self.bitcount = self.databyte = 0
246 self.startsample = -1
248 if self.state == FIND_ADDRESS:
249 self.state = FIND_DATA
250 elif self.state == FIND_DATA:
251 # There could be multiple data bytes in a row.
252 # So, either find a STOP condition or another data byte next.
255 def found_stop(self, scl, sda):
256 self.startsample = self.samplenum
258 self.put(self.out_proto, ['STOP', None, None])
259 self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
260 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
262 self.state = FIND_START
263 self.is_repeat_start = 0
266 def put(self, output_id, data):
267 # Inject sample range into the call up to sigrok.
268 super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
270 def decode(self, ss, es, data):
271 for samplenum, (scl, sda) in data:
272 self.samplenum = samplenum
274 # First sample: Save SCL/SDA value.
275 if self.oldscl == None:
280 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
283 if self.state == FIND_START:
284 if self.is_start_condition(scl, sda):
285 self.found_start(scl, sda)
286 elif self.state == FIND_ADDRESS:
287 if self.is_data_bit(scl, sda):
288 self.found_address_or_data(scl, sda)
289 elif self.state == FIND_DATA:
290 if self.is_data_bit(scl, sda):
291 self.found_address_or_data(scl, sda)
292 elif self.is_start_condition(scl, sda):
293 self.found_start(scl, sda)
294 elif self.is_stop_condition(scl, sda):
295 self.found_stop(scl, sda)
297 raise Exception('Invalid state %d' % self.STATE)
299 # Save current SDA/SCL values for the next round.