2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 * Channels are labelled 1-16, see this vendor's image of the cable:
28 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg (TI/TO are
29 * additional trigger in/out signals).
31 static const char *channel_names[] = {
32 "1", "2", "3", "4", "5", "6", "7", "8",
33 "9", "10", "11", "12", "13", "14", "15", "16",
36 static const uint32_t scanopts[] = {
41 static const uint32_t drvopts[] = {
42 SR_CONF_LOGIC_ANALYZER,
45 static const uint32_t devopts[] = {
46 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
47 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
48 SR_CONF_CONN | SR_CONF_GET,
49 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
50 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
51 SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
52 SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
53 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
54 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
55 /* Consider SR_CONF_TRIGGER_PATTERN (SR_T_STRING, GET/SET) support. */
58 static const char *ext_clock_edges[] = {
59 [SIGMA_CLOCK_EDGE_RISING] = "rising",
60 [SIGMA_CLOCK_EDGE_FALLING] = "falling",
61 [SIGMA_CLOCK_EDGE_EITHER] = "either",
64 static const int32_t trigger_matches[] = {
71 static void clear_helper(struct dev_context *devc)
73 (void)sigma_force_close(devc);
76 static int dev_clear(const struct sr_dev_driver *di)
78 return std_dev_clear_with_callback(di,
79 (std_dev_clear_callback)clear_helper);
82 static gboolean bus_addr_in_devices(int bus, int addr, GSList *devs)
84 struct sr_usb_dev_inst *usb;
86 for (/* EMPTY */; devs; devs = devs->next) {
88 if (usb->bus == bus && usb->address == addr)
95 static gboolean known_vid_pid(const struct libusb_device_descriptor *des)
97 gboolean is_sigma, is_omega;
99 if (des->idVendor != USB_VENDOR_ASIX)
101 is_sigma = des->idProduct == USB_PRODUCT_SIGMA;
102 is_omega = des->idProduct == USB_PRODUCT_OMEGA;
103 if (!is_sigma && !is_omega)
108 static GSList *scan(struct sr_dev_driver *di, GSList *options)
110 struct drv_context *drvc;
111 libusb_context *usbctx;
113 const char *probe_names;
114 GSList *l, *conn_devices;
115 struct sr_config *src;
117 libusb_device **devlist, *devitem;
119 struct libusb_device_descriptor des;
120 struct libusb_device_handle *hdl;
125 unsigned long serno_num, serno_pre;
126 enum asix_device_type dev_type;
127 const char *dev_text;
128 struct sr_dev_inst *sdi;
129 struct dev_context *devc;
130 size_t devidx, chidx;
134 usbctx = drvc->sr_ctx->libusb_ctx;
136 /* Find all devices which match an (optional) conn= spec. */
139 for (l = options; l; l = l->next) {
143 conn = g_variant_get_string(src->data, NULL);
145 case SR_CONF_PROBE_NAMES:
146 probe_names = g_variant_get_string(src->data, NULL);
152 conn_devices = sr_usb_find(usbctx, conn);
153 if (conn && !conn_devices)
156 /* Find all ASIX logic analyzers (which match the connection spec). */
158 libusb_get_device_list(usbctx, &devlist);
159 for (devidx = 0; devlist[devidx]; devidx++) {
160 devitem = devlist[devidx];
162 /* Check for connection match if a user spec was given. */
163 bus = libusb_get_bus_number(devitem);
164 addr = libusb_get_device_address(devitem);
165 if (conn && !bus_addr_in_devices(bus, addr, conn_devices))
167 snprintf(conn_id, sizeof(conn_id), "%d.%d", bus, addr);
170 * Check for known VID:PID pairs. Get the serial number,
171 * to then derive the device type from it.
173 libusb_get_device_descriptor(devitem, &des);
174 if (!known_vid_pid(&des))
176 if (!des.iSerialNumber) {
177 sr_warn("Cannot get serial number (index 0).");
180 ret = libusb_open(devitem, &hdl);
182 sr_warn("Cannot open USB device %04x.%04x: %s.",
183 des.idVendor, des.idProduct,
184 libusb_error_name(ret));
187 ret = libusb_get_string_descriptor_ascii(hdl,
189 (unsigned char *)serno_txt, sizeof(serno_txt));
191 sr_warn("Cannot get serial number (%s).",
192 libusb_error_name(ret));
199 * All ASIX logic analyzers have a serial number, which
200 * reads as a hex number, and tells the device type.
202 ret = sr_atoul_base(serno_txt, &serno_num, &end, 16);
203 if (ret != SR_OK || !end || *end) {
204 sr_warn("Cannot interpret serial number %s.", serno_txt);
207 dev_type = ASIX_TYPE_NONE;
209 serno_pre = serno_num >> 16;
212 dev_type = ASIX_TYPE_SIGMA;
214 sr_info("Found SIGMA, serno %s.", serno_txt);
217 dev_type = ASIX_TYPE_SIGMA;
219 sr_info("Found SIGMA2, serno %s.", serno_txt);
222 dev_type = ASIX_TYPE_OMEGA;
224 sr_info("Found OMEGA, serno %s.", serno_txt);
225 if (!ASIX_WITH_OMEGA) {
226 sr_warn("OMEGA support is not implemented yet.");
231 sr_warn("Unknown serno %s, skipping.", serno_txt);
235 /* Create a device instance, add it to the result set. */
237 sdi = g_malloc0(sizeof(*sdi));
238 devices = g_slist_append(devices, sdi);
239 sdi->status = SR_ST_INITIALIZING;
240 sdi->vendor = g_strdup("ASIX");
241 sdi->model = g_strdup(dev_text);
242 sdi->serial_num = g_strdup(serno_txt);
243 sdi->connection_id = g_strdup(conn_id);
244 devc = g_malloc0(sizeof(*devc));
246 devc->channel_names = sr_parse_probe_names(probe_names,
247 channel_names, ARRAY_SIZE(channel_names),
248 ARRAY_SIZE(channel_names), &count);
249 for (chidx = 0; chidx < count; chidx++)
250 sr_channel_new(sdi, chidx, SR_CHANNEL_LOGIC,
251 TRUE, devc->channel_names[chidx]);
252 devc->id.vid = des.idVendor;
253 devc->id.pid = des.idProduct;
254 devc->id.serno = serno_num;
255 devc->id.prefix = serno_pre;
256 devc->id.type = dev_type;
257 sr_sw_limits_init(&devc->limit.config);
258 devc->capture_ratio = 50;
259 devc->use_triggers = FALSE;
261 /* Get current hardware configuration (or use defaults). */
262 (void)sigma_fetch_hw_config(sdi);
264 libusb_free_device_list(devlist, 1);
265 g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
267 return std_scan_complete(di, devices);
270 static int dev_open(struct sr_dev_inst *sdi)
272 struct dev_context *devc;
276 if (devc->id.type == ASIX_TYPE_OMEGA && !ASIX_WITH_OMEGA) {
277 sr_err("OMEGA support is not implemented yet.");
281 return sigma_force_open(sdi);
284 static int dev_close(struct sr_dev_inst *sdi)
286 struct dev_context *devc;
290 return sigma_force_close(devc);
293 static int config_get(uint32_t key, GVariant **data,
294 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
296 struct dev_context *devc;
297 const char *clock_text;
307 *data = g_variant_new_string(sdi->connection_id);
309 case SR_CONF_SAMPLERATE:
310 *data = g_variant_new_uint64(devc->clock.samplerate);
312 case SR_CONF_EXTERNAL_CLOCK:
313 *data = g_variant_new_boolean(devc->clock.use_ext_clock);
315 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
316 clock_text = devc->channel_names[devc->clock.clock_pin];
317 *data = g_variant_new_string(clock_text);
319 case SR_CONF_CLOCK_EDGE:
320 clock_text = ext_clock_edges[devc->clock.clock_edge];
321 *data = g_variant_new_string(clock_text);
323 case SR_CONF_LIMIT_MSEC:
324 case SR_CONF_LIMIT_SAMPLES:
325 return sr_sw_limits_config_get(&devc->limit.config, key, data);
326 case SR_CONF_CAPTURE_RATIO:
327 *data = g_variant_new_uint64(devc->capture_ratio);
336 static int config_set(uint32_t key, GVariant *data,
337 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
339 struct dev_context *devc;
341 uint64_t want_rate, have_rate;
351 case SR_CONF_SAMPLERATE:
352 want_rate = g_variant_get_uint64(data);
353 ret = sigma_normalize_samplerate(want_rate, &have_rate);
356 if (have_rate != want_rate) {
357 char *text_want, *text_have;
358 text_want = sr_samplerate_string(want_rate);
359 text_have = sr_samplerate_string(have_rate);
360 sr_info("Adjusted samplerate %s to %s.",
361 text_want, text_have);
365 devc->clock.samplerate = have_rate;
367 case SR_CONF_EXTERNAL_CLOCK:
368 devc->clock.use_ext_clock = g_variant_get_boolean(data);
370 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
371 names = (const char **)devc->channel_names;
372 count = g_strv_length(devc->channel_names);
373 idx = std_str_idx(data, names, count);
376 devc->clock.clock_pin = idx;
378 case SR_CONF_CLOCK_EDGE:
379 idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges));
382 devc->clock.clock_edge = idx;
384 case SR_CONF_LIMIT_MSEC:
385 case SR_CONF_LIMIT_SAMPLES:
386 return sr_sw_limits_config_set(&devc->limit.config, key, data);
387 case SR_CONF_CAPTURE_RATIO:
388 devc->capture_ratio = g_variant_get_uint64(data);
397 static int config_list(uint32_t key, GVariant **data,
398 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
400 struct dev_context *devc;
404 devc = sdi ? sdi->priv : NULL;
406 case SR_CONF_SCAN_OPTIONS:
407 case SR_CONF_DEVICE_OPTIONS:
410 return STD_CONFIG_LIST(key, data, sdi, cg,
411 scanopts, drvopts, devopts);
412 case SR_CONF_SAMPLERATE:
413 *data = sigma_get_samplerates_list();
415 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
418 names = (const char **)devc->channel_names;
419 count = g_strv_length(devc->channel_names);
420 *data = g_variant_new_strv(names, count);
422 case SR_CONF_CLOCK_EDGE:
423 *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges));
425 case SR_CONF_TRIGGER_MATCH:
426 *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
435 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
437 struct dev_context *devc;
438 uint16_t pindis_mask;
443 struct triggerinout triggerinout_conf;
444 struct triggerlut lut;
445 uint8_t regval, cmd_bytes[4], *wrptr;
449 /* Convert caller's trigger spec to driver's internal format. */
450 ret = sigma_convert_trigger(sdi);
452 sr_err("Could not configure triggers.");
457 * Setup the device's samplerate from the value which up to now
458 * just got checked and stored. As a byproduct this can pick and
459 * send firmware to the device, reduce the number of available
460 * logic channels, etc.
462 * Determine an acquisition timeout from optionally configured
463 * sample count or time limits. Which depends on the samplerate.
464 * Force 50MHz samplerate when external clock is in use.
466 if (devc->clock.use_ext_clock) {
467 if (devc->clock.samplerate != SR_MHZ(50))
468 sr_info("External clock, forcing 50MHz samplerate.");
469 devc->clock.samplerate = SR_MHZ(50);
471 ret = sigma_set_samplerate(sdi);
474 ret = sigma_set_acquire_timeout(devc);
478 /* Enter trigger programming mode. */
479 trigsel2 = TRGSEL2_RESET;
480 ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2);
485 if (devc->clock.samplerate >= SR_MHZ(100)) {
486 /* 100 and 200 MHz mode. */
487 /* TODO Decipher the 0x81 magic number's purpose. */
488 ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81);
492 /* Find which pin to trigger on from mask. */
493 for (triggerpin = 0; triggerpin < 8; triggerpin++) {
494 if (devc->trigger.risingmask & BIT(triggerpin))
496 if (devc->trigger.fallingmask & BIT(triggerpin))
500 /* Set trigger pin and light LED on trigger. */
501 trigsel2 = triggerpin & TRGSEL2_PINS_MASK;
502 trigsel2 |= TRGSEL2_LEDSEL1;
504 /* Default rising edge. */
505 /* TODO Documentation disagrees, bit set means _rising_ edge. */
506 if (devc->trigger.fallingmask)
507 trigsel2 |= TRGSEL2_PINPOL_RISE;
509 } else if (devc->clock.samplerate <= SR_MHZ(50)) {
510 /* 50MHz firmware modes. */
512 /* Translate application specs to hardware perspective. */
513 ret = sigma_build_basic_trigger(devc, &lut);
517 /* Communicate resulting register values to the device. */
518 ret = sigma_write_trigger_lut(devc, &lut);
522 trigsel2 = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0;
525 /* Setup trigger in and out pins to default values. */
526 memset(&triggerinout_conf, 0, sizeof(triggerinout_conf));
527 triggerinout_conf.trgout_bytrigger = TRUE;
528 triggerinout_conf.trgout_enable = TRUE;
530 * Verify the correctness of this implementation. The previous
531 * version used to assign to a C language struct with bit fields
532 * which is highly non-portable and hard to guess the resulting
533 * raw memory layout or wire transfer content. The C struct's
534 * field names did not match the vendor documentation's names.
535 * Which means that I could not verify "on paper" either. Let's
536 * re-visit this code later during research for trigger support.
540 if (triggerinout_conf.trgout_bytrigger)
541 regval |= TRGOPT_TRGOOUTEN;
542 write_u8_inc(&wrptr, regval);
543 regval &= ~TRGOPT_CLEAR_MASK;
544 if (triggerinout_conf.trgout_enable)
545 regval |= TRGOPT_TRGOEN;
546 write_u8_inc(&wrptr, regval);
547 ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION,
548 cmd_bytes, wrptr - cmd_bytes);
552 /* Leave trigger programming mode. */
553 ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2);
558 * Samplerate dependent clock and channels configuration. Some
559 * channels by design are not available at higher clock rates.
560 * Register layout differs between firmware variants (depth 1
561 * with LSB channel mask above 50MHz, depth 4 with more details
564 * Derive a mask where bits are set for unavailable channels.
565 * Either send the single byte, or the full byte sequence.
567 pindis_mask = ~BITS_MASK(devc->interp.num_channels);
568 if (devc->clock.samplerate > SR_MHZ(50)) {
569 ret = sigma_set_register(devc, WRITE_CLOCK_SELECT,
573 /* Select 50MHz base clock, and divider. */
575 div = SR_MHZ(50) / devc->clock.samplerate - 1;
576 if (devc->clock.use_ext_clock) {
577 async = CLKSEL_CLKSEL8;
578 div = devc->clock.clock_pin + 1;
579 switch (devc->clock.clock_edge) {
580 case SIGMA_CLOCK_EDGE_RISING:
581 div |= CLKSEL_RISING;
583 case SIGMA_CLOCK_EDGE_FALLING:
584 div |= CLKSEL_FALLING;
586 case SIGMA_CLOCK_EDGE_EITHER:
587 div |= CLKSEL_RISING;
588 div |= CLKSEL_FALLING;
592 write_u8_inc(&wrptr, async);
593 write_u8_inc(&wrptr, div);
594 write_u16be_inc(&wrptr, pindis_mask);
595 ret = sigma_write_register(devc, WRITE_CLOCK_SELECT,
596 cmd_bytes, wrptr - cmd_bytes);
601 /* Setup maximum post trigger time. */
602 ret = sigma_set_register(devc, WRITE_POST_TRIGGER,
603 (devc->capture_ratio * 255) / 100);
607 /* Start acqusition. */
608 regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
609 if (devc->use_triggers)
611 ret = sigma_set_register(devc, WRITE_MODE, regval);
615 ret = std_session_send_df_header(sdi);
619 /* Add capture source. */
620 ret = sr_session_source_add(sdi->session, -1, 0, 10,
621 sigma_receive_data, (void *)sdi);
625 devc->state = SIGMA_CAPTURE;
630 static int dev_acquisition_stop(struct sr_dev_inst *sdi)
632 struct dev_context *devc;
637 * When acquisition is currently running, keep the receive
638 * routine registered and have it stop the acquisition upon the
639 * next invocation. Else unregister the receive routine here
640 * already. The detour is required to have sample data retrieved
641 * for forced acquisition stops.
643 if (devc->state == SIGMA_CAPTURE) {
644 devc->state = SIGMA_STOPPING;
646 devc->state = SIGMA_IDLE;
647 (void)sr_session_source_remove(sdi->session, -1);
653 static struct sr_dev_driver asix_sigma_driver_info = {
654 .name = "asix-sigma",
655 .longname = "ASIX SIGMA/SIGMA2",
658 .cleanup = std_cleanup,
660 .dev_list = std_dev_list,
661 .dev_clear = dev_clear,
662 .config_get = config_get,
663 .config_set = config_set,
664 .config_list = config_list,
665 .dev_open = dev_open,
666 .dev_close = dev_close,
667 .dev_acquisition_start = dev_acquisition_start,
668 .dev_acquisition_stop = dev_acquisition_stop,
671 SR_REGISTER_DEV_DRIVER(asix_sigma_driver_info);