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Commit | Line | Data |
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1 | ------------------------------------------------------------------------------- | |
2 | Onewire dumps, sockit_owm master | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This directory contains waveforms created by accessing various onewire devices | |
6 | using the 'sockit_owm' Verilog master. The master is used in a demo hardware | |
7 | (Terasic DE1 development board, and a Quartus/Qsys project) and software (also | |
8 | available as a Nios II project) implementation. | |
9 | ||
10 | Details: | |
11 | https://github.com/jeras/sockit_owm | |
12 | ||
13 | ||
14 | Logic analyzer setup | |
15 | -------------------- | |
16 | ||
17 | The logic analyzer used was a Saleae Logic (at 8MHz): | |
18 | ||
19 | Probe 1-Wire pin | |
20 | ---------------------- | |
21 | 1 (black) OWR | |
22 | ||
23 | ||
24 | Data | |
25 | ---- | |
26 | ||
27 | The sigrok command line used was: | |
28 | ||
29 | sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr | |
30 | ||
31 | This is the console output after running the demo: | |
32 | ||
33 | (0) 6700000003A6A842 25.9 Celsius | |
34 | (1) 3F000000C8CF9B28 25.8 Celsius | |
35 | (2) 44000801E51EC510 25.9 Celsius | |
36 |