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Commit | Line | Data |
---|---|---|
1 | ------------------------------------------------------------------------------- | |
2 | 1MHz clock signal | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a set of example captures of a digital 1MHz clock signal (rectangle | |
6 | signal) generated using a function generator, sampled using a logic analyzer. | |
7 | ||
8 | ||
9 | Logic analyzer setup | |
10 | -------------------- | |
11 | ||
12 | The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): | |
13 | ||
14 | Probe Signal | |
15 | ----------------------------- | |
16 | 1 1MHz clock signal | |
17 | ||
18 | ||
19 | Data | |
20 | ---- | |
21 | ||
22 | The sigrok command line used was: | |
23 | ||
24 | sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ | |
25 | -o <filename> -p XXXX | |
26 | ||
27 | XXXX specifies how many probes to sample/save: | |
28 | ||
29 | - 1 signal: -p 1 | |
30 | - 4 signals: -p 1-4 | |
31 | - 7 signals: -p 1-7 | |
32 | - 8 signals: -p 1-8 | |
33 | - 9 signals: -p 1-9 | |
34 | - 16 signals: -p 1-16 | |
35 |