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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H | |
22 | #define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H | |
23 | ||
24 | /* Modified protocol commands & flags used by DSLogic */ | |
25 | #define DS_CMD_GET_FW_VERSION 0xb0 | |
26 | #define DS_CMD_GET_REVID_VERSION 0xb1 | |
27 | #define DS_CMD_START 0xb2 | |
28 | #define DS_CMD_FPGA_FW 0xb3 | |
29 | #define DS_CMD_CONFIG 0xb4 | |
30 | ||
31 | #define DS_NUM_TRIGGER_STAGES 16 | |
32 | #define DS_START_FLAGS_STOP (1 << 7) | |
33 | #define DS_START_FLAGS_CLK_48MHZ (1 << 6) | |
34 | #define DS_START_FLAGS_SAMPLE_WIDE (1 << 5) | |
35 | #define DS_START_FLAGS_MODE_LA (1 << 4) | |
36 | ||
37 | enum dslogic_operation_modes { | |
38 | DS_OP_NORMAL, | |
39 | DS_OP_INTERNAL_TEST, | |
40 | DS_OP_EXTERNAL_TEST, | |
41 | DS_OP_LOOPBACK_TEST, | |
42 | }; | |
43 | ||
44 | struct dslogic_version { | |
45 | uint8_t major; | |
46 | uint8_t minor; | |
47 | }; | |
48 | ||
49 | struct dslogic_mode { | |
50 | uint8_t flags; | |
51 | uint8_t sample_delay_h; | |
52 | uint8_t sample_delay_l; | |
53 | }; | |
54 | ||
55 | struct dslogic_trigger_pos { | |
56 | uint32_t real_pos; | |
57 | uint32_t ram_saddr; | |
58 | uint8_t first_block[504]; | |
59 | }; | |
60 | ||
61 | /* | |
62 | * The FPGA is configured with TLV tuples. Length is specified as the | |
63 | * number of 16-bit words, and the (type, length) header is in some | |
64 | * cases padded with 0xffff. | |
65 | */ | |
66 | #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt) | |
67 | #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff) | |
68 | #define DS_CFG_START 0xf5a5f5a5 | |
69 | #define DS_CFG_MODE _DS_CFG(0, 1) | |
70 | #define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2) | |
71 | #define DS_CFG_COUNT _DS_CFG_PAD(3, 2) | |
72 | #define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2) | |
73 | #define DS_CFG_TRIG_GLB _DS_CFG(7, 1) | |
74 | #define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2) | |
75 | #define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2) | |
76 | #define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16) | |
77 | #define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16) | |
78 | #define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16) | |
79 | #define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16) | |
80 | #define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16) | |
81 | #define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16) | |
82 | #define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16) | |
83 | #define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16) | |
84 | #define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16) | |
85 | #define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16) | |
86 | #define DS_CFG_END 0xfa5afa5a | |
87 | ||
88 | struct dslogic_fpga_config { | |
89 | uint32_t sync; | |
90 | uint16_t mode_header; | |
91 | uint16_t mode; | |
92 | uint32_t divider_header; | |
93 | uint32_t divider; | |
94 | uint32_t count_header; | |
95 | uint32_t count; | |
96 | uint32_t trig_pos_header; | |
97 | uint32_t trig_pos; | |
98 | uint16_t trig_glb_header; | |
99 | uint16_t trig_glb; | |
100 | uint32_t trig_adp_header; | |
101 | uint32_t trig_adp; | |
102 | uint32_t trig_sda_header; | |
103 | uint32_t trig_sda; | |
104 | uint32_t trig_mask0_header; | |
105 | uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES]; | |
106 | uint32_t trig_mask1_header; | |
107 | uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES]; | |
108 | uint32_t trig_value0_header; | |
109 | uint16_t trig_value0[DS_NUM_TRIGGER_STAGES]; | |
110 | uint32_t trig_value1_header; | |
111 | uint16_t trig_value1[DS_NUM_TRIGGER_STAGES]; | |
112 | uint32_t trig_edge0_header; | |
113 | uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES]; | |
114 | uint32_t trig_edge1_header; | |
115 | uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES]; | |
116 | uint32_t trig_count0_header; | |
117 | uint16_t trig_count0[DS_NUM_TRIGGER_STAGES]; | |
118 | uint32_t trig_count1_header; | |
119 | uint16_t trig_count1[DS_NUM_TRIGGER_STAGES]; | |
120 | uint32_t trig_logic0_header; | |
121 | uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES]; | |
122 | uint32_t trig_logic1_header; | |
123 | uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES]; | |
124 | uint32_t end_sync; | |
125 | }; | |
126 | ||
127 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, | |
128 | const char *name); | |
129 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi); | |
130 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi); | |
131 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi); | |
132 | ||
133 | #endif |