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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # LPC protocol decoder | |
22 | ||
23 | import sigrokdecode as srd | |
24 | ||
25 | # ... | |
26 | fields = { | |
27 | # START field (indicates start or stop of a transaction) | |
28 | 'START': { | |
29 | 0b0000: 'Start of cycle for a target', | |
30 | 0b0001: 'Reserved', | |
31 | 0b0010: 'Grant for bus master 0', | |
32 | 0b0011: 'Grant for bus master 1', | |
33 | 0b0100: 'Reserved', | |
34 | 0b0101: 'Reserved', | |
35 | 0b0110: 'Reserved', | |
36 | 0b0111: 'Reserved', | |
37 | 0b1000: 'Reserved', | |
38 | 0b1001: 'Reserved', | |
39 | 0b1010: 'Reserved', | |
40 | 0b1011: 'Reserved', | |
41 | 0b1100: 'Reserved', | |
42 | 0b1101: 'Start of cycle for a Firmware Memory Read cycle', | |
43 | 0b1110: 'Start of cycle for a Firmware Memory Write cycle', | |
44 | 0b1111: 'Stop/abort (end of a cycle for a target)', | |
45 | }, | |
46 | # Cycle type / direction field | |
47 | # Bit 0 (LAD[0]) is unused, should always be 0. | |
48 | # Neither host nor peripheral are allowed to drive 0b11x0. | |
49 | 'CT_DR': { | |
50 | 0b0000: 'I/O read', | |
51 | 0b0010: 'I/O write', | |
52 | 0b0100: 'Memory read', | |
53 | 0b0110: 'Memory write', | |
54 | 0b1000: 'DMA read', | |
55 | 0b1010: 'DMA write', | |
56 | 0b1100: 'Reserved / not allowed', | |
57 | 0b1110: 'Reserved / not allowed', | |
58 | }, | |
59 | # SIZE field (determines how many bytes are to be transferred) | |
60 | # Bits[3:2] are reserved, must be driven to 0b00. | |
61 | # Neither host nor peripheral are allowed to drive 0b0010. | |
62 | 'SIZE': { | |
63 | 0b0000: '8 bits (1 byte)', | |
64 | 0b0001: '16 bits (2 bytes)', | |
65 | 0b0010: 'Reserved / not allowed', | |
66 | 0b0011: '32 bits (4 bytes)', | |
67 | }, | |
68 | # CHANNEL field (bits[2:0] contain the DMA channel number) | |
69 | 'CHANNEL': { | |
70 | 0b0000: '0', | |
71 | 0b0001: '1', | |
72 | 0b0010: '2', | |
73 | 0b0011: '3', | |
74 | 0b0100: '4', | |
75 | 0b0101: '5', | |
76 | 0b0110: '6', | |
77 | 0b0111: '7', | |
78 | }, | |
79 | # SYNC field (used to add wait states) | |
80 | 'SYNC': { | |
81 | 0b0000: 'Ready', | |
82 | 0b0001: 'Reserved', | |
83 | 0b0010: 'Reserved', | |
84 | 0b0011: 'Reserved', | |
85 | 0b0100: 'Reserved', | |
86 | 0b0101: 'Short wait', | |
87 | 0b0110: 'Long wait', | |
88 | 0b0111: 'Reserved', | |
89 | 0b1000: 'Reserved', | |
90 | 0b1001: 'Ready more (DMA only)', | |
91 | 0b1010: 'Error', | |
92 | 0b1011: 'Reserved', | |
93 | 0b1100: 'Reserved', | |
94 | 0b1101: 'Reserved', | |
95 | 0b1110: 'Reserved', | |
96 | 0b1111: 'Reserved', | |
97 | }, | |
98 | } | |
99 | ||
100 | class Decoder(srd.Decoder): | |
101 | api_version = 1 | |
102 | id = 'lpc' | |
103 | name = 'LPC' | |
104 | longname = 'Low-Pin-Count' | |
105 | desc = 'Protocol for low-bandwidth devices on PC mainboards.' | |
106 | license = 'gplv2+' | |
107 | inputs = ['logic'] | |
108 | outputs = ['lpc'] | |
109 | probes = [ | |
110 | {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'}, | |
111 | {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'}, | |
112 | {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'}, | |
113 | {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'}, | |
114 | {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'}, | |
115 | {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'}, | |
116 | {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'}, | |
117 | ] | |
118 | optional_probes = [ | |
119 | {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'}, | |
120 | {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'}, | |
121 | {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'}, | |
122 | {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'}, | |
123 | {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'}, | |
124 | {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'}, | |
125 | ] | |
126 | options = {} | |
127 | annotations = [ | |
128 | ['Text', 'Human-readable text'], | |
129 | ] | |
130 | ||
131 | def __init__(self, **kwargs): | |
132 | self.state = 'IDLE' | |
133 | self.oldlclk = -1 | |
134 | self.samplenum = 0 | |
135 | self.clocknum = 0 | |
136 | self.lad = -1 | |
137 | self.addr = 0 | |
138 | self.cur_nibble = 0 | |
139 | self.cycle_type = -1 | |
140 | self.oldpins = (-1, -1, -1, -1, -1, -1, -1) | |
141 | ||
142 | def start(self, metadata): | |
143 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc') | |
144 | self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc') | |
145 | ||
146 | def report(self): | |
147 | pass | |
148 | ||
149 | def handle_get_start(self, lad, lframe): | |
150 | # LAD[3:0]: START field (1 clock cycle). | |
151 | ||
152 | # The last value of LAD[3:0] before LFRAME# gets de-asserted is what | |
153 | # the peripherals must use. However, the host can keep LFRAME# asserted | |
154 | # multiple clocks, and we output all START fields that occur, even | |
155 | # though the peripherals are supposed to ignore all but the last one. | |
156 | s = fields['START'][lad] | |
157 | self.put(0, 0, self.out_ann, [0, [s]]) | |
158 | ||
159 | # Output a warning if LAD[3:0] changes while LFRAME# is low. | |
160 | # TODO | |
161 | if (self.lad != -1 and self.lad != lad): | |
162 | self.put(0, 0, self.out_ann, | |
163 | [0, ['Warning: LAD[3:0] changed while ' | |
164 | 'LFRAME# was asserted']]) | |
165 | ||
166 | # LFRAME# is asserted (low). Wait until it gets de-asserted again | |
167 | # (the host is allowed to keep it asserted multiple clocks). | |
168 | if lframe != 1: | |
169 | return | |
170 | ||
171 | self.start_field = self.lad | |
172 | self.state = 'GET CT/DR' | |
173 | ||
174 | def handle_get_ct_dr(self, lad, lad_bits): | |
175 | # LAD[3:0]: Cycle type / direction field (1 clock cycle). | |
176 | ||
177 | self.cycle_type = fields['CT_DR'][lad] | |
178 | ||
179 | # TODO: Warning/error on invalid cycle types. | |
180 | if self.cycle_type == 'Reserved': | |
181 | self.put(0, 0, self.out_ann, | |
182 | [0, ['Warning: Invalid cycle type (%s)' % lad_bits]]) | |
183 | ||
184 | # ... | |
185 | self.put(0, 0, self.out_ann, [0, ['Cycle type: %s' % self.cycle_type]]) | |
186 | ||
187 | self.state = 'GET ADDR' | |
188 | self.addr = 0 | |
189 | self.cur_nibble = 0 | |
190 | ||
191 | def handle_get_addr(self, lad, lad_bits): | |
192 | # LAD[3:0]: ADDR field (4/8/0 clock cycles). | |
193 | ||
194 | # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks. | |
195 | # DMA cycles: no ADDR clocks at all. | |
196 | if self.cycle_type in ('I/O read', 'I/O write'): | |
197 | addr_nibbles = 4 # Address is 16bits. | |
198 | elif self.cycle_type in ('Memory read', 'Memory write'): | |
199 | addr_nibbles = 8 # Address is 32bits. | |
200 | else: | |
201 | addr_nibbles = 0 # TODO: How to handle later on? | |
202 | ||
203 | # Data is driven MSN-first. | |
204 | offset = ((addr_nibbles - 1) - self.cur_nibble) * 4 | |
205 | self.addr |= (lad << offset) | |
206 | ||
207 | # Continue if we haven't seen all ADDR cycles, yet. | |
208 | # TODO: Off-by-one? | |
209 | if (self.cur_nibble < addr_nibbles - 1): | |
210 | self.cur_nibble += 1 | |
211 | return | |
212 | ||
213 | self.put(0, 0, self.out_ann, [0, ['Address: %s' % hex(self.addr)]]) | |
214 | ||
215 | self.state = 'GET TAR' | |
216 | self.tar_count = 0 | |
217 | ||
218 | def handle_get_tar(self, lad, lad_bits): | |
219 | # LAD[3:0]: First TAR (turn-around) field (2 clock cycles). | |
220 | ||
221 | self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s' | |
222 | % (self.tarcount, lad_bits)]]) | |
223 | ||
224 | # On the first TAR clock cycle LAD[3:0] is driven to 1111 by | |
225 | # either the host or peripheral. On the second clock cycle, | |
226 | # the host or peripheral tri-states LAD[3:0], but its value | |
227 | # should still be 1111, due to pull-ups on the LAD lines. | |
228 | if lad_bits != '1111': | |
229 | self.put(0, 0, self.out_ann, | |
230 | [0, ['Warning: TAR, cycle %d: %s (expected 1111)' | |
231 | % (self.tarcount, lad_bits)]]) | |
232 | ||
233 | if (self.tarcount != 2): | |
234 | self.tarcount += 1 | |
235 | return | |
236 | ||
237 | self.state = 'GET SYNC' | |
238 | ||
239 | def handle_get_sync(self, lad, lad_bits): | |
240 | # LAD[3:0]: SYNC field (1-n clock cycles). | |
241 | ||
242 | self.sync_val = lad_bits | |
243 | self.cycle_type = fields['SYNC'][lad] | |
244 | ||
245 | # TODO: Warnings if reserved value are seen? | |
246 | if self.cycle_type == 'Reserved': | |
247 | self.put(0, 0, self.out_ann, [0, ['Warning: SYNC, cycle %d: %s ' | |
248 | '(reserved value)' % (self.synccount, self.sync_val)]]) | |
249 | ||
250 | self.put(0, 0, self.out_ann, [0, ['SYNC, cycle %d: %s' | |
251 | % (self.synccount, self.sync_val)]]) | |
252 | ||
253 | # TODO | |
254 | ||
255 | self.state = 'GET DATA' | |
256 | self.cycle_count = 0 | |
257 | ||
258 | def handle_get_data(self, lad, lad_bits): | |
259 | # LAD[3:0]: DATA field (2 clock cycles). | |
260 | ||
261 | if (self.cycle_count == 0): | |
262 | self.databyte = lad | |
263 | elif (self.cycle_count == 1): | |
264 | self.databyte |= (lad << 4) | |
265 | else: | |
266 | pass # TODO: Error? | |
267 | ||
268 | if (self.cycle_count != 2): | |
269 | self.cycle_count += 1 | |
270 | return | |
271 | ||
272 | self.put(0, 0, self.out_ann, [0, ['DATA: %s' % hex(self.databyte)]]) | |
273 | ||
274 | self.state = 'GET TAR2' | |
275 | ||
276 | def handle_get_tar2(self, lad, lad_bits): | |
277 | # LAD[3:0]: Second TAR field (2 clock cycles). | |
278 | ||
279 | self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s' | |
280 | % (self.tarcount, lad_bits)]]) | |
281 | ||
282 | # On the first TAR clock cycle LAD[3:0] is driven to 1111 by | |
283 | # either the host or peripheral. On the second clock cycle, | |
284 | # the host or peripheral tri-states LAD[3:0], but its value | |
285 | # should still be 1111, due to pull-ups on the LAD lines. | |
286 | if lad_bits != '1111': | |
287 | self.put(0, 0, self.out_ann, | |
288 | [0, ['Warning: TAR, cycle %d: %s (expected 1111)' | |
289 | % (self.tarcount, lad_bits)]]) | |
290 | ||
291 | if (self.tarcount != 2): | |
292 | self.tarcount += 1 | |
293 | return | |
294 | ||
295 | self.state = 'GET SYNC' | |
296 | ||
297 | # TODO: At which edge of the clock is data latched? Falling? | |
298 | def decode(self, ss, es, data): | |
299 | for (samplenum, pins) in data: | |
300 | ||
301 | # If none of the pins changed, there's nothing to do. | |
302 | if self.oldpins == pins: | |
303 | continue | |
304 | ||
305 | # Store current pin values for the next round. | |
306 | self.oldpins = pins | |
307 | ||
308 | # Get individual pin values into local variables. | |
309 | # TODO: Handle optional pins. | |
310 | (lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins | |
311 | ||
312 | # Only look at the signals upon falling LCLK edges. | |
313 | # TODO: Rising? | |
314 | ## if not (self.oldlclk == 1 and lclk == 0) | |
315 | ## self.oldlclk = lclk | |
316 | ## continue | |
317 | ||
318 | # Store LAD[3:0] bit values (one nibble) in local variables. | |
319 | # Most (but not all) states need this. | |
320 | if self.state != 'IDLE': | |
321 | lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 | |
322 | lad_bits = bin(lad)[2:] | |
323 | ||
324 | # State machine | |
325 | if self.state == 'IDLE': | |
326 | # A valid LPC cycle starts with LFRAME# being asserted (low). | |
327 | # TODO? | |
328 | if lframe != 0: | |
329 | continue | |
330 | self.state = 'GET START' | |
331 | self.lad = -1 | |
332 | # self.clocknum = 0 | |
333 | elif self.state == 'GET START': | |
334 | handle_get_start(lad, lad_bits, lframe) | |
335 | elif self.state == 'GET CT/DR': | |
336 | handle_get_ct_dr(lad, lad_bits) | |
337 | elif self.state == 'GET ADDR': | |
338 | handle_get_addr(lad, lad_bits) | |
339 | elif self.state == 'GET TAR': | |
340 | handle_get_tar(lad, lad_bits) | |
341 | elif self.state == 'GET SYNC': | |
342 | handle_get_sync(lad, lad_bits) | |
343 | elif self.state == 'GET DATA': | |
344 | handle_get_data(lad, lad_bits) | |
345 | elif self.state == 'GET TAR2': | |
346 | handle_get_tar2(lad, lad_bits) | |
347 | else: | |
348 | raise Exception('Invalid state: %s' % self.state) | |
349 |