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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45
46static const uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1",
67 "2",
68 "3",
69 "4",
70 "5",
71 "6",
72 "7",
73 "8",
74 "9",
75 "10",
76 "11",
77 "12",
78 "13",
79 "14",
80 "15",
81 "16",
82 NULL,
83};
84
85static const struct sr_samplerates samplerates = {
86 0,
87 0,
88 0,
89 supported_samplerates,
90};
91
92static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
94 SR_HWCAP_SAMPLERATE,
95 SR_HWCAP_CAPTURE_RATIO,
96
97 SR_HWCAP_LIMIT_MSEC,
98 0,
99};
100
101/* Force the FPGA to reboot. */
102static uint8_t suicide[] = {
103 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
104};
105
106/* Prepare to upload firmware (FPGA specific). */
107static uint8_t init[] = {
108 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
109};
110
111/* Initialize the logic analyzer mode. */
112static uint8_t logic_mode_start[] = {
113 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
114 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
115};
116
117static const char *firmware_files[] = {
118 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
119 "asix-sigma-100.fw", /* 100 MHz */
120 "asix-sigma-200.fw", /* 200 MHz */
121 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
122 "asix-sigma-phasor.fw", /* Frequency counter */
123};
124
125static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
126 void *cb_data);
127
128static int sigma_read(void *buf, size_t size, struct dev_context *devc)
129{
130 int ret;
131
132 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
133 if (ret < 0) {
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&devc->ftdic));
136 }
137
138 return ret;
139}
140
141static int sigma_write(void *buf, size_t size, struct dev_context *devc)
142{
143 int ret;
144
145 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
146 if (ret < 0) {
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&devc->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
151 }
152
153 return ret;
154}
155
156static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
157 struct dev_context *devc)
158{
159 size_t i;
160 uint8_t buf[len + 2];
161 int idx = 0;
162
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
165
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
169 }
170
171 return sigma_write(buf, idx, devc);
172}
173
174static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
175{
176 return sigma_write_register(reg, &value, 1, devc);
177}
178
179static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
180 struct dev_context *devc)
181{
182 uint8_t buf[3];
183
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
187
188 sigma_write(buf, sizeof(buf), devc);
189
190 return sigma_read(data, len, devc);
191}
192
193static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
194{
195 uint8_t value;
196
197 if (1 != sigma_read_register(reg, &value, 1, devc)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
199 return 0;
200 }
201
202 return value;
203}
204
205static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
206 struct dev_context *devc)
207{
208 uint8_t buf[] = {
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
210
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 };
218 uint8_t result[6];
219
220 sigma_write(buf, sizeof(buf), devc);
221
222 sigma_read(result, sizeof(result), devc);
223
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
226
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
229 stoppos -= 64;
230
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
232 triggerpos -= 64;
233
234 return 1;
235}
236
237static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct dev_context *devc)
239{
240 size_t i;
241 uint8_t buf[4096];
242 int idx = 0;
243
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
248
249 /* Read the DRAM. */
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
252
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
257
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
259
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
262 }
263
264 sigma_write(buf, idx, devc);
265
266 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
267}
268
269/* Upload trigger look-up tables to Sigma. */
270static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
271{
272 int i;
273 uint8_t tmp[2];
274 uint16_t bit;
275
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
278 bit = 1 << i;
279
280 tmp[0] = tmp[1] = 0;
281
282 if (lut->m2d[0] & bit)
283 tmp[0] |= 0x01;
284 if (lut->m2d[1] & bit)
285 tmp[0] |= 0x02;
286 if (lut->m2d[2] & bit)
287 tmp[0] |= 0x04;
288 if (lut->m2d[3] & bit)
289 tmp[0] |= 0x08;
290
291 if (lut->m3 & bit)
292 tmp[0] |= 0x10;
293 if (lut->m3s & bit)
294 tmp[0] |= 0x20;
295 if (lut->m4 & bit)
296 tmp[0] |= 0x40;
297
298 if (lut->m0d[0] & bit)
299 tmp[1] |= 0x01;
300 if (lut->m0d[1] & bit)
301 tmp[1] |= 0x02;
302 if (lut->m0d[2] & bit)
303 tmp[1] |= 0x04;
304 if (lut->m0d[3] & bit)
305 tmp[1] |= 0x08;
306
307 if (lut->m1d[0] & bit)
308 tmp[1] |= 0x10;
309 if (lut->m1d[1] & bit)
310 tmp[1] |= 0x20;
311 if (lut->m1d[2] & bit)
312 tmp[1] |= 0x40;
313 if (lut->m1d[3] & bit)
314 tmp[1] |= 0x80;
315
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
317 devc);
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
319 }
320
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), devc);
324
325 return SR_OK;
326}
327
328/* Generate the bitbang stream for programming the FPGA. */
329static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
331{
332 FILE *f;
333 unsigned long file_size;
334 unsigned long offset = 0;
335 unsigned char *p;
336 uint8_t *firmware;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
339 size_t i;
340 int c, bit, v;
341 uint32_t imm = 0x3f6df2ab;
342
343 f = g_fopen(filename, "rb");
344 if (!f) {
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
346 return SR_ERR;
347 }
348
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
351 fclose(f);
352 return SR_ERR;
353 }
354
355 file_size = ftell(f);
356
357 fseek(f, 0, SEEK_SET);
358
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
361 fclose(f);
362 return SR_ERR_MALLOC;
363 }
364
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
368 }
369 fclose(f);
370
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
373 fclose(f);
374 g_free(firmware);
375 return SR_ERR;
376 }
377
378 *buf_size = fwsize * 2 * 8;
379
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
381 if (!p) {
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
383 g_free(firmware);
384 return SR_ERR_MALLOC;
385 }
386
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
391 p[offset++] = v;
392 }
393 }
394
395 g_free(firmware);
396
397 if (offset != *buf_size) {
398 g_free(*buf);
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
402
403 return SR_ERR;
404 }
405
406 return SR_OK;
407}
408
409static int clear_instances(void)
410{
411 GSList *l;
412 struct sr_dev_inst *sdi;
413 struct drv_context *drvc;
414 struct dev_context *devc;
415
416 drvc = adi->priv;
417
418 /* Properly close all devices. */
419 for (l = drvc->instances; l; l = l->next) {
420 if (!(sdi = l->data)) {
421 /* Log error, but continue cleaning up the rest. */
422 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
423 continue;
424 }
425 if (sdi->priv) {
426 devc = sdi->priv;
427 ftdi_free(&devc->ftdic);
428 }
429 sr_dev_inst_free(sdi);
430 }
431 g_slist_free(drvc->instances);
432 drvc->instances = NULL;
433
434 return SR_OK;
435}
436
437static int hw_init(void)
438{
439 struct drv_context *drvc;
440
441 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
442 sr_err("asix-sigma: driver context malloc failed.");
443 return SR_ERR;
444 }
445 adi->priv = drvc;
446
447 return SR_OK;
448}
449
450static GSList *hw_scan(GSList *options)
451{
452 struct sr_dev_inst *sdi;
453 struct sr_probe *probe;
454 struct drv_context *drvc;
455 struct dev_context *devc;
456 GSList *devices;
457 struct ftdi_device_list *devlist;
458 char serial_txt[10];
459 uint32_t serial;
460 int ret, i;
461
462 (void)options;
463 drvc = adi->priv;
464 devices = NULL;
465 clear_instances();
466
467 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
468 sr_err("sigma: %s: devc malloc failed", __func__);
469 return NULL;
470 }
471
472 ftdi_init(&devc->ftdic);
473
474 /* Look for SIGMAs. */
475
476 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
477 USB_VENDOR, USB_PRODUCT)) <= 0) {
478 if (ret < 0)
479 sr_err("ftdi_usb_find_all(): %d", ret);
480 goto free;
481 }
482
483 /* Make sure it's a version 1 or 2 SIGMA. */
484 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
485 serial_txt, sizeof(serial_txt));
486 sscanf(serial_txt, "%x", &serial);
487
488 if (serial < 0xa6010000 || serial > 0xa602ffff) {
489 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
490 "in this version of sigrok.");
491 goto free;
492 }
493
494 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
495
496 devc->cur_samplerate = 0;
497 devc->period_ps = 0;
498 devc->limit_msec = 0;
499 devc->cur_firmware = -1;
500 devc->num_probes = 0;
501 devc->samples_per_event = 0;
502 devc->capture_ratio = 50;
503 devc->use_triggers = 0;
504
505 /* Register SIGMA device. */
506 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
507 USB_MODEL_NAME, USB_MODEL_VERSION))) {
508 sr_err("sigma: %s: sdi was NULL", __func__);
509 goto free;
510 }
511 sdi->driver = adi;
512
513 for (i = 0; probe_names[i]; i++) {
514 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
515 probe_names[i])))
516 return NULL;
517 sdi->probes = g_slist_append(sdi->probes, probe);
518 }
519
520 devices = g_slist_append(devices, sdi);
521 drvc->instances = g_slist_append(drvc->instances, sdi);
522 sdi->priv = devc;
523
524 /* We will open the device again when we need it. */
525 ftdi_list_free(&devlist);
526
527 return devices;
528
529free:
530 ftdi_deinit(&devc->ftdic);
531 g_free(devc);
532 return NULL;
533}
534
535static GSList *hw_dev_list(void)
536{
537 struct drv_context *drvc;
538
539 drvc = adi->priv;
540
541 return drvc->instances;
542}
543
544static int upload_firmware(int firmware_idx, struct dev_context *devc)
545{
546 int ret;
547 unsigned char *buf;
548 unsigned char pins;
549 size_t buf_size;
550 unsigned char result[32];
551 char firmware_path[128];
552
553 /* Make sure it's an ASIX SIGMA. */
554 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
555 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
556 sr_err("sigma: ftdi_usb_open failed: %s",
557 ftdi_get_error_string(&devc->ftdic));
558 return 0;
559 }
560
561 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
562 sr_err("sigma: ftdi_set_bitmode failed: %s",
563 ftdi_get_error_string(&devc->ftdic));
564 return 0;
565 }
566
567 /* Four times the speed of sigmalogan - Works well. */
568 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
569 sr_err("sigma: ftdi_set_baudrate failed: %s",
570 ftdi_get_error_string(&devc->ftdic));
571 return 0;
572 }
573
574 /* Force the FPGA to reboot. */
575 sigma_write(suicide, sizeof(suicide), devc);
576 sigma_write(suicide, sizeof(suicide), devc);
577 sigma_write(suicide, sizeof(suicide), devc);
578 sigma_write(suicide, sizeof(suicide), devc);
579
580 /* Prepare to upload firmware (FPGA specific). */
581 sigma_write(init, sizeof(init), devc);
582
583 ftdi_usb_purge_buffers(&devc->ftdic);
584
585 /* Wait until the FPGA asserts INIT_B. */
586 while (1) {
587 ret = sigma_read(result, 1, devc);
588 if (result[0] & 0x20)
589 break;
590 }
591
592 /* Prepare firmware. */
593 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
594 firmware_files[firmware_idx]);
595
596 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
597 sr_err("sigma: An error occured while reading the firmware: %s",
598 firmware_path);
599 return ret;
600 }
601
602 /* Upload firmare. */
603 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
604 sigma_write(buf, buf_size, devc);
605
606 g_free(buf);
607
608 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
609 sr_err("sigma: ftdi_set_bitmode failed: %s",
610 ftdi_get_error_string(&devc->ftdic));
611 return SR_ERR;
612 }
613
614 ftdi_usb_purge_buffers(&devc->ftdic);
615
616 /* Discard garbage. */
617 while (1 == sigma_read(&pins, 1, devc))
618 ;
619
620 /* Initialize the logic analyzer mode. */
621 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
622
623 /* Expect a 3 byte reply. */
624 ret = sigma_read(result, 3, devc);
625 if (ret != 3 ||
626 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
627 sr_err("sigma: Configuration failed. Invalid reply received.");
628 return SR_ERR;
629 }
630
631 devc->cur_firmware = firmware_idx;
632
633 sr_info("sigma: Firmware uploaded");
634
635 return SR_OK;
636}
637
638static int hw_dev_open(struct sr_dev_inst *sdi)
639{
640 struct dev_context *devc;
641 int ret;
642
643 devc = sdi->priv;
644
645 /* Make sure it's an ASIX SIGMA. */
646 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
647 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
648
649 sr_err("sigma: ftdi_usb_open failed: %s",
650 ftdi_get_error_string(&devc->ftdic));
651
652 return 0;
653 }
654
655 sdi->status = SR_ST_ACTIVE;
656
657 return SR_OK;
658}
659
660static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
661{
662 int i, ret;
663 struct dev_context *devc = sdi->priv;
664
665 for (i = 0; supported_samplerates[i]; i++) {
666 if (supported_samplerates[i] == samplerate)
667 break;
668 }
669 if (supported_samplerates[i] == 0)
670 return SR_ERR_SAMPLERATE;
671
672 if (samplerate <= SR_MHZ(50)) {
673 ret = upload_firmware(0, devc);
674 devc->num_probes = 16;
675 }
676 if (samplerate == SR_MHZ(100)) {
677 ret = upload_firmware(1, devc);
678 devc->num_probes = 8;
679 }
680 else if (samplerate == SR_MHZ(200)) {
681 ret = upload_firmware(2, devc);
682 devc->num_probes = 4;
683 }
684
685 devc->cur_samplerate = samplerate;
686 devc->period_ps = 1000000000000 / samplerate;
687 devc->samples_per_event = 16 / devc->num_probes;
688 devc->state.state = SIGMA_IDLE;
689
690 return ret;
691}
692
693/*
694 * In 100 and 200 MHz mode, only a single pin rising/falling can be
695 * set as trigger. In other modes, two rising/falling triggers can be set,
696 * in addition to value/mask trigger for any number of probes.
697 *
698 * The Sigma supports complex triggers using boolean expressions, but this
699 * has not been implemented yet.
700 */
701static int configure_probes(const struct sr_dev_inst *sdi)
702{
703 struct dev_context *devc = sdi->priv;
704 const struct sr_probe *probe;
705 const GSList *l;
706 int trigger_set = 0;
707 int probebit;
708
709 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
710
711 for (l = sdi->probes; l; l = l->next) {
712 probe = (struct sr_probe *)l->data;
713 probebit = 1 << (probe->index);
714
715 if (!probe->enabled || !probe->trigger)
716 continue;
717
718 if (devc->cur_samplerate >= SR_MHZ(100)) {
719 /* Fast trigger support. */
720 if (trigger_set) {
721 sr_err("sigma: ASIX SIGMA only supports a single "
722 "pin trigger in 100 and 200MHz mode.");
723 return SR_ERR;
724 }
725 if (probe->trigger[0] == 'f')
726 devc->trigger.fallingmask |= probebit;
727 else if (probe->trigger[0] == 'r')
728 devc->trigger.risingmask |= probebit;
729 else {
730 sr_err("sigma: ASIX SIGMA only supports "
731 "rising/falling trigger in 100 "
732 "and 200MHz mode.");
733 return SR_ERR;
734 }
735
736 ++trigger_set;
737 } else {
738 /* Simple trigger support (event). */
739 if (probe->trigger[0] == '1') {
740 devc->trigger.simplevalue |= probebit;
741 devc->trigger.simplemask |= probebit;
742 }
743 else if (probe->trigger[0] == '0') {
744 devc->trigger.simplevalue &= ~probebit;
745 devc->trigger.simplemask |= probebit;
746 }
747 else if (probe->trigger[0] == 'f') {
748 devc->trigger.fallingmask |= probebit;
749 ++trigger_set;
750 }
751 else if (probe->trigger[0] == 'r') {
752 devc->trigger.risingmask |= probebit;
753 ++trigger_set;
754 }
755
756 /*
757 * Actually, Sigma supports 2 rising/falling triggers,
758 * but they are ORed and the current trigger syntax
759 * does not permit ORed triggers.
760 */
761 if (trigger_set > 1) {
762 sr_err("sigma: ASIX SIGMA only supports 1 "
763 "rising/falling triggers.");
764 return SR_ERR;
765 }
766 }
767
768 if (trigger_set)
769 devc->use_triggers = 1;
770 }
771
772 return SR_OK;
773}
774
775static int hw_dev_close(struct sr_dev_inst *sdi)
776{
777 struct dev_context *devc;
778
779 if (!(devc = sdi->priv)) {
780 sr_err("sigma: %s: sdi->priv was NULL", __func__);
781 return SR_ERR_BUG;
782 }
783
784 /* TODO */
785 if (sdi->status == SR_ST_ACTIVE)
786 ftdi_usb_close(&devc->ftdic);
787
788 sdi->status = SR_ST_INACTIVE;
789
790 return SR_OK;
791}
792
793static int hw_cleanup(void)
794{
795
796 if (!adi->priv)
797 return SR_OK;
798
799 clear_instances();
800
801 return SR_OK;
802}
803
804static int hw_info_get(int info_id, const void **data,
805 const struct sr_dev_inst *sdi)
806{
807 struct dev_context *devc;
808
809 switch (info_id) {
810 case SR_DI_HWCAPS:
811 *data = hwcaps;
812 break;
813 case SR_DI_NUM_PROBES:
814 *data = GINT_TO_POINTER(NUM_PROBES);
815 break;
816 case SR_DI_PROBE_NAMES:
817 *data = probe_names;
818 break;
819 case SR_DI_SAMPLERATES:
820 *data = &samplerates;
821 break;
822 case SR_DI_TRIGGER_TYPES:
823 *data = (char *)TRIGGER_TYPES;
824 break;
825 case SR_DI_CUR_SAMPLERATE:
826 if (sdi) {
827 devc = sdi->priv;
828 *data = &devc->cur_samplerate;
829 } else
830 return SR_ERR;
831 break;
832 default:
833 return SR_ERR_ARG;
834 }
835
836 return SR_OK;
837}
838
839static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
840 const void *value)
841{
842 struct dev_context *devc;
843 int ret;
844
845 devc = sdi->priv;
846
847 if (hwcap == SR_HWCAP_SAMPLERATE) {
848 ret = set_samplerate(sdi, *(const uint64_t *)value);
849 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
850 devc->limit_msec = *(const uint64_t *)value;
851 if (devc->limit_msec > 0)
852 ret = SR_OK;
853 else
854 ret = SR_ERR;
855 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
856 devc->capture_ratio = *(const uint64_t *)value;
857 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
858 ret = SR_ERR;
859 else
860 ret = SR_OK;
861 } else {
862 ret = SR_ERR;
863 }
864
865 return ret;
866}
867
868/* Software trigger to determine exact trigger position. */
869static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
870 struct sigma_trigger *t)
871{
872 int i;
873
874 for (i = 0; i < 8; ++i) {
875 if (i > 0)
876 last_sample = samples[i-1];
877
878 /* Simple triggers. */
879 if ((samples[i] & t->simplemask) != t->simplevalue)
880 continue;
881
882 /* Rising edge. */
883 if ((last_sample & t->risingmask) != 0 || (samples[i] &
884 t->risingmask) != t->risingmask)
885 continue;
886
887 /* Falling edge. */
888 if ((last_sample & t->fallingmask) != t->fallingmask ||
889 (samples[i] & t->fallingmask) != 0)
890 continue;
891
892 break;
893 }
894
895 /* If we did not match, return original trigger pos. */
896 return i & 0x7;
897}
898
899/*
900 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
901 * Each event is 20ns apart, and can contain multiple samples.
902 *
903 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
904 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
905 * For 50 MHz and below, events contain one sample for each channel,
906 * spread 20 ns apart.
907 */
908static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
909 uint16_t *lastsample, int triggerpos,
910 uint16_t limit_chunk, void *cb_data)
911{
912 struct sr_dev_inst *sdi = cb_data;
913 struct dev_context *devc = sdi->priv;
914 uint16_t tsdiff, ts;
915 uint16_t samples[65536 * devc->samples_per_event];
916 struct sr_datafeed_packet packet;
917 struct sr_datafeed_logic logic;
918 int i, j, k, l, numpad, tosend;
919 size_t n = 0, sent = 0;
920 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
921 uint16_t *event;
922 uint16_t cur_sample;
923 int triggerts = -1;
924
925 /* Check if trigger is in this chunk. */
926 if (triggerpos != -1) {
927 if (devc->cur_samplerate <= SR_MHZ(50))
928 triggerpos -= EVENTS_PER_CLUSTER - 1;
929
930 if (triggerpos < 0)
931 triggerpos = 0;
932
933 /* Find in which cluster the trigger occured. */
934 triggerts = triggerpos / 7;
935 }
936
937 /* For each ts. */
938 for (i = 0; i < 64; ++i) {
939 ts = *(uint16_t *) &buf[i * 16];
940 tsdiff = ts - *lastts;
941 *lastts = ts;
942
943 /* Decode partial chunk. */
944 if (limit_chunk && ts > limit_chunk)
945 return SR_OK;
946
947 /* Pad last sample up to current point. */
948 numpad = tsdiff * devc->samples_per_event - clustersize;
949 if (numpad > 0) {
950 for (j = 0; j < numpad; ++j)
951 samples[j] = *lastsample;
952
953 n = numpad;
954 }
955
956 /* Send samples between previous and this timestamp to sigrok. */
957 sent = 0;
958 while (sent < n) {
959 tosend = MIN(2048, n - sent);
960
961 packet.type = SR_DF_LOGIC;
962 packet.payload = &logic;
963 logic.length = tosend * sizeof(uint16_t);
964 logic.unitsize = 2;
965 logic.data = samples + sent;
966 sr_session_send(devc->session_dev_id, &packet);
967
968 sent += tosend;
969 }
970 n = 0;
971
972 event = (uint16_t *) &buf[i * 16 + 2];
973 cur_sample = 0;
974
975 /* For each event in cluster. */
976 for (j = 0; j < 7; ++j) {
977
978 /* For each sample in event. */
979 for (k = 0; k < devc->samples_per_event; ++k) {
980 cur_sample = 0;
981
982 /* For each probe. */
983 for (l = 0; l < devc->num_probes; ++l)
984 cur_sample |= (!!(event[j] & (1 << (l *
985 devc->samples_per_event + k)))) << l;
986
987 samples[n++] = cur_sample;
988 }
989 }
990
991 /* Send data up to trigger point (if triggered). */
992 sent = 0;
993 if (i == triggerts) {
994 /*
995 * Trigger is not always accurate to sample because of
996 * pipeline delay. However, it always triggers before
997 * the actual event. We therefore look at the next
998 * samples to pinpoint the exact position of the trigger.
999 */
1000 tosend = get_trigger_offset(samples, *lastsample,
1001 &devc->trigger);
1002
1003 if (tosend > 0) {
1004 packet.type = SR_DF_LOGIC;
1005 packet.payload = &logic;
1006 logic.length = tosend * sizeof(uint16_t);
1007 logic.unitsize = 2;
1008 logic.data = samples;
1009 sr_session_send(devc->session_dev_id, &packet);
1010
1011 sent += tosend;
1012 }
1013
1014 /* Only send trigger if explicitly enabled. */
1015 if (devc->use_triggers) {
1016 packet.type = SR_DF_TRIGGER;
1017 sr_session_send(devc->session_dev_id, &packet);
1018 }
1019 }
1020
1021 /* Send rest of the chunk to sigrok. */
1022 tosend = n - sent;
1023
1024 if (tosend > 0) {
1025 packet.type = SR_DF_LOGIC;
1026 packet.payload = &logic;
1027 logic.length = tosend * sizeof(uint16_t);
1028 logic.unitsize = 2;
1029 logic.data = samples + sent;
1030 sr_session_send(devc->session_dev_id, &packet);
1031 }
1032
1033 *lastsample = samples[n - 1];
1034 }
1035
1036 return SR_OK;
1037}
1038
1039static int receive_data(int fd, int revents, void *cb_data)
1040{
1041 struct sr_dev_inst *sdi = cb_data;
1042 struct dev_context *devc = sdi->priv;
1043 struct sr_datafeed_packet packet;
1044 const int chunks_per_read = 32;
1045 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1046 int bufsz, numchunks, i, newchunks;
1047 uint64_t running_msec;
1048 struct timeval tv;
1049
1050 /* Avoid compiler warnings. */
1051 (void)fd;
1052 (void)revents;
1053
1054 /* Get the current position. */
1055 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1056
1057 numchunks = (devc->state.stoppos + 511) / 512;
1058
1059 if (devc->state.state == SIGMA_IDLE)
1060 return TRUE;
1061
1062 if (devc->state.state == SIGMA_CAPTURE) {
1063 /* Check if the timer has expired, or memory is full. */
1064 gettimeofday(&tv, 0);
1065 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1066 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1067
1068 if (running_msec < devc->limit_msec && numchunks < 32767)
1069 return TRUE; /* While capturing... */
1070 else
1071 hw_dev_acquisition_stop(sdi, sdi);
1072
1073 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1074 if (devc->state.chunks_downloaded >= numchunks) {
1075 /* End of samples. */
1076 packet.type = SR_DF_END;
1077 sr_session_send(devc->session_dev_id, &packet);
1078
1079 devc->state.state = SIGMA_IDLE;
1080
1081 return TRUE;
1082 }
1083
1084 newchunks = MIN(chunks_per_read,
1085 numchunks - devc->state.chunks_downloaded);
1086
1087 sr_info("sigma: Downloading sample data: %.0f %%",
1088 100.0 * devc->state.chunks_downloaded / numchunks);
1089
1090 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1091 newchunks, buf, devc);
1092 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1093 (void)bufsz;
1094
1095 /* Find first ts. */
1096 if (devc->state.chunks_downloaded == 0) {
1097 devc->state.lastts = *(uint16_t *) buf - 1;
1098 devc->state.lastsample = 0;
1099 }
1100
1101 /* Decode chunks and send them to sigrok. */
1102 for (i = 0; i < newchunks; ++i) {
1103 int limit_chunk = 0;
1104
1105 /* The last chunk may potentially be only in part. */
1106 if (devc->state.chunks_downloaded == numchunks - 1) {
1107 /* Find the last valid timestamp */
1108 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1109 }
1110
1111 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1112 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1113 &devc->state.lastts,
1114 &devc->state.lastsample,
1115 devc->state.triggerpos & 0x1ff,
1116 limit_chunk, sdi);
1117 else
1118 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1119 &devc->state.lastts,
1120 &devc->state.lastsample,
1121 -1, limit_chunk, sdi);
1122
1123 ++devc->state.chunks_downloaded;
1124 }
1125 }
1126
1127 return TRUE;
1128}
1129
1130/* Build a LUT entry used by the trigger functions. */
1131static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1132{
1133 int i, j, k, bit;
1134
1135 /* For each quad probe. */
1136 for (i = 0; i < 4; ++i) {
1137 entry[i] = 0xffff;
1138
1139 /* For each bit in LUT. */
1140 for (j = 0; j < 16; ++j)
1141
1142 /* For each probe in quad. */
1143 for (k = 0; k < 4; ++k) {
1144 bit = 1 << (i * 4 + k);
1145
1146 /* Set bit in entry */
1147 if ((mask & bit) &&
1148 ((!(value & bit)) !=
1149 (!(j & (1 << k)))))
1150 entry[i] &= ~(1 << j);
1151 }
1152 }
1153}
1154
1155/* Add a logical function to LUT mask. */
1156static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1157 int index, int neg, uint16_t *mask)
1158{
1159 int i, j;
1160 int x[2][2], tmp, a, b, aset, bset, rset;
1161
1162 memset(x, 0, 4 * sizeof(int));
1163
1164 /* Trigger detect condition. */
1165 switch (oper) {
1166 case OP_LEVEL:
1167 x[0][1] = 1;
1168 x[1][1] = 1;
1169 break;
1170 case OP_NOT:
1171 x[0][0] = 1;
1172 x[1][0] = 1;
1173 break;
1174 case OP_RISE:
1175 x[0][1] = 1;
1176 break;
1177 case OP_FALL:
1178 x[1][0] = 1;
1179 break;
1180 case OP_RISEFALL:
1181 x[0][1] = 1;
1182 x[1][0] = 1;
1183 break;
1184 case OP_NOTRISE:
1185 x[1][1] = 1;
1186 x[0][0] = 1;
1187 x[1][0] = 1;
1188 break;
1189 case OP_NOTFALL:
1190 x[1][1] = 1;
1191 x[0][0] = 1;
1192 x[0][1] = 1;
1193 break;
1194 case OP_NOTRISEFALL:
1195 x[1][1] = 1;
1196 x[0][0] = 1;
1197 break;
1198 }
1199
1200 /* Transpose if neg is set. */
1201 if (neg) {
1202 for (i = 0; i < 2; ++i) {
1203 for (j = 0; j < 2; ++j) {
1204 tmp = x[i][j];
1205 x[i][j] = x[1-i][1-j];
1206 x[1-i][1-j] = tmp;
1207 }
1208 }
1209 }
1210
1211 /* Update mask with function. */
1212 for (i = 0; i < 16; ++i) {
1213 a = (i >> (2 * index + 0)) & 1;
1214 b = (i >> (2 * index + 1)) & 1;
1215
1216 aset = (*mask >> i) & 1;
1217 bset = x[b][a];
1218
1219 if (func == FUNC_AND || func == FUNC_NAND)
1220 rset = aset & bset;
1221 else if (func == FUNC_OR || func == FUNC_NOR)
1222 rset = aset | bset;
1223 else if (func == FUNC_XOR || func == FUNC_NXOR)
1224 rset = aset ^ bset;
1225
1226 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1227 rset = !rset;
1228
1229 *mask &= ~(1 << i);
1230
1231 if (rset)
1232 *mask |= 1 << i;
1233 }
1234}
1235
1236/*
1237 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1238 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1239 * set at any time, but a full mask and value can be set (0/1).
1240 */
1241static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1242{
1243 int i,j;
1244 uint16_t masks[2] = { 0, 0 };
1245
1246 memset(lut, 0, sizeof(struct triggerlut));
1247
1248 /* Contant for simple triggers. */
1249 lut->m4 = 0xa000;
1250
1251 /* Value/mask trigger support. */
1252 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1253 lut->m2d);
1254
1255 /* Rise/fall trigger support. */
1256 for (i = 0, j = 0; i < 16; ++i) {
1257 if (devc->trigger.risingmask & (1 << i) ||
1258 devc->trigger.fallingmask & (1 << i))
1259 masks[j++] = 1 << i;
1260 }
1261
1262 build_lut_entry(masks[0], masks[0], lut->m0d);
1263 build_lut_entry(masks[1], masks[1], lut->m1d);
1264
1265 /* Add glue logic */
1266 if (masks[0] || masks[1]) {
1267 /* Transition trigger. */
1268 if (masks[0] & devc->trigger.risingmask)
1269 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1270 if (masks[0] & devc->trigger.fallingmask)
1271 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1272 if (masks[1] & devc->trigger.risingmask)
1273 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1274 if (masks[1] & devc->trigger.fallingmask)
1275 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1276 } else {
1277 /* Only value/mask trigger. */
1278 lut->m3 = 0xffff;
1279 }
1280
1281 /* Triggertype: event. */
1282 lut->params.selres = 3;
1283
1284 return SR_OK;
1285}
1286
1287static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1288 void *cb_data)
1289{
1290 struct dev_context *devc;
1291 struct sr_datafeed_packet *packet;
1292 struct sr_datafeed_header *header;
1293 struct sr_datafeed_meta_logic meta;
1294 struct clockselect_50 clockselect;
1295 int frac, triggerpin, ret;
1296 uint8_t triggerselect;
1297 struct triggerinout triggerinout_conf;
1298 struct triggerlut lut;
1299
1300 devc = sdi->priv;
1301
1302 if (configure_probes(sdi) != SR_OK) {
1303 sr_err("asix-sigma: failed to configured probes");
1304 return SR_ERR;
1305 }
1306
1307 /* If the samplerate has not been set, default to 200 kHz. */
1308 if (devc->cur_firmware == -1) {
1309 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1310 return ret;
1311 }
1312
1313 /* Enter trigger programming mode. */
1314 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1315
1316 /* 100 and 200 MHz mode. */
1317 if (devc->cur_samplerate >= SR_MHZ(100)) {
1318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1319
1320 /* Find which pin to trigger on from mask. */
1321 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1322 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1323 (1 << triggerpin))
1324 break;
1325
1326 /* Set trigger pin and light LED on trigger. */
1327 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1328
1329 /* Default rising edge. */
1330 if (devc->trigger.fallingmask)
1331 triggerselect |= 1 << 3;
1332
1333 /* All other modes. */
1334 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1335 build_basic_trigger(&lut, devc);
1336
1337 sigma_write_trigger_lut(&lut, devc);
1338
1339 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1340 }
1341
1342 /* Setup trigger in and out pins to default values. */
1343 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1344 triggerinout_conf.trgout_bytrigger = 1;
1345 triggerinout_conf.trgout_enable = 1;
1346
1347 sigma_write_register(WRITE_TRIGGER_OPTION,
1348 (uint8_t *) &triggerinout_conf,
1349 sizeof(struct triggerinout), devc);
1350
1351 /* Go back to normal mode. */
1352 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1353
1354 /* Set clock select register. */
1355 if (devc->cur_samplerate == SR_MHZ(200))
1356 /* Enable 4 probes. */
1357 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1358 else if (devc->cur_samplerate == SR_MHZ(100))
1359 /* Enable 8 probes. */
1360 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1361 else {
1362 /*
1363 * 50 MHz mode (or fraction thereof). Any fraction down to
1364 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1365 */
1366 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1367
1368 clockselect.async = 0;
1369 clockselect.fraction = frac;
1370 clockselect.disabled_probes = 0;
1371
1372 sigma_write_register(WRITE_CLOCK_SELECT,
1373 (uint8_t *) &clockselect,
1374 sizeof(clockselect), devc);
1375 }
1376
1377 /* Setup maximum post trigger time. */
1378 sigma_set_register(WRITE_POST_TRIGGER,
1379 (devc->capture_ratio * 255) / 100, devc);
1380
1381 /* Start acqusition. */
1382 gettimeofday(&devc->start_tv, 0);
1383 sigma_set_register(WRITE_MODE, 0x0d, devc);
1384
1385 devc->session_dev_id = cb_data;
1386
1387 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1388 sr_err("sigma: %s: packet malloc failed.", __func__);
1389 return SR_ERR_MALLOC;
1390 }
1391
1392 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1393 sr_err("sigma: %s: header malloc failed.", __func__);
1394 return SR_ERR_MALLOC;
1395 }
1396
1397 /* Send header packet to the session bus. */
1398 packet->type = SR_DF_HEADER;
1399 packet->payload = header;
1400 header->feed_version = 1;
1401 gettimeofday(&header->starttime, NULL);
1402 sr_session_send(devc->session_dev_id, packet);
1403
1404 /* Send metadata about the SR_DF_LOGIC packets to come. */
1405 packet->type = SR_DF_META_LOGIC;
1406 packet->payload = &meta;
1407 meta.samplerate = devc->cur_samplerate;
1408 meta.num_probes = devc->num_probes;
1409 sr_session_send(devc->session_dev_id, packet);
1410
1411 /* Add capture source. */
1412 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1413
1414 g_free(header);
1415 g_free(packet);
1416
1417 devc->state.state = SIGMA_CAPTURE;
1418
1419 return SR_OK;
1420}
1421
1422static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1423 void *cb_data)
1424{
1425 struct dev_context *devc;
1426 uint8_t modestatus;
1427
1428 /* Avoid compiler warnings. */
1429 (void)cb_data;
1430
1431 sr_source_remove(0);
1432
1433 if (!(devc = sdi->priv)) {
1434 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1435 return SR_ERR_BUG;
1436 }
1437
1438 /* Stop acquisition. */
1439 sigma_set_register(WRITE_MODE, 0x11, devc);
1440
1441 /* Set SDRAM Read Enable. */
1442 sigma_set_register(WRITE_MODE, 0x02, devc);
1443
1444 /* Get the current position. */
1445 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1446
1447 /* Check if trigger has fired. */
1448 modestatus = sigma_get_register(READ_MODE, devc);
1449 if (modestatus & 0x20)
1450 devc->state.triggerchunk = devc->state.triggerpos / 512;
1451 else
1452 devc->state.triggerchunk = -1;
1453
1454 devc->state.chunks_downloaded = 0;
1455
1456 devc->state.state = SIGMA_DOWNLOAD;
1457
1458 return SR_OK;
1459}
1460
1461SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1462 .name = "asix-sigma",
1463 .longname = "ASIX SIGMA/SIGMA2",
1464 .api_version = 1,
1465 .init = hw_init,
1466 .cleanup = hw_cleanup,
1467 .scan = hw_scan,
1468 .dev_list = hw_dev_list,
1469 .dev_clear = clear_instances,
1470 .dev_open = hw_dev_open,
1471 .dev_close = hw_dev_close,
1472 .info_get = hw_info_get,
1473 .dev_config_set = hw_dev_config_set,
1474 .dev_acquisition_start = hw_dev_acquisition_start,
1475 .dev_acquisition_stop = hw_dev_acquisition_stop,
1476 .priv = NULL,
1477};
Hardware access and backend lib