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Commit | Line | Data |
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75521c9b GS |
1 | ------------------------------------------------------------------------------- |
2 | UART traffic, 5-9 data bits, counter values in data bits | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a collection of example UART communication (TX only). The | |
6 | data bits in the UART frame contain numeric values from a counter. | |
7 | There are dumps for various numbers of data bits in the UART frames. | |
8 | ||
9 | ||
10 | Logic analyzer setup | |
11 | -------------------- | |
12 | ||
13 | The capture was taken with an ASIX Sigma2 logic analyzer at a sample | |
14 | rate of 500kHz. The first three channels were enabled: | |
15 | ||
16 | Probe UART | |
17 | ---------------- | |
18 | 1 UART TX (counter values) | |
19 | 2 UART RX (always idle) | |
20 | 3 high for active UART frames | |
21 | ||
22 | ||
23 | Data | |
24 | ---- | |
25 | ||
26 | The hardware sending the data is an Atmel ATmega328P. The bitrate is | |
27 | always 19200, the frame format is 5n1, 6n1, 7n1, 8n1, 9n1 respectively. | |
28 | ||
29 | There is a pause between each UART frame (idle TX line for a few hundred | |
30 | microseconds), such that decoders will immediately "lock in" to the | |
31 | content, and manual inspection is simplified. | |
32 | ||
33 | Capture was arranged such that at least one full counter period is | |
34 | covered and all possible data bit patterns are seen. | |
35 | ||
36 | The ATmega firmware asserts a GPIO line when a UART frame is being | |
37 | sent. This is not essential for UART communication, but again is useful | |
38 | for human inspection, and verification of protocol decoders. |