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c463dcf0 MC |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
fec7aa6a MC |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
c463dcf0 MC |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
15abcf0f MC |
23 | #include <stdint.h> |
24 | #include <string.h> | |
25 | #include <glib.h> | |
26 | #include <glib/gstdio.h> | |
27 | #include <stdio.h> | |
28 | #include <errno.h> | |
29 | #include <math.h> | |
c1aae900 | 30 | #include <libsigrok/libsigrok.h> |
15abcf0f | 31 | #include "libsigrok-internal.h" |
515ab088 | 32 | #include "protocol.h" |
15abcf0f | 33 | |
8e2d6c9d DE |
34 | #define FPGA_FIRMWARE_18 "saleae-logic16-fpga-18.bitstream" |
35 | #define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream" | |
15abcf0f | 36 | |
7b5daad4 MC |
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) |
38 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
39 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
40 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
41 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
42 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
43 | ||
44 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
45 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
46 | ||
15abcf0f MC |
47 | #define COMMAND_START_ACQUISITION 1 |
48 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
49 | #define COMMAND_WRITE_EEPROM 6 | |
50 | #define COMMAND_READ_EEPROM 7 | |
51 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
52 | #define COMMAND_SET_LED_MODE 0x7b | |
53 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
54 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
55 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
56 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
57 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
58 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
59 | #define COMMAND_GET_REVID 0x82 | |
60 | ||
61 | #define WRITE_EEPROM_COOKIE1 0x42 | |
62 | #define WRITE_EEPROM_COOKIE2 0x55 | |
63 | #define READ_EEPROM_COOKIE1 0x33 | |
64 | #define READ_EEPROM_COOKIE2 0x81 | |
65 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
66 | ||
7b5daad4 MC |
67 | #define MAX_EMPTY_TRANSFERS 64 |
68 | ||
c8681396 MC |
69 | /* Register mappings for old and new bitstream versions */ |
70 | ||
71 | enum fpga_register_id { | |
72 | FPGA_REGISTER_VERSION, | |
73 | FPGA_REGISTER_STATUS_CONTROL, | |
74 | FPGA_REGISTER_CHANNEL_SELECT_LOW, | |
75 | FPGA_REGISTER_CHANNEL_SELECT_HIGH, | |
76 | FPGA_REGISTER_SAMPLE_RATE_DIVISOR, | |
77 | FPGA_REGISTER_LED_BRIGHTNESS, | |
78 | FPGA_REGISTER_PRIMER_DATA1, | |
79 | FPGA_REGISTER_PRIMER_CONTROL, | |
80 | FPGA_REGISTER_MODE, | |
81 | FPGA_REGISTER_PRIMER_DATA2, | |
82 | FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2 | |
83 | }; | |
84 | ||
85 | enum fpga_status_control_bit { | |
86 | FPGA_STATUS_CONTROL_BIT_RUNNING, | |
87 | FPGA_STATUS_CONTROL_BIT_UPDATE, | |
88 | FPGA_STATUS_CONTROL_BIT_UNKNOWN1, | |
89 | FPGA_STATUS_CONTROL_BIT_OVERFLOW, | |
90 | FPGA_STATUS_CONTROL_BIT_UNKNOWN2, | |
91 | FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2 | |
92 | }; | |
93 | ||
94 | enum fpga_mode_bit { | |
95 | FPGA_MODE_BIT_CLOCK, | |
96 | FPGA_MODE_BIT_UNKNOWN1, | |
97 | FPGA_MODE_BIT_UNKNOWN2, | |
98 | FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2 | |
99 | }; | |
100 | ||
101 | static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = { | |
102 | [FPGA_REGISTER_VERSION] = 0, | |
103 | [FPGA_REGISTER_STATUS_CONTROL] = 1, | |
104 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2, | |
105 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3, | |
106 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4, | |
107 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
108 | [FPGA_REGISTER_PRIMER_DATA1] = 6, | |
109 | [FPGA_REGISTER_PRIMER_CONTROL] = 7, | |
110 | [FPGA_REGISTER_MODE] = 10, | |
111 | [FPGA_REGISTER_PRIMER_DATA2] = 12, | |
112 | }; | |
113 | ||
114 | static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = { | |
115 | [FPGA_REGISTER_VERSION] = 7, | |
116 | [FPGA_REGISTER_STATUS_CONTROL] = 15, | |
117 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1, | |
118 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6, | |
119 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11, | |
120 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
121 | [FPGA_REGISTER_PRIMER_DATA1] = 14, | |
122 | [FPGA_REGISTER_PRIMER_CONTROL] = 2, | |
123 | [FPGA_REGISTER_MODE] = 4, | |
124 | [FPGA_REGISTER_PRIMER_DATA2] = 3, | |
125 | }; | |
126 | ||
127 | static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
128 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01, | |
129 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02, | |
130 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08, | |
131 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20, | |
132 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40, | |
133 | }; | |
134 | ||
135 | static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
136 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20, | |
137 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08, | |
138 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10, | |
139 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01, | |
140 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04, | |
141 | }; | |
142 | ||
143 | static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = { | |
144 | [FPGA_MODE_BIT_CLOCK] = 0x01, | |
145 | [FPGA_MODE_BIT_UNKNOWN1] = 0x40, | |
146 | [FPGA_MODE_BIT_UNKNOWN2] = 0x80, | |
147 | }; | |
148 | ||
149 | static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = { | |
150 | [FPGA_MODE_BIT_CLOCK] = 0x04, | |
151 | [FPGA_MODE_BIT_UNKNOWN1] = 0x80, | |
152 | [FPGA_MODE_BIT_UNKNOWN2] = 0x01, | |
153 | }; | |
154 | ||
155 | #define FPGA_REG(x) \ | |
156 | (devc->fpga_register_map[FPGA_REGISTER_ ## x]) | |
157 | ||
158 | #define FPGA_STATUS_CONTROL(x) \ | |
159 | (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x]) | |
160 | ||
161 | #define FPGA_MODE(x) \ | |
162 | (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x]) | |
163 | ||
15abcf0f MC |
164 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) |
165 | { | |
166 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 167 | uint8_t t, v; |
15abcf0f MC |
168 | int i; |
169 | ||
96484e22 UH |
170 | for (i = 0; i < cnt; i++) { |
171 | v = src[i]; | |
15abcf0f MC |
172 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; |
173 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
174 | dest[i] = state2 = t; | |
175 | state1 = v; | |
176 | } | |
177 | } | |
178 | ||
179 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
180 | { | |
181 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 182 | uint8_t t, v; |
15abcf0f | 183 | int i; |
96484e22 UH |
184 | |
185 | for (i = 0; i < cnt; i++) { | |
186 | v = src[i]; | |
15abcf0f MC |
187 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; |
188 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
189 | dest[i] = state1 = t; | |
190 | state2 = v; | |
191 | } | |
192 | } | |
193 | ||
194 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
195 | const uint8_t *command, uint8_t cmd_len, | |
196 | uint8_t *reply, uint8_t reply_len) | |
197 | { | |
198 | uint8_t buf[64]; | |
199 | struct sr_usb_dev_inst *usb; | |
200 | int ret, xfer; | |
201 | ||
202 | usb = sdi->conn; | |
203 | ||
204 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
98fec29e | 205 | !command || (reply_len > 0 && !reply)) |
15abcf0f MC |
206 | return SR_ERR_ARG; |
207 | ||
208 | encrypt(buf, command, cmd_len); | |
209 | ||
210 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
211 | if (ret != 0) { | |
96484e22 | 212 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", |
15abcf0f MC |
213 | command[0], libusb_error_name(ret)); |
214 | return SR_ERR; | |
215 | } | |
216 | if (xfer != cmd_len) { | |
96484e22 | 217 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " |
6433156c | 218 | "%d != %d.", command[0], xfer, cmd_len); |
15abcf0f MC |
219 | return SR_ERR; |
220 | } | |
221 | ||
222 | if (reply_len == 0) | |
223 | return SR_OK; | |
224 | ||
96484e22 UH |
225 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, |
226 | &xfer, 1000); | |
15abcf0f | 227 | if (ret != 0) { |
96484e22 | 228 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", |
15abcf0f MC |
229 | command[0], libusb_error_name(ret)); |
230 | return SR_ERR; | |
231 | } | |
232 | if (xfer != reply_len) { | |
96484e22 | 233 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " |
6433156c | 234 | "incorrect length %d != %d.", command[0], xfer, reply_len); |
15abcf0f MC |
235 | return SR_ERR; |
236 | } | |
237 | ||
238 | decrypt(reply, buf, reply_len); | |
239 | ||
240 | return SR_OK; | |
241 | } | |
242 | ||
243 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
244 | uint8_t address, uint8_t length, uint8_t *buf) | |
245 | { | |
246 | uint8_t command[5] = { | |
247 | COMMAND_READ_EEPROM, | |
248 | READ_EEPROM_COOKIE1, | |
249 | READ_EEPROM_COOKIE2, | |
250 | address, | |
251 | length, | |
252 | }; | |
253 | ||
254 | return do_ep1_command(sdi, command, 5, buf, length); | |
255 | } | |
256 | ||
257 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
258 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
259 | { | |
96484e22 | 260 | uint8_t chunk, command[64]; |
15abcf0f MC |
261 | int ret; |
262 | ||
98fec29e | 263 | if (cnt < 1 || cnt + offset > 64 || !table) |
15abcf0f MC |
264 | return SR_ERR_ARG; |
265 | ||
266 | while (cnt > 0) { | |
96484e22 | 267 | chunk = (cnt > 32 ? 32 : cnt); |
15abcf0f MC |
268 | |
269 | command[0] = COMMAND_WRITE_LED_TABLE; | |
270 | command[1] = offset; | |
271 | command[2] = chunk; | |
96484e22 | 272 | memcpy(command + 3, table, chunk); |
15abcf0f | 273 | |
96484e22 UH |
274 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); |
275 | if (ret != SR_OK) | |
15abcf0f MC |
276 | return ret; |
277 | ||
278 | table += chunk; | |
279 | offset += chunk; | |
280 | cnt -= chunk; | |
281 | } | |
282 | ||
283 | return SR_OK; | |
284 | } | |
285 | ||
286 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
287 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
288 | uint8_t repeat) | |
289 | { | |
290 | uint8_t command[6] = { | |
291 | COMMAND_SET_LED_MODE, | |
292 | animate, | |
96484e22 UH |
293 | t2reload & 0xff, |
294 | t2reload >> 8, | |
15abcf0f MC |
295 | div, |
296 | repeat, | |
297 | }; | |
298 | ||
299 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
300 | } | |
301 | ||
302 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
303 | uint8_t address, uint8_t *value) | |
304 | { | |
305 | uint8_t command[3] = { | |
306 | COMMAND_FPGA_READ_REGISTER, | |
307 | 1, | |
308 | address, | |
309 | }; | |
310 | ||
311 | return do_ep1_command(sdi, command, 3, value, 1); | |
312 | } | |
313 | ||
314 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
315 | uint8_t (*regs)[2], uint8_t cnt) | |
316 | { | |
317 | uint8_t command[64]; | |
318 | int i; | |
319 | ||
320 | if (cnt < 1 || cnt > 31) | |
321 | return SR_ERR_ARG; | |
322 | ||
323 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
324 | command[1] = cnt; | |
96484e22 UH |
325 | for (i = 0; i < cnt; i++) { |
326 | command[2 + 2 * i] = regs[i][0]; | |
327 | command[3 + 2 * i] = regs[i][1]; | |
15abcf0f MC |
328 | } |
329 | ||
96484e22 | 330 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); |
15abcf0f MC |
331 | } |
332 | ||
333 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
334 | uint8_t address, uint8_t value) | |
335 | { | |
336 | uint8_t regs[2] = { address, value }; | |
96484e22 | 337 | |
15abcf0f MC |
338 | return write_fpga_registers(sdi, ®s, 1); |
339 | } | |
340 | ||
15abcf0f MC |
341 | static uint8_t map_eeprom_data(uint8_t v) |
342 | { | |
186dde8d | 343 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; |
15abcf0f MC |
344 | } |
345 | ||
c8681396 MC |
346 | static int setup_register_mapping(const struct sr_dev_inst *sdi) |
347 | { | |
348 | struct dev_context *devc; | |
349 | int ret; | |
350 | ||
351 | devc = sdi->priv; | |
352 | ||
353 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
354 | uint8_t reg0, reg7; | |
355 | ||
356 | /* | |
357 | * Check for newer bitstream version by polling the | |
358 | * version register at the old and new location. | |
359 | */ | |
360 | ||
361 | if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK) | |
362 | return ret; | |
363 | ||
364 | if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK) | |
365 | return ret; | |
366 | ||
84ab9da1 UH |
367 | if (reg0 == 0 && reg7 > 0x10) { |
368 | sr_info("Original Saleae Logic16 using new bitstream."); | |
c8681396 | 369 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM; |
84ab9da1 UH |
370 | } else { |
371 | sr_info("Original Saleae Logic16 using old bitstream."); | |
c8681396 | 372 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; |
84ab9da1 | 373 | } |
c8681396 MC |
374 | } |
375 | ||
376 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) { | |
377 | devc->fpga_register_map = fpga_register_map_new; | |
378 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new; | |
379 | devc->fpga_mode_bit_map = fpga_mode_bit_map_new; | |
380 | } else { | |
381 | devc->fpga_register_map = fpga_register_map_old; | |
382 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old; | |
383 | devc->fpga_mode_bit_map = fpga_mode_bit_map_old; | |
384 | } | |
385 | ||
386 | return SR_OK; | |
387 | } | |
388 | ||
15abcf0f MC |
389 | static int prime_fpga(const struct sr_dev_inst *sdi) |
390 | { | |
c8681396 | 391 | struct dev_context *devc = sdi->priv; |
15abcf0f | 392 | uint8_t eeprom_data[16]; |
c8681396 | 393 | uint8_t old_mode_reg, version; |
15abcf0f | 394 | uint8_t regs[8][2] = { |
c8681396 MC |
395 | {FPGA_REG(MODE), 0x00}, |
396 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
397 | {FPGA_REG(PRIMER_DATA2), 0}, | |
398 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)}, | |
399 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
400 | {FPGA_REG(PRIMER_DATA1), 0}, | |
401 | {FPGA_REG(PRIMER_CONTROL), 1}, | |
402 | {FPGA_REG(PRIMER_CONTROL), 0} | |
15abcf0f MC |
403 | }; |
404 | int i, ret; | |
405 | ||
406 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
407 | return ret; | |
408 | ||
c8681396 | 409 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK) |
15abcf0f MC |
410 | return ret; |
411 | ||
c8681396 MC |
412 | regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2)); |
413 | regs[1][1] |= old_mode_reg; | |
414 | regs[3][1] |= old_mode_reg; | |
415 | regs[4][1] |= old_mode_reg; | |
186dde8d | 416 | |
96484e22 | 417 | for (i = 0; i < 16; i++) { |
15abcf0f MC |
418 | regs[2][1] = eeprom_data[i]; |
419 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
420 | if (i) | |
421 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
422 | else | |
423 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
424 | if (ret != SR_OK) | |
425 | return ret; | |
426 | } | |
427 | ||
c8681396 | 428 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK) |
15abcf0f MC |
429 | return ret; |
430 | ||
c8681396 | 431 | if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK) |
15abcf0f MC |
432 | return ret; |
433 | ||
c8681396 | 434 | if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) { |
6f479a0a | 435 | sr_err("Unsupported FPGA version: 0x%02x.", version); |
15abcf0f MC |
436 | return SR_ERR; |
437 | } | |
438 | ||
439 | return SR_OK; | |
440 | } | |
441 | ||
442 | static void make_heartbeat(uint8_t *table, int len) | |
443 | { | |
444 | int i, j; | |
445 | ||
446 | memset(table, 0, len); | |
447 | len >>= 3; | |
96484e22 UH |
448 | for (i = 0; i < 2; i++) |
449 | for (j = 0; j < len; j++) | |
bbc42811 | 450 | *table++ = sin(j * G_PI / len) * 255; |
15abcf0f MC |
451 | } |
452 | ||
453 | static int configure_led(const struct sr_dev_inst *sdi) | |
454 | { | |
455 | uint8_t table[64]; | |
456 | int ret; | |
457 | ||
458 | make_heartbeat(table, 64); | |
459 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
460 | return ret; | |
461 | ||
462 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
463 | } | |
464 | ||
465 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
466 | enum voltage_range vrange) | |
467 | { | |
8e2d6c9d DE |
468 | uint64_t sum; |
469 | struct sr_resource bitstream; | |
15abcf0f | 470 | struct dev_context *devc; |
8e2d6c9d DE |
471 | struct drv_context *drvc; |
472 | const char *name; | |
473 | ssize_t chunksize; | |
474 | int ret; | |
475 | uint8_t command[64]; | |
15abcf0f MC |
476 | |
477 | devc = sdi->priv; | |
8e2d6c9d | 478 | drvc = sdi->driver->context; |
15abcf0f MC |
479 | |
480 | if (devc->cur_voltage_range == vrange) | |
481 | return SR_OK; | |
482 | ||
c8681396 | 483 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { |
6f479a0a PZ |
484 | switch (vrange) { |
485 | case VOLTAGE_RANGE_18_33_V: | |
8e2d6c9d | 486 | name = FPGA_FIRMWARE_18; |
6f479a0a PZ |
487 | break; |
488 | case VOLTAGE_RANGE_5_V: | |
8e2d6c9d | 489 | name = FPGA_FIRMWARE_33; |
6f479a0a PZ |
490 | break; |
491 | default: | |
492 | sr_err("Unsupported voltage range."); | |
493 | return SR_ERR; | |
494 | } | |
15abcf0f | 495 | |
8e2d6c9d DE |
496 | sr_info("Uploading FPGA bitstream '%s'.", name); |
497 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, | |
498 | SR_RESOURCE_FIRMWARE, name); | |
499 | if (ret != SR_OK) | |
500 | return ret; | |
15abcf0f | 501 | |
8e2d6c9d DE |
502 | command[0] = COMMAND_FPGA_UPLOAD_INIT; |
503 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) { | |
504 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
6f479a0a PZ |
505 | return ret; |
506 | } | |
15abcf0f | 507 | |
8e2d6c9d | 508 | sum = 0; |
6f479a0a | 509 | while (1) { |
8e2d6c9d DE |
510 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, |
511 | &command[2], sizeof(command) - 2); | |
512 | if (chunksize < 0) { | |
513 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
514 | return SR_ERR; | |
515 | } | |
6f479a0a PZ |
516 | if (chunksize == 0) |
517 | break; | |
8e2d6c9d DE |
518 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; |
519 | command[1] = chunksize; | |
520 | ||
521 | ret = do_ep1_command(sdi, command, chunksize + 2, | |
522 | NULL, 0); | |
523 | if (ret != SR_OK) { | |
524 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
525 | return ret; | |
15abcf0f | 526 | } |
8e2d6c9d | 527 | sum += chunksize; |
6f479a0a | 528 | } |
8e2d6c9d DE |
529 | sr_resource_close(drvc->sr_ctx, &bitstream); |
530 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum); | |
15abcf0f | 531 | } |
15abcf0f | 532 | |
c8681396 MC |
533 | /* This needs to be called before accessing any FPGA registers. */ |
534 | if ((ret = setup_register_mapping(sdi)) != SR_OK) | |
535 | return ret; | |
536 | ||
15abcf0f MC |
537 | if ((ret = prime_fpga(sdi)) != SR_OK) |
538 | return ret; | |
539 | ||
540 | if ((ret = configure_led(sdi)) != SR_OK) | |
541 | return ret; | |
542 | ||
15abcf0f MC |
543 | devc->cur_voltage_range = vrange; |
544 | return SR_OK; | |
545 | } | |
546 | ||
7b5daad4 | 547 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) |
15abcf0f MC |
548 | { |
549 | static const uint8_t command[2] = { | |
550 | COMMAND_ABORT_ACQUISITION_SYNC, | |
551 | ABORT_ACQUISITION_SYNC_PATTERN, | |
552 | }; | |
553 | uint8_t reply, expected_reply; | |
554 | int ret; | |
555 | ||
556 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
557 | return ret; | |
558 | ||
559 | expected_reply = ~command[1]; | |
560 | if (reply != expected_reply) { | |
561 | sr_err("Invalid response for abort acquisition command: " | |
96484e22 | 562 | "0x%02x != 0x%02x.", reply, expected_reply); |
15abcf0f MC |
563 | return SR_ERR; |
564 | } | |
565 | ||
566 | return SR_OK; | |
567 | } | |
568 | ||
96484e22 UH |
569 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, |
570 | uint64_t samplerate, uint16_t channels) | |
7b5daad4 | 571 | { |
c8681396 | 572 | uint8_t clock_select, sta_con_reg, mode_reg; |
7b5daad4 MC |
573 | uint64_t div; |
574 | int i, ret, nchan = 0; | |
db11d7d2 MC |
575 | struct dev_context *devc; |
576 | ||
577 | devc = sdi->priv; | |
7b5daad4 MC |
578 | |
579 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
580 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
581 | return SR_ERR; | |
582 | } | |
583 | ||
584 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
585 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
586 | clock_select = 0; | |
587 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
588 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
589 | clock_select = 1; | |
590 | } else { | |
591 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
592 | return SR_ERR; | |
593 | } | |
594 | ||
96484e22 UH |
595 | for (i = 0; i < 16; i++) |
596 | if (channels & (1U << i)) | |
7b5daad4 MC |
597 | nchan++; |
598 | ||
599 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
600 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
601 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
602 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
603 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
604 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
605 | "with this many channels.", samplerate); | |
606 | return SR_ERR; | |
607 | } | |
608 | ||
96484e22 UH |
609 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
610 | if (ret != SR_OK) | |
db11d7d2 MC |
611 | return ret; |
612 | ||
c8681396 | 613 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
614 | return ret; |
615 | ||
7754fb4d | 616 | /* Ignore FIFO overflow on previous capture */ |
c8681396 | 617 | sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW); |
7754fb4d | 618 | |
c8681396 MC |
619 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
620 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
621 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
622 | } |
623 | ||
c8681396 | 624 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
625 | return ret; |
626 | ||
c8681396 | 627 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK) |
7b5daad4 MC |
628 | return ret; |
629 | ||
c8681396 | 630 | if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK) |
7b5daad4 MC |
631 | return ret; |
632 | ||
c8681396 | 633 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK) |
7b5daad4 MC |
634 | return ret; |
635 | ||
c8681396 | 636 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK) |
7b5daad4 MC |
637 | return ret; |
638 | ||
c8681396 | 639 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK) |
7b5daad4 MC |
640 | return ret; |
641 | ||
c8681396 | 642 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
643 | return ret; |
644 | ||
c8681396 | 645 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
646 | return ret; |
647 | ||
c8681396 MC |
648 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) { |
649 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
650 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
651 | } |
652 | ||
c8681396 | 653 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK) |
7b5daad4 MC |
654 | return ret; |
655 | ||
c8681396 | 656 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) { |
a11e10ec | 657 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " |
c8681396 | 658 | "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0)); |
7b5daad4 MC |
659 | } |
660 | ||
661 | return SR_OK; | |
662 | } | |
663 | ||
96484e22 | 664 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
665 | { |
666 | static const uint8_t command[1] = { | |
667 | COMMAND_START_ACQUISITION, | |
668 | }; | |
669 | int ret; | |
c8681396 MC |
670 | struct dev_context *devc; |
671 | ||
672 | devc = sdi->priv; | |
7b5daad4 MC |
673 | |
674 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
675 | return ret; | |
676 | ||
c8681396 | 677 | return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING)); |
7b5daad4 MC |
678 | } |
679 | ||
96484e22 | 680 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
681 | { |
682 | static const uint8_t command[1] = { | |
683 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
684 | }; | |
685 | int ret; | |
c8681396 | 686 | uint8_t sta_con_reg; |
6f479a0a PZ |
687 | struct dev_context *devc; |
688 | ||
689 | devc = sdi->priv; | |
7b5daad4 MC |
690 | |
691 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
692 | return ret; | |
693 | ||
c8681396 | 694 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK) |
7b5daad4 MC |
695 | return ret; |
696 | ||
c8681396 | 697 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
698 | return ret; |
699 | ||
c8681396 MC |
700 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
701 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
702 | return SR_ERR; |
703 | } | |
704 | ||
7b5daad4 | 705 | |
c8681396 MC |
706 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { |
707 | uint8_t reg8, reg9; | |
708 | ||
709 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
710 | return ret; | |
711 | ||
712 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
713 | return ret; | |
714 | } | |
7b5daad4 | 715 | |
c8681396 | 716 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) { |
7754fb4d MC |
717 | sr_warn("FIFO overflow, capture data may be truncated."); |
718 | return SR_ERR; | |
719 | } | |
720 | ||
7b5daad4 MC |
721 | return SR_OK; |
722 | } | |
723 | ||
96484e22 | 724 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) |
15abcf0f | 725 | { |
6f479a0a | 726 | uint8_t version; |
15abcf0f MC |
727 | struct dev_context *devc; |
728 | int ret; | |
729 | ||
730 | devc = sdi->priv; | |
731 | ||
732 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
733 | ||
7b5daad4 | 734 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) |
15abcf0f MC |
735 | return ret; |
736 | ||
737 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
738 | return ret; | |
739 | ||
6f479a0a PZ |
740 | /* mcupro Saleae16 has firmware pre-stored in FPGA. |
741 | So, we can query it right away. */ | |
c8681396 | 742 | if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK && |
6f479a0a PZ |
743 | (version == 0x40 || version == 0x41)) { |
744 | sr_info("mcupro Saleae16 detected."); | |
745 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
746 | } else { | |
747 | sr_info("Original Saleae Logic16 detected."); | |
748 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
749 | } | |
750 | ||
96484e22 UH |
751 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
752 | if (ret != SR_OK) | |
15abcf0f MC |
753 | return ret; |
754 | ||
755 | return SR_OK; | |
756 | } | |
757 | ||
102f1239 | 758 | static void finish_acquisition(struct sr_dev_inst *sdi) |
7b5daad4 | 759 | { |
102f1239 BV |
760 | struct dev_context *devc; |
761 | ||
762 | devc = sdi->priv; | |
7b5daad4 | 763 | |
3be42bc2 | 764 | std_session_send_df_end(sdi, LOG_PREFIX); |
7b5daad4 MC |
765 | |
766 | /* Remove fds from polling. */ | |
102f1239 | 767 | usb_source_remove(sdi->session, devc->ctx); |
7b5daad4 MC |
768 | |
769 | devc->num_transfers = 0; | |
770 | g_free(devc->transfers); | |
771 | g_free(devc->convbuffer); | |
863357fb BV |
772 | if (devc->stl) { |
773 | soft_trigger_logic_free(devc->stl); | |
774 | devc->stl = NULL; | |
775 | } | |
7b5daad4 MC |
776 | } |
777 | ||
778 | static void free_transfer(struct libusb_transfer *transfer) | |
779 | { | |
102f1239 | 780 | struct sr_dev_inst *sdi; |
7b5daad4 MC |
781 | struct dev_context *devc; |
782 | unsigned int i; | |
783 | ||
102f1239 BV |
784 | sdi = transfer->user_data; |
785 | devc = sdi->priv; | |
7b5daad4 MC |
786 | |
787 | g_free(transfer->buffer); | |
788 | transfer->buffer = NULL; | |
789 | libusb_free_transfer(transfer); | |
790 | ||
791 | for (i = 0; i < devc->num_transfers; i++) { | |
792 | if (devc->transfers[i] == transfer) { | |
793 | devc->transfers[i] = NULL; | |
794 | break; | |
795 | } | |
796 | } | |
797 | ||
798 | devc->submitted_transfers--; | |
799 | if (devc->submitted_transfers == 0) | |
102f1239 | 800 | finish_acquisition(sdi); |
7b5daad4 MC |
801 | } |
802 | ||
803 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
804 | { | |
805 | int ret; | |
806 | ||
807 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
808 | return; | |
809 | ||
810 | free_transfer(transfer); | |
811 | /* TODO: Stop session? */ | |
812 | ||
813 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
814 | } | |
815 | ||
a989cdbe BV |
816 | static size_t convert_sample_data(struct dev_context *devc, |
817 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
c463dcf0 | 818 | { |
7b5daad4 MC |
819 | uint16_t *channel_data; |
820 | int i, cur_channel; | |
821 | size_t ret = 0; | |
96484e22 | 822 | uint16_t sample, channel_mask; |
7b5daad4 MC |
823 | |
824 | srccnt /= 2; | |
825 | ||
826 | channel_data = devc->channel_data; | |
827 | cur_channel = devc->cur_channel; | |
828 | ||
96484e22 | 829 | while (srccnt--) { |
7b5daad4 MC |
830 | sample = src[0] | (src[1] << 8); |
831 | src += 2; | |
832 | ||
833 | channel_mask = devc->channel_masks[cur_channel]; | |
834 | ||
96484e22 | 835 | for (i = 15; i >= 0; --i, sample >>= 1) |
7b5daad4 MC |
836 | if (sample & 1) |
837 | channel_data[i] |= channel_mask; | |
838 | ||
839 | if (++cur_channel == devc->num_channels) { | |
840 | cur_channel = 0; | |
96484e22 | 841 | if (destcnt < 16 * 2) { |
7b5daad4 MC |
842 | sr_err("Conversion buffer too small!"); |
843 | break; | |
844 | } | |
96484e22 UH |
845 | memcpy(dest, channel_data, 16 * 2); |
846 | memset(channel_data, 0, 16 * 2); | |
847 | dest += 16 * 2; | |
1b822521 | 848 | ret += 16; |
96484e22 | 849 | destcnt -= 16 * 2; |
7b5daad4 MC |
850 | } |
851 | } | |
852 | ||
853 | devc->cur_channel = cur_channel; | |
c463dcf0 | 854 | |
7b5daad4 MC |
855 | return ret; |
856 | } | |
857 | ||
55462b8b | 858 | SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) |
7b5daad4 MC |
859 | { |
860 | gboolean packet_has_error = FALSE; | |
861 | struct sr_datafeed_packet packet; | |
862 | struct sr_datafeed_logic logic; | |
102f1239 | 863 | struct sr_dev_inst *sdi; |
c463dcf0 | 864 | struct dev_context *devc; |
863357fb BV |
865 | size_t new_samples, num_samples; |
866 | int trigger_offset; | |
5a971f66 | 867 | int pre_trigger_samples; |
7b5daad4 | 868 | |
102f1239 BV |
869 | sdi = transfer->user_data; |
870 | devc = sdi->priv; | |
7b5daad4 MC |
871 | |
872 | /* | |
873 | * If acquisition has already ended, just free any queued up | |
874 | * transfer that come in. | |
875 | */ | |
863357fb | 876 | if (devc->sent_samples < 0) { |
7b5daad4 MC |
877 | free_transfer(transfer); |
878 | return; | |
879 | } | |
880 | ||
974fb0ff BV |
881 | sr_info("receive_transfer(): status %s received %d bytes.", |
882 | libusb_error_name(transfer->status), transfer->actual_length); | |
7b5daad4 MC |
883 | |
884 | switch (transfer->status) { | |
885 | case LIBUSB_TRANSFER_NO_DEVICE: | |
863357fb | 886 | devc->sent_samples = -2; |
7b5daad4 MC |
887 | free_transfer(transfer); |
888 | return; | |
889 | case LIBUSB_TRANSFER_COMPLETED: | |
890 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
891 | break; | |
892 | default: | |
893 | packet_has_error = TRUE; | |
894 | break; | |
895 | } | |
c463dcf0 | 896 | |
7b5daad4 | 897 | if (transfer->actual_length & 1) { |
96484e22 UH |
898 | sr_err("Got an odd number of bytes from the device. " |
899 | "This should not happen."); | |
900 | /* Bail out right away. */ | |
7b5daad4 MC |
901 | packet_has_error = TRUE; |
902 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
903 | } | |
c463dcf0 | 904 | |
7b5daad4 MC |
905 | if (transfer->actual_length == 0 || packet_has_error) { |
906 | devc->empty_transfer_count++; | |
907 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
908 | /* | |
909 | * The FX2 gave up. End the acquisition, the frontend | |
910 | * will work out that the samplecount is short. | |
911 | */ | |
863357fb | 912 | devc->sent_samples = -2; |
7b5daad4 MC |
913 | free_transfer(transfer); |
914 | } else { | |
915 | resubmit_transfer(transfer); | |
916 | } | |
917 | return; | |
918 | } else { | |
919 | devc->empty_transfer_count = 0; | |
920 | } | |
c463dcf0 | 921 | |
863357fb | 922 | new_samples = convert_sample_data(devc, devc->convbuffer, |
a989cdbe | 923 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); |
863357fb BV |
924 | |
925 | if (new_samples > 0) { | |
926 | if (devc->trigger_fired) { | |
927 | /* Send the incoming transfer to the session bus. */ | |
928 | packet.type = SR_DF_LOGIC; | |
929 | packet.payload = &logic; | |
930 | if (devc->limit_samples && | |
931 | new_samples > devc->limit_samples - devc->sent_samples) | |
932 | new_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
933 | logic.length = new_samples * 2; |
934 | logic.unitsize = 2; | |
863357fb BV |
935 | logic.data = devc->convbuffer; |
936 | sr_session_send(devc->cb_data, &packet); | |
937 | devc->sent_samples += new_samples; | |
938 | } else { | |
939 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
5a971f66 | 940 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); |
863357fb | 941 | if (trigger_offset > -1) { |
5a971f66 | 942 | devc->sent_samples += pre_trigger_samples; |
863357fb BV |
943 | packet.type = SR_DF_LOGIC; |
944 | packet.payload = &logic; | |
945 | num_samples = new_samples - trigger_offset; | |
946 | if (devc->limit_samples && | |
947 | num_samples > devc->limit_samples - devc->sent_samples) | |
948 | num_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
949 | logic.length = num_samples * 2; |
950 | logic.unitsize = 2; | |
951 | logic.data = devc->convbuffer + trigger_offset * 2; | |
863357fb BV |
952 | sr_session_send(devc->cb_data, &packet); |
953 | devc->sent_samples += num_samples; | |
954 | ||
955 | devc->trigger_fired = TRUE; | |
956 | } | |
2db95906 MC |
957 | } |
958 | ||
7b5daad4 | 959 | if (devc->limit_samples && |
863357fb BV |
960 | (uint64_t)devc->sent_samples >= devc->limit_samples) { |
961 | devc->sent_samples = -2; | |
7b5daad4 MC |
962 | free_transfer(transfer); |
963 | return; | |
964 | } | |
c463dcf0 MC |
965 | } |
966 | ||
7b5daad4 | 967 | resubmit_transfer(transfer); |
c463dcf0 | 968 | } |