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c463dcf0 MC |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
fec7aa6a MC |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
c463dcf0 MC |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
15abcf0f MC |
23 | #include <stdint.h> |
24 | #include <string.h> | |
25 | #include <glib.h> | |
26 | #include <glib/gstdio.h> | |
27 | #include <stdio.h> | |
28 | #include <errno.h> | |
29 | #include <math.h> | |
c1aae900 | 30 | #include <libsigrok/libsigrok.h> |
15abcf0f | 31 | #include "libsigrok-internal.h" |
515ab088 | 32 | #include "protocol.h" |
15abcf0f | 33 | |
8e2d6c9d DE |
34 | #define FPGA_FIRMWARE_18 "saleae-logic16-fpga-18.bitstream" |
35 | #define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream" | |
15abcf0f | 36 | |
7b5daad4 | 37 | #define MAX_SAMPLE_RATE SR_MHZ(100) |
cb193a20 | 38 | #define MAX_SAMPLE_RATE_X_CH SR_MHZ(300) |
7b5daad4 MC |
39 | |
40 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
41 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
42 | ||
15abcf0f MC |
43 | #define COMMAND_START_ACQUISITION 1 |
44 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
45 | #define COMMAND_WRITE_EEPROM 6 | |
46 | #define COMMAND_READ_EEPROM 7 | |
47 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
48 | #define COMMAND_SET_LED_MODE 0x7b | |
49 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
50 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
51 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
52 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
53 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
54 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
55 | #define COMMAND_GET_REVID 0x82 | |
56 | ||
57 | #define WRITE_EEPROM_COOKIE1 0x42 | |
58 | #define WRITE_EEPROM_COOKIE2 0x55 | |
59 | #define READ_EEPROM_COOKIE1 0x33 | |
60 | #define READ_EEPROM_COOKIE2 0x81 | |
61 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
62 | ||
7b5daad4 MC |
63 | #define MAX_EMPTY_TRANSFERS 64 |
64 | ||
c8681396 MC |
65 | /* Register mappings for old and new bitstream versions */ |
66 | ||
67 | enum fpga_register_id { | |
68 | FPGA_REGISTER_VERSION, | |
69 | FPGA_REGISTER_STATUS_CONTROL, | |
70 | FPGA_REGISTER_CHANNEL_SELECT_LOW, | |
71 | FPGA_REGISTER_CHANNEL_SELECT_HIGH, | |
72 | FPGA_REGISTER_SAMPLE_RATE_DIVISOR, | |
73 | FPGA_REGISTER_LED_BRIGHTNESS, | |
74 | FPGA_REGISTER_PRIMER_DATA1, | |
75 | FPGA_REGISTER_PRIMER_CONTROL, | |
76 | FPGA_REGISTER_MODE, | |
77 | FPGA_REGISTER_PRIMER_DATA2, | |
78 | FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2 | |
79 | }; | |
80 | ||
81 | enum fpga_status_control_bit { | |
82 | FPGA_STATUS_CONTROL_BIT_RUNNING, | |
83 | FPGA_STATUS_CONTROL_BIT_UPDATE, | |
84 | FPGA_STATUS_CONTROL_BIT_UNKNOWN1, | |
85 | FPGA_STATUS_CONTROL_BIT_OVERFLOW, | |
86 | FPGA_STATUS_CONTROL_BIT_UNKNOWN2, | |
87 | FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2 | |
88 | }; | |
89 | ||
90 | enum fpga_mode_bit { | |
91 | FPGA_MODE_BIT_CLOCK, | |
92 | FPGA_MODE_BIT_UNKNOWN1, | |
93 | FPGA_MODE_BIT_UNKNOWN2, | |
94 | FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2 | |
95 | }; | |
96 | ||
97 | static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = { | |
98 | [FPGA_REGISTER_VERSION] = 0, | |
99 | [FPGA_REGISTER_STATUS_CONTROL] = 1, | |
100 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2, | |
101 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3, | |
102 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4, | |
103 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
104 | [FPGA_REGISTER_PRIMER_DATA1] = 6, | |
105 | [FPGA_REGISTER_PRIMER_CONTROL] = 7, | |
106 | [FPGA_REGISTER_MODE] = 10, | |
107 | [FPGA_REGISTER_PRIMER_DATA2] = 12, | |
108 | }; | |
109 | ||
110 | static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = { | |
111 | [FPGA_REGISTER_VERSION] = 7, | |
112 | [FPGA_REGISTER_STATUS_CONTROL] = 15, | |
113 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1, | |
114 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6, | |
115 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11, | |
116 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
117 | [FPGA_REGISTER_PRIMER_DATA1] = 14, | |
118 | [FPGA_REGISTER_PRIMER_CONTROL] = 2, | |
119 | [FPGA_REGISTER_MODE] = 4, | |
120 | [FPGA_REGISTER_PRIMER_DATA2] = 3, | |
121 | }; | |
122 | ||
123 | static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
124 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01, | |
125 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02, | |
126 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08, | |
127 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20, | |
128 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40, | |
129 | }; | |
130 | ||
131 | static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
132 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20, | |
133 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08, | |
134 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10, | |
135 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01, | |
136 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04, | |
137 | }; | |
138 | ||
139 | static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = { | |
140 | [FPGA_MODE_BIT_CLOCK] = 0x01, | |
141 | [FPGA_MODE_BIT_UNKNOWN1] = 0x40, | |
142 | [FPGA_MODE_BIT_UNKNOWN2] = 0x80, | |
143 | }; | |
144 | ||
145 | static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = { | |
146 | [FPGA_MODE_BIT_CLOCK] = 0x04, | |
147 | [FPGA_MODE_BIT_UNKNOWN1] = 0x80, | |
148 | [FPGA_MODE_BIT_UNKNOWN2] = 0x01, | |
149 | }; | |
150 | ||
151 | #define FPGA_REG(x) \ | |
152 | (devc->fpga_register_map[FPGA_REGISTER_ ## x]) | |
153 | ||
154 | #define FPGA_STATUS_CONTROL(x) \ | |
155 | (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x]) | |
156 | ||
157 | #define FPGA_MODE(x) \ | |
158 | (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x]) | |
159 | ||
15abcf0f MC |
160 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) |
161 | { | |
162 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 163 | uint8_t t, v; |
15abcf0f MC |
164 | int i; |
165 | ||
96484e22 UH |
166 | for (i = 0; i < cnt; i++) { |
167 | v = src[i]; | |
15abcf0f MC |
168 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; |
169 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
170 | dest[i] = state2 = t; | |
171 | state1 = v; | |
172 | } | |
173 | } | |
174 | ||
175 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
176 | { | |
177 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 178 | uint8_t t, v; |
15abcf0f | 179 | int i; |
96484e22 UH |
180 | |
181 | for (i = 0; i < cnt; i++) { | |
182 | v = src[i]; | |
15abcf0f MC |
183 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; |
184 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
185 | dest[i] = state1 = t; | |
186 | state2 = v; | |
187 | } | |
188 | } | |
189 | ||
190 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
191 | const uint8_t *command, uint8_t cmd_len, | |
192 | uint8_t *reply, uint8_t reply_len) | |
193 | { | |
194 | uint8_t buf[64]; | |
195 | struct sr_usb_dev_inst *usb; | |
196 | int ret, xfer; | |
197 | ||
198 | usb = sdi->conn; | |
199 | ||
200 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
98fec29e | 201 | !command || (reply_len > 0 && !reply)) |
15abcf0f MC |
202 | return SR_ERR_ARG; |
203 | ||
204 | encrypt(buf, command, cmd_len); | |
205 | ||
206 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
207 | if (ret != 0) { | |
96484e22 | 208 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", |
15abcf0f MC |
209 | command[0], libusb_error_name(ret)); |
210 | return SR_ERR; | |
211 | } | |
212 | if (xfer != cmd_len) { | |
96484e22 | 213 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " |
6433156c | 214 | "%d != %d.", command[0], xfer, cmd_len); |
15abcf0f MC |
215 | return SR_ERR; |
216 | } | |
217 | ||
218 | if (reply_len == 0) | |
219 | return SR_OK; | |
220 | ||
96484e22 UH |
221 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, |
222 | &xfer, 1000); | |
15abcf0f | 223 | if (ret != 0) { |
96484e22 | 224 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", |
15abcf0f MC |
225 | command[0], libusb_error_name(ret)); |
226 | return SR_ERR; | |
227 | } | |
228 | if (xfer != reply_len) { | |
96484e22 | 229 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " |
6433156c | 230 | "incorrect length %d != %d.", command[0], xfer, reply_len); |
15abcf0f MC |
231 | return SR_ERR; |
232 | } | |
233 | ||
234 | decrypt(reply, buf, reply_len); | |
235 | ||
236 | return SR_OK; | |
237 | } | |
238 | ||
239 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
240 | uint8_t address, uint8_t length, uint8_t *buf) | |
241 | { | |
242 | uint8_t command[5] = { | |
243 | COMMAND_READ_EEPROM, | |
244 | READ_EEPROM_COOKIE1, | |
245 | READ_EEPROM_COOKIE2, | |
246 | address, | |
247 | length, | |
248 | }; | |
249 | ||
250 | return do_ep1_command(sdi, command, 5, buf, length); | |
251 | } | |
252 | ||
253 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
254 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
255 | { | |
96484e22 | 256 | uint8_t chunk, command[64]; |
15abcf0f MC |
257 | int ret; |
258 | ||
98fec29e | 259 | if (cnt < 1 || cnt + offset > 64 || !table) |
15abcf0f MC |
260 | return SR_ERR_ARG; |
261 | ||
262 | while (cnt > 0) { | |
96484e22 | 263 | chunk = (cnt > 32 ? 32 : cnt); |
15abcf0f MC |
264 | |
265 | command[0] = COMMAND_WRITE_LED_TABLE; | |
266 | command[1] = offset; | |
267 | command[2] = chunk; | |
96484e22 | 268 | memcpy(command + 3, table, chunk); |
15abcf0f | 269 | |
96484e22 UH |
270 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); |
271 | if (ret != SR_OK) | |
15abcf0f MC |
272 | return ret; |
273 | ||
274 | table += chunk; | |
275 | offset += chunk; | |
276 | cnt -= chunk; | |
277 | } | |
278 | ||
279 | return SR_OK; | |
280 | } | |
281 | ||
282 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
283 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
284 | uint8_t repeat) | |
285 | { | |
286 | uint8_t command[6] = { | |
287 | COMMAND_SET_LED_MODE, | |
288 | animate, | |
96484e22 UH |
289 | t2reload & 0xff, |
290 | t2reload >> 8, | |
15abcf0f MC |
291 | div, |
292 | repeat, | |
293 | }; | |
294 | ||
295 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
296 | } | |
297 | ||
298 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
299 | uint8_t address, uint8_t *value) | |
300 | { | |
301 | uint8_t command[3] = { | |
302 | COMMAND_FPGA_READ_REGISTER, | |
303 | 1, | |
304 | address, | |
305 | }; | |
306 | ||
307 | return do_ep1_command(sdi, command, 3, value, 1); | |
308 | } | |
309 | ||
310 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
311 | uint8_t (*regs)[2], uint8_t cnt) | |
312 | { | |
313 | uint8_t command[64]; | |
314 | int i; | |
315 | ||
316 | if (cnt < 1 || cnt > 31) | |
317 | return SR_ERR_ARG; | |
318 | ||
319 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
320 | command[1] = cnt; | |
96484e22 UH |
321 | for (i = 0; i < cnt; i++) { |
322 | command[2 + 2 * i] = regs[i][0]; | |
323 | command[3 + 2 * i] = regs[i][1]; | |
15abcf0f MC |
324 | } |
325 | ||
96484e22 | 326 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); |
15abcf0f MC |
327 | } |
328 | ||
329 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
330 | uint8_t address, uint8_t value) | |
331 | { | |
332 | uint8_t regs[2] = { address, value }; | |
96484e22 | 333 | |
15abcf0f MC |
334 | return write_fpga_registers(sdi, ®s, 1); |
335 | } | |
336 | ||
15abcf0f MC |
337 | static uint8_t map_eeprom_data(uint8_t v) |
338 | { | |
186dde8d | 339 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; |
15abcf0f MC |
340 | } |
341 | ||
c8681396 MC |
342 | static int setup_register_mapping(const struct sr_dev_inst *sdi) |
343 | { | |
344 | struct dev_context *devc; | |
345 | int ret; | |
346 | ||
347 | devc = sdi->priv; | |
348 | ||
349 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
350 | uint8_t reg0, reg7; | |
351 | ||
352 | /* | |
353 | * Check for newer bitstream version by polling the | |
354 | * version register at the old and new location. | |
355 | */ | |
356 | ||
357 | if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK) | |
358 | return ret; | |
359 | ||
360 | if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK) | |
361 | return ret; | |
362 | ||
84ab9da1 UH |
363 | if (reg0 == 0 && reg7 > 0x10) { |
364 | sr_info("Original Saleae Logic16 using new bitstream."); | |
c8681396 | 365 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM; |
84ab9da1 UH |
366 | } else { |
367 | sr_info("Original Saleae Logic16 using old bitstream."); | |
c8681396 | 368 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; |
84ab9da1 | 369 | } |
c8681396 MC |
370 | } |
371 | ||
372 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) { | |
373 | devc->fpga_register_map = fpga_register_map_new; | |
374 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new; | |
375 | devc->fpga_mode_bit_map = fpga_mode_bit_map_new; | |
376 | } else { | |
377 | devc->fpga_register_map = fpga_register_map_old; | |
378 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old; | |
379 | devc->fpga_mode_bit_map = fpga_mode_bit_map_old; | |
380 | } | |
381 | ||
382 | return SR_OK; | |
383 | } | |
384 | ||
15abcf0f MC |
385 | static int prime_fpga(const struct sr_dev_inst *sdi) |
386 | { | |
c8681396 | 387 | struct dev_context *devc = sdi->priv; |
15abcf0f | 388 | uint8_t eeprom_data[16]; |
c8681396 | 389 | uint8_t old_mode_reg, version; |
15abcf0f | 390 | uint8_t regs[8][2] = { |
c8681396 MC |
391 | {FPGA_REG(MODE), 0x00}, |
392 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
393 | {FPGA_REG(PRIMER_DATA2), 0}, | |
394 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)}, | |
395 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
396 | {FPGA_REG(PRIMER_DATA1), 0}, | |
397 | {FPGA_REG(PRIMER_CONTROL), 1}, | |
398 | {FPGA_REG(PRIMER_CONTROL), 0} | |
15abcf0f MC |
399 | }; |
400 | int i, ret; | |
401 | ||
402 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
403 | return ret; | |
404 | ||
c8681396 | 405 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK) |
15abcf0f MC |
406 | return ret; |
407 | ||
c8681396 MC |
408 | regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2)); |
409 | regs[1][1] |= old_mode_reg; | |
410 | regs[3][1] |= old_mode_reg; | |
411 | regs[4][1] |= old_mode_reg; | |
186dde8d | 412 | |
96484e22 | 413 | for (i = 0; i < 16; i++) { |
15abcf0f MC |
414 | regs[2][1] = eeprom_data[i]; |
415 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
416 | if (i) | |
417 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
418 | else | |
419 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
420 | if (ret != SR_OK) | |
421 | return ret; | |
422 | } | |
423 | ||
c8681396 | 424 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK) |
15abcf0f MC |
425 | return ret; |
426 | ||
c8681396 | 427 | if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK) |
15abcf0f MC |
428 | return ret; |
429 | ||
c8681396 | 430 | if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) { |
108d2ec2 | 431 | sr_warn("Unsupported FPGA version: 0x%02x.", version); |
15abcf0f MC |
432 | } |
433 | ||
434 | return SR_OK; | |
435 | } | |
436 | ||
437 | static void make_heartbeat(uint8_t *table, int len) | |
438 | { | |
439 | int i, j; | |
440 | ||
441 | memset(table, 0, len); | |
442 | len >>= 3; | |
96484e22 UH |
443 | for (i = 0; i < 2; i++) |
444 | for (j = 0; j < len; j++) | |
bbc42811 | 445 | *table++ = sin(j * G_PI / len) * 255; |
15abcf0f MC |
446 | } |
447 | ||
448 | static int configure_led(const struct sr_dev_inst *sdi) | |
449 | { | |
450 | uint8_t table[64]; | |
451 | int ret; | |
452 | ||
453 | make_heartbeat(table, 64); | |
454 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
455 | return ret; | |
456 | ||
457 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
458 | } | |
459 | ||
460 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
461 | enum voltage_range vrange) | |
462 | { | |
8e2d6c9d DE |
463 | uint64_t sum; |
464 | struct sr_resource bitstream; | |
15abcf0f | 465 | struct dev_context *devc; |
8e2d6c9d DE |
466 | struct drv_context *drvc; |
467 | const char *name; | |
468 | ssize_t chunksize; | |
469 | int ret; | |
470 | uint8_t command[64]; | |
15abcf0f MC |
471 | |
472 | devc = sdi->priv; | |
8e2d6c9d | 473 | drvc = sdi->driver->context; |
15abcf0f MC |
474 | |
475 | if (devc->cur_voltage_range == vrange) | |
476 | return SR_OK; | |
477 | ||
c8681396 | 478 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { |
6f479a0a PZ |
479 | switch (vrange) { |
480 | case VOLTAGE_RANGE_18_33_V: | |
8e2d6c9d | 481 | name = FPGA_FIRMWARE_18; |
6f479a0a PZ |
482 | break; |
483 | case VOLTAGE_RANGE_5_V: | |
8e2d6c9d | 484 | name = FPGA_FIRMWARE_33; |
6f479a0a PZ |
485 | break; |
486 | default: | |
487 | sr_err("Unsupported voltage range."); | |
488 | return SR_ERR; | |
489 | } | |
15abcf0f | 490 | |
8e2d6c9d DE |
491 | sr_info("Uploading FPGA bitstream '%s'.", name); |
492 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, | |
493 | SR_RESOURCE_FIRMWARE, name); | |
494 | if (ret != SR_OK) | |
495 | return ret; | |
15abcf0f | 496 | |
8e2d6c9d DE |
497 | command[0] = COMMAND_FPGA_UPLOAD_INIT; |
498 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) { | |
499 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
6f479a0a PZ |
500 | return ret; |
501 | } | |
15abcf0f | 502 | |
8e2d6c9d | 503 | sum = 0; |
6f479a0a | 504 | while (1) { |
8e2d6c9d DE |
505 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, |
506 | &command[2], sizeof(command) - 2); | |
507 | if (chunksize < 0) { | |
508 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
509 | return SR_ERR; | |
510 | } | |
6f479a0a PZ |
511 | if (chunksize == 0) |
512 | break; | |
8e2d6c9d DE |
513 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; |
514 | command[1] = chunksize; | |
515 | ||
516 | ret = do_ep1_command(sdi, command, chunksize + 2, | |
517 | NULL, 0); | |
518 | if (ret != SR_OK) { | |
519 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
520 | return ret; | |
15abcf0f | 521 | } |
8e2d6c9d | 522 | sum += chunksize; |
6f479a0a | 523 | } |
8e2d6c9d DE |
524 | sr_resource_close(drvc->sr_ctx, &bitstream); |
525 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum); | |
15abcf0f | 526 | } |
15abcf0f | 527 | |
c8681396 MC |
528 | /* This needs to be called before accessing any FPGA registers. */ |
529 | if ((ret = setup_register_mapping(sdi)) != SR_OK) | |
530 | return ret; | |
531 | ||
15abcf0f MC |
532 | if ((ret = prime_fpga(sdi)) != SR_OK) |
533 | return ret; | |
534 | ||
535 | if ((ret = configure_led(sdi)) != SR_OK) | |
536 | return ret; | |
537 | ||
15abcf0f MC |
538 | devc->cur_voltage_range = vrange; |
539 | return SR_OK; | |
540 | } | |
541 | ||
7b5daad4 | 542 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) |
15abcf0f MC |
543 | { |
544 | static const uint8_t command[2] = { | |
545 | COMMAND_ABORT_ACQUISITION_SYNC, | |
546 | ABORT_ACQUISITION_SYNC_PATTERN, | |
547 | }; | |
548 | uint8_t reply, expected_reply; | |
549 | int ret; | |
550 | ||
551 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
552 | return ret; | |
553 | ||
554 | expected_reply = ~command[1]; | |
555 | if (reply != expected_reply) { | |
556 | sr_err("Invalid response for abort acquisition command: " | |
96484e22 | 557 | "0x%02x != 0x%02x.", reply, expected_reply); |
15abcf0f MC |
558 | return SR_ERR; |
559 | } | |
560 | ||
561 | return SR_OK; | |
562 | } | |
563 | ||
96484e22 UH |
564 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, |
565 | uint64_t samplerate, uint16_t channels) | |
7b5daad4 | 566 | { |
c8681396 | 567 | uint8_t clock_select, sta_con_reg, mode_reg; |
7b5daad4 MC |
568 | uint64_t div; |
569 | int i, ret, nchan = 0; | |
db11d7d2 MC |
570 | struct dev_context *devc; |
571 | ||
572 | devc = sdi->priv; | |
7b5daad4 MC |
573 | |
574 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
575 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
576 | return SR_ERR; | |
577 | } | |
578 | ||
579 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
580 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
581 | clock_select = 0; | |
582 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
583 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
584 | clock_select = 1; | |
585 | } else { | |
586 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
587 | return SR_ERR; | |
588 | } | |
589 | ||
96484e22 UH |
590 | for (i = 0; i < 16; i++) |
591 | if (channels & (1U << i)) | |
7b5daad4 MC |
592 | nchan++; |
593 | ||
cb193a20 | 594 | if (nchan * samplerate > MAX_SAMPLE_RATE_X_CH) { |
7b5daad4 MC |
595 | sr_err("Unable to sample at %" PRIu64 "Hz " |
596 | "with this many channels.", samplerate); | |
597 | return SR_ERR; | |
598 | } | |
599 | ||
96484e22 UH |
600 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
601 | if (ret != SR_OK) | |
db11d7d2 MC |
602 | return ret; |
603 | ||
c8681396 | 604 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
605 | return ret; |
606 | ||
7754fb4d | 607 | /* Ignore FIFO overflow on previous capture */ |
c8681396 | 608 | sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW); |
7754fb4d | 609 | |
c8681396 MC |
610 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
611 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
612 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
613 | } |
614 | ||
c8681396 | 615 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
616 | return ret; |
617 | ||
c8681396 | 618 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK) |
7b5daad4 MC |
619 | return ret; |
620 | ||
c8681396 | 621 | if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK) |
7b5daad4 MC |
622 | return ret; |
623 | ||
c8681396 | 624 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK) |
7b5daad4 MC |
625 | return ret; |
626 | ||
c8681396 | 627 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK) |
7b5daad4 MC |
628 | return ret; |
629 | ||
c8681396 | 630 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK) |
7b5daad4 MC |
631 | return ret; |
632 | ||
c8681396 | 633 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
634 | return ret; |
635 | ||
c8681396 | 636 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
637 | return ret; |
638 | ||
c8681396 MC |
639 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) { |
640 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
641 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
642 | } |
643 | ||
c8681396 | 644 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK) |
7b5daad4 MC |
645 | return ret; |
646 | ||
c8681396 | 647 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) { |
a11e10ec | 648 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " |
c8681396 | 649 | "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0)); |
7b5daad4 MC |
650 | } |
651 | ||
652 | return SR_OK; | |
653 | } | |
654 | ||
96484e22 | 655 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
656 | { |
657 | static const uint8_t command[1] = { | |
658 | COMMAND_START_ACQUISITION, | |
659 | }; | |
660 | int ret; | |
c8681396 MC |
661 | struct dev_context *devc; |
662 | ||
663 | devc = sdi->priv; | |
7b5daad4 MC |
664 | |
665 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
666 | return ret; | |
667 | ||
c8681396 | 668 | return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING)); |
7b5daad4 MC |
669 | } |
670 | ||
96484e22 | 671 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
672 | { |
673 | static const uint8_t command[1] = { | |
674 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
675 | }; | |
676 | int ret; | |
c8681396 | 677 | uint8_t sta_con_reg; |
6f479a0a PZ |
678 | struct dev_context *devc; |
679 | ||
680 | devc = sdi->priv; | |
7b5daad4 MC |
681 | |
682 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
683 | return ret; | |
684 | ||
c8681396 | 685 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK) |
7b5daad4 MC |
686 | return ret; |
687 | ||
c8681396 | 688 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
689 | return ret; |
690 | ||
c8681396 MC |
691 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
692 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
693 | return SR_ERR; |
694 | } | |
695 | ||
7b5daad4 | 696 | |
c8681396 MC |
697 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { |
698 | uint8_t reg8, reg9; | |
699 | ||
700 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
701 | return ret; | |
702 | ||
703 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
704 | return ret; | |
705 | } | |
7b5daad4 | 706 | |
c8681396 | 707 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) { |
7754fb4d MC |
708 | sr_warn("FIFO overflow, capture data may be truncated."); |
709 | return SR_ERR; | |
710 | } | |
711 | ||
7b5daad4 MC |
712 | return SR_OK; |
713 | } | |
714 | ||
96484e22 | 715 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) |
15abcf0f | 716 | { |
6f479a0a | 717 | uint8_t version; |
15abcf0f MC |
718 | struct dev_context *devc; |
719 | int ret; | |
720 | ||
721 | devc = sdi->priv; | |
722 | ||
723 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
724 | ||
7b5daad4 | 725 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) |
15abcf0f MC |
726 | return ret; |
727 | ||
728 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
729 | return ret; | |
730 | ||
6f479a0a PZ |
731 | /* mcupro Saleae16 has firmware pre-stored in FPGA. |
732 | So, we can query it right away. */ | |
c8681396 | 733 | if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK && |
6f479a0a PZ |
734 | (version == 0x40 || version == 0x41)) { |
735 | sr_info("mcupro Saleae16 detected."); | |
736 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
737 | } else { | |
738 | sr_info("Original Saleae Logic16 detected."); | |
739 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
740 | } | |
741 | ||
96484e22 UH |
742 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
743 | if (ret != SR_OK) | |
15abcf0f MC |
744 | return ret; |
745 | ||
746 | return SR_OK; | |
747 | } | |
748 | ||
102f1239 | 749 | static void finish_acquisition(struct sr_dev_inst *sdi) |
7b5daad4 | 750 | { |
102f1239 BV |
751 | struct dev_context *devc; |
752 | ||
753 | devc = sdi->priv; | |
7b5daad4 | 754 | |
bee2b016 | 755 | std_session_send_df_end(sdi); |
7b5daad4 | 756 | |
102f1239 | 757 | usb_source_remove(sdi->session, devc->ctx); |
7b5daad4 MC |
758 | |
759 | devc->num_transfers = 0; | |
760 | g_free(devc->transfers); | |
761 | g_free(devc->convbuffer); | |
863357fb BV |
762 | if (devc->stl) { |
763 | soft_trigger_logic_free(devc->stl); | |
764 | devc->stl = NULL; | |
765 | } | |
7b5daad4 MC |
766 | } |
767 | ||
768 | static void free_transfer(struct libusb_transfer *transfer) | |
769 | { | |
102f1239 | 770 | struct sr_dev_inst *sdi; |
7b5daad4 MC |
771 | struct dev_context *devc; |
772 | unsigned int i; | |
773 | ||
102f1239 BV |
774 | sdi = transfer->user_data; |
775 | devc = sdi->priv; | |
7b5daad4 MC |
776 | |
777 | g_free(transfer->buffer); | |
778 | transfer->buffer = NULL; | |
779 | libusb_free_transfer(transfer); | |
780 | ||
781 | for (i = 0; i < devc->num_transfers; i++) { | |
782 | if (devc->transfers[i] == transfer) { | |
783 | devc->transfers[i] = NULL; | |
784 | break; | |
785 | } | |
786 | } | |
787 | ||
788 | devc->submitted_transfers--; | |
789 | if (devc->submitted_transfers == 0) | |
102f1239 | 790 | finish_acquisition(sdi); |
7b5daad4 MC |
791 | } |
792 | ||
793 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
794 | { | |
795 | int ret; | |
796 | ||
797 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
798 | return; | |
799 | ||
800 | free_transfer(transfer); | |
801 | /* TODO: Stop session? */ | |
802 | ||
803 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
804 | } | |
805 | ||
a989cdbe BV |
806 | static size_t convert_sample_data(struct dev_context *devc, |
807 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
c463dcf0 | 808 | { |
7b5daad4 MC |
809 | uint16_t *channel_data; |
810 | int i, cur_channel; | |
811 | size_t ret = 0; | |
96484e22 | 812 | uint16_t sample, channel_mask; |
7b5daad4 MC |
813 | |
814 | srccnt /= 2; | |
815 | ||
816 | channel_data = devc->channel_data; | |
817 | cur_channel = devc->cur_channel; | |
818 | ||
96484e22 | 819 | while (srccnt--) { |
7b5daad4 MC |
820 | sample = src[0] | (src[1] << 8); |
821 | src += 2; | |
822 | ||
823 | channel_mask = devc->channel_masks[cur_channel]; | |
824 | ||
96484e22 | 825 | for (i = 15; i >= 0; --i, sample >>= 1) |
7b5daad4 MC |
826 | if (sample & 1) |
827 | channel_data[i] |= channel_mask; | |
828 | ||
829 | if (++cur_channel == devc->num_channels) { | |
830 | cur_channel = 0; | |
96484e22 | 831 | if (destcnt < 16 * 2) { |
7b5daad4 MC |
832 | sr_err("Conversion buffer too small!"); |
833 | break; | |
834 | } | |
96484e22 UH |
835 | memcpy(dest, channel_data, 16 * 2); |
836 | memset(channel_data, 0, 16 * 2); | |
837 | dest += 16 * 2; | |
1b822521 | 838 | ret += 16; |
96484e22 | 839 | destcnt -= 16 * 2; |
7b5daad4 MC |
840 | } |
841 | } | |
842 | ||
843 | devc->cur_channel = cur_channel; | |
c463dcf0 | 844 | |
7b5daad4 MC |
845 | return ret; |
846 | } | |
847 | ||
55462b8b | 848 | SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) |
7b5daad4 MC |
849 | { |
850 | gboolean packet_has_error = FALSE; | |
851 | struct sr_datafeed_packet packet; | |
852 | struct sr_datafeed_logic logic; | |
102f1239 | 853 | struct sr_dev_inst *sdi; |
c463dcf0 | 854 | struct dev_context *devc; |
863357fb BV |
855 | size_t new_samples, num_samples; |
856 | int trigger_offset; | |
5a971f66 | 857 | int pre_trigger_samples; |
7b5daad4 | 858 | |
102f1239 BV |
859 | sdi = transfer->user_data; |
860 | devc = sdi->priv; | |
7b5daad4 MC |
861 | |
862 | /* | |
863 | * If acquisition has already ended, just free any queued up | |
864 | * transfer that come in. | |
865 | */ | |
863357fb | 866 | if (devc->sent_samples < 0) { |
7b5daad4 MC |
867 | free_transfer(transfer); |
868 | return; | |
869 | } | |
870 | ||
974fb0ff BV |
871 | sr_info("receive_transfer(): status %s received %d bytes.", |
872 | libusb_error_name(transfer->status), transfer->actual_length); | |
7b5daad4 MC |
873 | |
874 | switch (transfer->status) { | |
875 | case LIBUSB_TRANSFER_NO_DEVICE: | |
863357fb | 876 | devc->sent_samples = -2; |
7b5daad4 MC |
877 | free_transfer(transfer); |
878 | return; | |
879 | case LIBUSB_TRANSFER_COMPLETED: | |
880 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
881 | break; | |
882 | default: | |
883 | packet_has_error = TRUE; | |
884 | break; | |
885 | } | |
c463dcf0 | 886 | |
7b5daad4 | 887 | if (transfer->actual_length & 1) { |
96484e22 UH |
888 | sr_err("Got an odd number of bytes from the device. " |
889 | "This should not happen."); | |
890 | /* Bail out right away. */ | |
7b5daad4 MC |
891 | packet_has_error = TRUE; |
892 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
893 | } | |
c463dcf0 | 894 | |
7b5daad4 MC |
895 | if (transfer->actual_length == 0 || packet_has_error) { |
896 | devc->empty_transfer_count++; | |
897 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
898 | /* | |
899 | * The FX2 gave up. End the acquisition, the frontend | |
900 | * will work out that the samplecount is short. | |
901 | */ | |
863357fb | 902 | devc->sent_samples = -2; |
7b5daad4 MC |
903 | free_transfer(transfer); |
904 | } else { | |
905 | resubmit_transfer(transfer); | |
906 | } | |
907 | return; | |
908 | } else { | |
909 | devc->empty_transfer_count = 0; | |
910 | } | |
c463dcf0 | 911 | |
863357fb | 912 | new_samples = convert_sample_data(devc, devc->convbuffer, |
a989cdbe | 913 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); |
863357fb | 914 | |
3782e571 UH |
915 | if (new_samples <= 0) { |
916 | resubmit_transfer(transfer); | |
917 | return; | |
918 | } | |
919 | ||
920 | /* At least one new sample. */ | |
921 | if (devc->trigger_fired) { | |
922 | /* Send the incoming transfer to the session bus. */ | |
923 | packet.type = SR_DF_LOGIC; | |
924 | packet.payload = &logic; | |
925 | if (devc->limit_samples && | |
926 | new_samples > devc->limit_samples - devc->sent_samples) | |
927 | new_samples = devc->limit_samples - devc->sent_samples; | |
928 | logic.length = new_samples * 2; | |
929 | logic.unitsize = 2; | |
930 | logic.data = devc->convbuffer; | |
931 | sr_session_send(sdi, &packet); | |
932 | devc->sent_samples += new_samples; | |
933 | } else { | |
934 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
935 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); | |
936 | if (trigger_offset > -1) { | |
937 | devc->sent_samples += pre_trigger_samples; | |
863357fb BV |
938 | packet.type = SR_DF_LOGIC; |
939 | packet.payload = &logic; | |
3782e571 | 940 | num_samples = new_samples - trigger_offset; |
863357fb | 941 | if (devc->limit_samples && |
3782e571 UH |
942 | num_samples > devc->limit_samples - devc->sent_samples) |
943 | num_samples = devc->limit_samples - devc->sent_samples; | |
944 | logic.length = num_samples * 2; | |
a989cdbe | 945 | logic.unitsize = 2; |
3782e571 | 946 | logic.data = devc->convbuffer + trigger_offset * 2; |
695dc859 | 947 | sr_session_send(sdi, &packet); |
3782e571 | 948 | devc->sent_samples += num_samples; |
2db95906 | 949 | |
3782e571 | 950 | devc->trigger_fired = TRUE; |
7b5daad4 | 951 | } |
c463dcf0 MC |
952 | } |
953 | ||
3782e571 UH |
954 | if (devc->limit_samples && |
955 | (uint64_t)devc->sent_samples >= devc->limit_samples) { | |
956 | devc->sent_samples = -2; | |
957 | free_transfer(transfer); | |
958 | return; | |
959 | } | |
960 | ||
7b5daad4 | 961 | resubmit_transfer(transfer); |
c463dcf0 | 962 | } |