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f4816ac6 ML |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
88e429c9 | 5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
bafd4890 | 6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> |
f4816ac6 ML |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
f4816ac6 | 23 | #include <stdlib.h> |
e0b7d23c ML |
24 | #include <stdarg.h> |
25 | #include <unistd.h> | |
26 | #include <errno.h> | |
a3df166f | 27 | #include <string.h> |
254dd102 | 28 | #include <math.h> |
bafd4890 ML |
29 | #include <ctype.h> |
30 | #include <time.h> | |
f4816ac6 | 31 | #include <glib.h> |
c1aae900 | 32 | #include <libsigrok/libsigrok.h> |
f4816ac6 | 33 | #include "libsigrok-internal.h" |
5a1afc09 | 34 | #include "scpi.h" |
f4816ac6 ML |
35 | #include "protocol.h" |
36 | ||
bafd4890 ML |
37 | /* |
38 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
39 | * | |
40 | * DS1000 support tested with a Rigol DS1102D. | |
41 | * | |
42 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
43 | * | |
44 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
45 | * standard. If you want to read it - it costs real money... | |
46 | * | |
47 | * Every response from the scope has a linefeed appended because the | |
48 | * standard says so. In principle this could be ignored because sending the | |
49 | * next command clears the output queue of the scope. This driver tries to | |
50 | * avoid doing that because it may cause an error being generated inside the | |
51 | * scope and who knows what bugs the firmware has WRT this. | |
52 | * | |
53 | * Waveform data is transferred in a format called "arbitrary block program | |
54 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
55 | * 2000/3000 series scopes for a nice description. | |
56 | * | |
57 | * Each data block from the scope has a header, e.g. "#900000001400". | |
58 | * The '#' marks the start of a block. | |
59 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
60 | * ASCII decimal digits following. | |
61 | * Last are the ASCII decimal digits giving the number of bytes (not | |
62 | * samples!) in the block. | |
63 | * | |
64 | * After this header as many data bytes as indicated follow. | |
65 | * | |
66 | * Each data block has a trailing linefeed too. | |
67 | */ | |
68 | ||
bafd4890 ML |
69 | static int parse_int(const char *str, int *ret) |
70 | { | |
71 | char *e; | |
72 | long tmp; | |
73 | ||
74 | errno = 0; | |
75 | tmp = strtol(str, &e, 10); | |
76 | if (e == str || *e != '\0') { | |
77 | sr_dbg("Failed to parse integer: '%s'", str); | |
78 | return SR_ERR; | |
79 | } | |
80 | if (errno) { | |
81 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
82 | return SR_ERR; | |
83 | } | |
84 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
85 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
86 | return SR_ERR; | |
87 | } | |
88 | ||
89 | *ret = (int)tmp; | |
90 | return SR_OK; | |
91 | } | |
92 | ||
babab622 ML |
93 | /* Set the next event to wait for in rigol_ds_receive */ |
94 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
95 | { | |
96 | if (event == WAIT_STOP) | |
97 | devc->wait_status = 2; | |
98 | else | |
99 | devc->wait_status = 1; | |
100 | devc->wait_event = event; | |
101 | } | |
102 | ||
bafd4890 | 103 | /* |
babab622 ML |
104 | * Waiting for a event will return a timeout after 2 to 3 seconds in order |
105 | * to not block the application. | |
bafd4890 | 106 | */ |
babab622 | 107 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) |
bafd4890 | 108 | { |
334fbc2a | 109 | char *buf; |
bafd4890 ML |
110 | struct dev_context *devc; |
111 | time_t start; | |
112 | ||
113 | if (!(devc = sdi->priv)) | |
114 | return SR_ERR; | |
115 | ||
116 | start = time(NULL); | |
117 | ||
118 | /* | |
119 | * Trigger status may return: | |
babab622 ML |
120 | * "TD" or "T'D" - triggered |
121 | * "AUTO" - autotriggered | |
122 | * "RUN" - running | |
123 | * "WAIT" - waiting for trigger | |
124 | * "STOP" - stopped | |
bafd4890 ML |
125 | */ |
126 | ||
babab622 | 127 | if (devc->wait_status == 1) { |
bafd4890 ML |
128 | do { |
129 | if (time(NULL) - start >= 3) { | |
130 | sr_dbg("Timeout waiting for trigger"); | |
131 | return SR_ERR_TIMEOUT; | |
132 | } | |
133 | ||
334fbc2a | 134 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 135 | return SR_ERR; |
babab622 | 136 | } while (buf[0] == status1 || buf[0] == status2); |
bafd4890 | 137 | |
babab622 | 138 | devc->wait_status = 2; |
bafd4890 | 139 | } |
babab622 | 140 | if (devc->wait_status == 2) { |
bafd4890 ML |
141 | do { |
142 | if (time(NULL) - start >= 3) { | |
143 | sr_dbg("Timeout waiting for trigger"); | |
144 | return SR_ERR_TIMEOUT; | |
145 | } | |
146 | ||
334fbc2a | 147 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 148 | return SR_ERR; |
babab622 | 149 | } while (buf[0] != status1 && buf[0] != status2); |
bafd4890 | 150 | |
babab622 | 151 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
bafd4890 ML |
152 | } |
153 | ||
154 | return SR_OK; | |
155 | } | |
156 | ||
157 | /* | |
babab622 ML |
158 | * For live capture we need to wait for a new trigger event to ensure that |
159 | * sample data is not returned twice. | |
bafd4890 ML |
160 | * |
161 | * Unfortunately this will never really work because for sufficiently fast | |
babab622 | 162 | * timebases and trigger rates it just can't catch the status changes. |
bafd4890 ML |
163 | * |
164 | * What would be needed is a trigger event register with autoreset like the | |
165 | * Agilents have. The Rigols don't seem to have anything like this. | |
166 | * | |
167 | * The workaround is to only wait for the trigger when the timebase is slow | |
168 | * enough. Of course this means that for faster timebases sample data can be | |
babab622 ML |
169 | * returned multiple times, this effect is mitigated somewhat by sleeping |
170 | * for about one sweep time in that case. | |
bafd4890 | 171 | */ |
babab622 | 172 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) |
bafd4890 ML |
173 | { |
174 | struct dev_context *devc; | |
babab622 | 175 | long s; |
bafd4890 ML |
176 | |
177 | if (!(devc = sdi->priv)) | |
178 | return SR_ERR; | |
179 | ||
babab622 ML |
180 | /* |
181 | * If timebase < 50 msecs/DIV just sleep about one sweep time except | |
182 | * for really fast sweeps. | |
183 | */ | |
c2b394d5 | 184 | if (devc->timebase < 0.0499) { |
babab622 ML |
185 | if (devc->timebase > 0.99e-6) { |
186 | /* | |
187 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
188 | * -> 85 percent of sweep time | |
189 | */ | |
569d4dbd | 190 | s = (devc->timebase * devc->model->series->num_horizontal_divs |
babab622 ML |
191 | * 85e6) / 100L; |
192 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
193 | g_usleep(s); | |
194 | } | |
195 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
196 | return SR_OK; | |
197 | } else { | |
198 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
199 | } | |
200 | } | |
bafd4890 | 201 | |
babab622 ML |
202 | /* Wait for scope to got to "Stop" in single shot mode */ |
203 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
204 | { | |
205 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
206 | } | |
207 | ||
208 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
209 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
210 | { | |
211 | struct dev_context *devc; | |
ba7dd8bb | 212 | struct sr_channel *ch; |
babab622 ML |
213 | int tmp; |
214 | ||
215 | if (!(devc = sdi->priv)) | |
bafd4890 | 216 | return SR_ERR; |
babab622 | 217 | |
ba7dd8bb | 218 | ch = devc->channel_entry->data; |
821fbcad | 219 | |
702f42e8 | 220 | if (devc->model->series->protocol != PROTOCOL_V3) |
e086b750 ML |
221 | return SR_OK; |
222 | ||
38354d9d | 223 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 224 | ch->index + 1) != SR_OK) |
babab622 ML |
225 | return SR_ERR; |
226 | /* Check that the number of samples will be accepted */ | |
38354d9d | 227 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK) |
babab622 | 228 | return SR_ERR; |
334fbc2a | 229 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) |
bafd4890 | 230 | return SR_ERR; |
babab622 ML |
231 | /* |
232 | * If we get an "Execution error" the scope went from "Single" to | |
233 | * "Stop" without actually triggering. There is no waveform | |
234 | * displayed and trying to download one will fail - the scope thinks | |
235 | * it has 1400 samples (like display memory) and the driver thinks | |
236 | * it has a different number of samples. | |
237 | * | |
238 | * In that case just try to capture something again. Might still | |
239 | * fail in interesting ways. | |
240 | * | |
241 | * Ain't firmware fun? | |
242 | */ | |
243 | if (tmp & 0x10) { | |
244 | sr_warn("Single shot acquisition failed, retrying..."); | |
245 | /* Sleep a bit, otherwise the single shot will often fail */ | |
1a46cc62 | 246 | g_usleep(500 * 1000); |
38354d9d | 247 | rigol_ds_config_set(sdi, ":SING"); |
babab622 | 248 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
bafd4890 | 249 | return SR_ERR; |
babab622 | 250 | } |
bafd4890 | 251 | |
babab622 ML |
252 | return SR_OK; |
253 | } | |
bafd4890 | 254 | |
babab622 ML |
255 | /* Wait for enough data becoming available in scope output buffer */ |
256 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
257 | { | |
334fbc2a | 258 | char *buf; |
babab622 ML |
259 | struct dev_context *devc; |
260 | time_t start; | |
261 | int len; | |
262 | ||
263 | if (!(devc = sdi->priv)) | |
264 | return SR_ERR; | |
265 | ||
702f42e8 | 266 | if (devc->model->series->protocol == PROTOCOL_V3) { |
babab622 | 267 | |
4472867a ML |
268 | start = time(NULL); |
269 | ||
270 | do { | |
271 | if (time(NULL) - start >= 3) { | |
272 | sr_dbg("Timeout waiting for data block"); | |
273 | return SR_ERR_TIMEOUT; | |
274 | } | |
babab622 | 275 | |
4472867a ML |
276 | /* |
277 | * The scope copies data really slowly from sample | |
278 | * memory to its output buffer, so try not to bother | |
279 | * it too much with SCPI requests but don't wait too | |
280 | * long for short sample frame sizes. | |
281 | */ | |
1a46cc62 | 282 | g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000)); |
4472867a ML |
283 | |
284 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
285 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) | |
286 | return SR_ERR; | |
287 | ||
288 | if (parse_int(buf + 5, &len) != SR_OK) | |
289 | return SR_ERR; | |
1a46cc62 | 290 | } while (buf[0] == 'R' && len < (1000 * 1000)); |
4472867a | 291 | } |
babab622 ML |
292 | |
293 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
294 | ||
295 | return SR_OK; | |
296 | } | |
297 | ||
38354d9d ML |
298 | /* Send a configuration setting. */ |
299 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
300 | { | |
301 | struct dev_context *devc = sdi->priv; | |
302 | va_list args; | |
303 | int ret; | |
304 | ||
305 | va_start(args, format); | |
306 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
307 | va_end(args); | |
308 | ||
309 | if (ret != SR_OK) | |
310 | return SR_ERR; | |
311 | ||
569d4dbd | 312 | if (devc->model->series->protocol == PROTOCOL_V2) { |
38354d9d ML |
313 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ |
314 | sr_spew("delay %dms", 100); | |
1a46cc62 | 315 | g_usleep(100 * 1000); |
38354d9d ML |
316 | return SR_OK; |
317 | } else { | |
318 | return sr_scpi_get_opc(sdi->conn); | |
319 | } | |
320 | } | |
321 | ||
babab622 ML |
322 | /* Start capturing a new frameset */ |
323 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
324 | { | |
325 | struct dev_context *devc; | |
e086b750 | 326 | gchar *trig_mode; |
702f42e8 | 327 | unsigned int num_channels, i, j; |
babab622 ML |
328 | |
329 | if (!(devc = sdi->priv)) | |
330 | return SR_ERR; | |
331 | ||
0c536bcd | 332 | sr_dbg("Starting data capture for frameset %" PRIu64 " of %" PRIu64, |
babab622 ML |
333 | devc->num_frames + 1, devc->limit_frames); |
334 | ||
569d4dbd ML |
335 | switch (devc->model->series->protocol) { |
336 | case PROTOCOL_V1: | |
337 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
338 | break; | |
339 | case PROTOCOL_V2: | |
340 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
341 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
e086b750 | 342 | return SR_ERR; |
569d4dbd | 343 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 344 | } else { |
e086b750 ML |
345 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) |
346 | return SR_ERR; | |
347 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
348 | return SR_ERR; | |
349 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
350 | return SR_ERR; | |
351 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
352 | return SR_ERR; | |
353 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
354 | return SR_ERR; | |
569d4dbd ML |
355 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
356 | } | |
357 | break; | |
358 | case PROTOCOL_V3: | |
702f42e8 | 359 | case PROTOCOL_V4: |
569d4dbd ML |
360 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) |
361 | return SR_ERR; | |
362 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
363 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
364 | return SR_ERR; | |
702f42e8 ML |
365 | devc->analog_frame_size = devc->model->series->live_samples; |
366 | devc->digital_frame_size = devc->model->series->live_samples; | |
569d4dbd | 367 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 368 | } else { |
702f42e8 ML |
369 | if (devc->model->series->protocol == PROTOCOL_V3) { |
370 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
371 | return SR_ERR; | |
372 | } else if (devc->model->series->protocol == PROTOCOL_V4) { | |
373 | num_channels = 0; | |
374 | ||
375 | /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */ | |
376 | for (i = 0; i < devc->model->analog_channels; i++) { | |
377 | if (devc->analog_channels[i]) { | |
378 | num_channels++; | |
379 | } else if (i >= 2 && devc->model->has_digital) { | |
380 | for (j = 0; j < 8; j++) { | |
381 | if (devc->digital_channels[8 * (i - 2) + j]) { | |
382 | num_channels++; | |
383 | break; | |
384 | } | |
385 | } | |
386 | } | |
387 | } | |
388 | ||
389 | devc->analog_frame_size = devc->digital_frame_size = | |
390 | num_channels == 1 ? | |
391 | devc->model->series->buffer_samples : | |
392 | num_channels == 2 ? | |
393 | devc->model->series->buffer_samples / 2 : | |
394 | devc->model->series->buffer_samples / 4; | |
395 | } | |
396 | ||
e086b750 ML |
397 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) |
398 | return SR_ERR; | |
569d4dbd | 399 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
e086b750 | 400 | } |
569d4dbd | 401 | break; |
bafd4890 ML |
402 | } |
403 | ||
404 | return SR_OK; | |
405 | } | |
406 | ||
babab622 ML |
407 | /* Start reading data from the current channel */ |
408 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
409 | { | |
410 | struct dev_context *devc; | |
ba7dd8bb | 411 | struct sr_channel *ch; |
babab622 ML |
412 | |
413 | if (!(devc = sdi->priv)) | |
414 | return SR_ERR; | |
415 | ||
ba7dd8bb | 416 | ch = devc->channel_entry->data; |
821fbcad | 417 | |
ba7dd8bb | 418 | sr_dbg("Starting reading data from channel %d", ch->index + 1); |
babab622 | 419 | |
2ea67fc9 | 420 | switch (devc->model->series->protocol) { |
702f42e8 ML |
421 | case PROTOCOL_V1: |
422 | case PROTOCOL_V2: | |
3f239f08 | 423 | if (ch->type == SR_CHANNEL_LOGIC) { |
677f85d0 ML |
424 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) |
425 | return SR_ERR; | |
426 | } else { | |
821fbcad | 427 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", |
ba7dd8bb | 428 | ch->index + 1) != SR_OK) |
677f85d0 ML |
429 | return SR_ERR; |
430 | } | |
e086b750 | 431 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
702f42e8 ML |
432 | break; |
433 | case PROTOCOL_V3: | |
38354d9d | 434 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 435 | ch->index + 1) != SR_OK) |
babab622 | 436 | return SR_ERR; |
677f85d0 | 437 | if (devc->data_source != DATA_SOURCE_LIVE) { |
38354d9d | 438 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) |
677f85d0 | 439 | return SR_ERR; |
38354d9d | 440 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) |
677f85d0 | 441 | return SR_ERR; |
aff00e40 | 442 | } |
702f42e8 ML |
443 | break; |
444 | case PROTOCOL_V4: | |
445 | if (ch->type == SR_CHANNEL_ANALOG) { | |
446 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
447 | ch->index + 1) != SR_OK) | |
448 | return SR_ERR; | |
449 | } else { | |
450 | if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d", | |
451 | ch->index) != SR_OK) | |
452 | return SR_ERR; | |
453 | } | |
454 | ||
455 | if (rigol_ds_config_set(sdi, | |
456 | devc->data_source == DATA_SOURCE_LIVE ? | |
457 | ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK) | |
458 | return SR_ERR; | |
459 | break; | |
460 | } | |
461 | ||
462 | if (devc->model->series->protocol >= PROTOCOL_V3 && | |
463 | ch->type == SR_CHANNEL_ANALOG) { | |
464 | /* Vertical reference. */ | |
465 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", | |
466 | &devc->vert_reference[ch->index]) != SR_OK) | |
467 | return SR_ERR; | |
677f85d0 | 468 | } |
babab622 | 469 | |
aff00e40 ML |
470 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
471 | ||
f76c24f6 | 472 | devc->num_channel_bytes = 0; |
aff00e40 | 473 | devc->num_header_bytes = 0; |
babab622 ML |
474 | devc->num_block_bytes = 0; |
475 | ||
476 | return SR_OK; | |
477 | } | |
478 | ||
479 | /* Read the header of a data block */ | |
aff00e40 | 480 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) |
bafd4890 | 481 | { |
aff00e40 ML |
482 | struct sr_scpi_dev_inst *scpi = sdi->conn; |
483 | struct dev_context *devc = sdi->priv; | |
484 | char *buf = (char *) devc->buffer; | |
fe0d9caa ML |
485 | size_t header_length; |
486 | int ret; | |
aff00e40 ML |
487 | |
488 | /* Try to read the hashsign and length digit. */ | |
489 | if (devc->num_header_bytes < 2) { | |
fe0d9caa | 490 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, |
aff00e40 | 491 | 2 - devc->num_header_bytes); |
fe0d9caa | 492 | if (ret < 0) { |
aff00e40 ML |
493 | sr_err("Read error while reading data header."); |
494 | return SR_ERR; | |
495 | } | |
fe0d9caa | 496 | devc->num_header_bytes += ret; |
bafd4890 | 497 | } |
aff00e40 ML |
498 | |
499 | if (devc->num_header_bytes < 2) | |
500 | return 0; | |
501 | ||
502 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
503 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
504 | return SR_ERR; | |
bafd4890 | 505 | } |
bafd4890 | 506 | |
fe0d9caa | 507 | header_length = 2 + buf[1] - '0'; |
aff00e40 ML |
508 | |
509 | /* Try to read the length. */ | |
fe0d9caa ML |
510 | if (devc->num_header_bytes < header_length) { |
511 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
512 | header_length - devc->num_header_bytes); | |
513 | if (ret < 0) { | |
aff00e40 ML |
514 | sr_err("Read error while reading data header."); |
515 | return SR_ERR; | |
516 | } | |
fe0d9caa | 517 | devc->num_header_bytes += ret; |
bafd4890 | 518 | } |
aff00e40 | 519 | |
fe0d9caa | 520 | if (devc->num_header_bytes < header_length) |
aff00e40 ML |
521 | return 0; |
522 | ||
523 | /* Read the data length. */ | |
fe0d9caa | 524 | buf[header_length] = '\0'; |
aff00e40 | 525 | |
fe0d9caa | 526 | if (parse_int(buf + 2, &ret) != SR_OK) { |
aff00e40 | 527 | sr_err("Received invalid data block length '%s'.", buf + 2); |
bafd4890 ML |
528 | return -1; |
529 | } | |
530 | ||
fe0d9caa | 531 | sr_dbg("Received data block header: '%s' -> block length %d", buf, ret); |
bafd4890 | 532 | |
fe0d9caa | 533 | return ret; |
bafd4890 ML |
534 | } |
535 | ||
3086efdd | 536 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) |
f4816ac6 | 537 | { |
e0b7d23c | 538 | struct sr_dev_inst *sdi; |
ae1bc1cc | 539 | struct sr_scpi_dev_inst *scpi; |
f4816ac6 | 540 | struct dev_context *devc; |
e0b7d23c | 541 | struct sr_datafeed_packet packet; |
5faebab2 | 542 | struct sr_datafeed_analog_old analog; |
6bb192bc | 543 | struct sr_datafeed_logic logic; |
254dd102 | 544 | double vdiv, offset; |
f80a0bf2 | 545 | int len, i, vref; |
ba7dd8bb | 546 | struct sr_channel *ch; |
bac11aeb | 547 | gsize expected_data_bytes; |
f4816ac6 | 548 | |
decfe89d | 549 | (void)fd; |
9bd4c956 | 550 | |
f4816ac6 ML |
551 | if (!(sdi = cb_data)) |
552 | return TRUE; | |
553 | ||
554 | if (!(devc = sdi->priv)) | |
555 | return TRUE; | |
556 | ||
ae1bc1cc | 557 | scpi = sdi->conn; |
9bd4c956 | 558 | |
dc89faea UH |
559 | if (!(revents == G_IO_IN || revents == 0)) |
560 | return TRUE; | |
561 | ||
562 | switch (devc->wait_event) { | |
563 | case WAIT_NONE: | |
564 | break; | |
565 | case WAIT_TRIGGER: | |
566 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
3918fbb0 | 567 | return TRUE; |
dc89faea | 568 | if (rigol_ds_channel_start(sdi) != SR_OK) |
e086b750 | 569 | return TRUE; |
dc89faea UH |
570 | return TRUE; |
571 | case WAIT_BLOCK: | |
572 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
573 | return TRUE; | |
574 | break; | |
575 | case WAIT_STOP: | |
576 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
577 | return TRUE; | |
578 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
579 | return TRUE; | |
580 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
581 | return TRUE; | |
582 | return TRUE; | |
583 | default: | |
584 | sr_err("BUG: Unknown event target encountered"); | |
585 | break; | |
586 | } | |
f76c24f6 | 587 | |
dc89faea | 588 | ch = devc->channel_entry->data; |
702f42e8 | 589 | |
dc89faea UH |
590 | expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ? |
591 | devc->analog_frame_size : devc->digital_frame_size; | |
bac11aeb | 592 | |
dc89faea UH |
593 | if (devc->num_block_bytes == 0) { |
594 | if (devc->model->series->protocol >= PROTOCOL_V4) { | |
595 | if (sr_scpi_send(sdi->conn, ":WAV:START %d", | |
596 | devc->num_channel_bytes + 1) != SR_OK) | |
597 | return TRUE; | |
598 | if (sr_scpi_send(sdi->conn, ":WAV:STOP %d", | |
599 | MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE, | |
600 | devc->analog_frame_size)) != SR_OK) | |
05c644ea | 601 | return TRUE; |
bafd4890 | 602 | } |
f80a0bf2 | 603 | |
dc89faea UH |
604 | if (devc->model->series->protocol >= PROTOCOL_V3) |
605 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) | |
606 | return TRUE; | |
f80a0bf2 | 607 | |
dc89faea | 608 | if (sr_scpi_read_begin(scpi) != SR_OK) |
7d63347e | 609 | return TRUE; |
6bb192bc | 610 | |
dc89faea UH |
611 | if (devc->format == FORMAT_IEEE488_2) { |
612 | sr_dbg("New block header expected"); | |
613 | len = rigol_ds_read_header(sdi); | |
614 | if (len == 0) | |
615 | /* Still reading the header. */ | |
616 | return TRUE; | |
617 | if (len == -1) { | |
618 | sr_err("Read error, aborting capture."); | |
7d63347e ML |
619 | packet.type = SR_DF_FRAME_END; |
620 | sr_session_send(cb_data, &packet); | |
3ed7a40c ML |
621 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
622 | return TRUE; | |
623 | } | |
dc89faea UH |
624 | /* At slow timebases in live capture the DS2072 |
625 | * sometimes returns "short" data blocks, with | |
626 | * apparently no way to get the rest of the data. | |
627 | * Discard these, the complete data block will | |
628 | * appear eventually. | |
629 | */ | |
630 | if (devc->data_source == DATA_SOURCE_LIVE | |
631 | && (unsigned)len < expected_data_bytes) { | |
632 | sr_dbg("Discarding short data block"); | |
633 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); | |
634 | return TRUE; | |
635 | } | |
636 | devc->num_block_bytes = len; | |
48460c6f | 637 | } else { |
dc89faea | 638 | devc->num_block_bytes = expected_data_bytes; |
ee7e9bee | 639 | } |
dc89faea UH |
640 | devc->num_block_read = 0; |
641 | } | |
75d8a4e5 | 642 | |
dc89faea UH |
643 | len = devc->num_block_bytes - devc->num_block_read; |
644 | if (len > ACQ_BUFFER_SIZE) | |
645 | len = ACQ_BUFFER_SIZE; | |
646 | sr_dbg("Requesting read of %d bytes", len); | |
48460c6f | 647 | |
dc89faea | 648 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); |
48460c6f | 649 | |
dc89faea UH |
650 | if (len == -1) { |
651 | sr_err("Read error, aborting capture."); | |
652 | packet.type = SR_DF_FRAME_END; | |
653 | sr_session_send(cb_data, &packet); | |
654 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
655 | return TRUE; | |
656 | } | |
657 | ||
658 | sr_dbg("Received %d bytes.", len); | |
659 | ||
660 | devc->num_block_read += len; | |
661 | ||
662 | if (ch->type == SR_CHANNEL_ANALOG) { | |
663 | vref = devc->vert_reference[ch->index]; | |
664 | vdiv = devc->vdiv[ch->index] / 25.6; | |
665 | offset = devc->vert_offset[ch->index]; | |
666 | if (devc->model->series->protocol >= PROTOCOL_V3) | |
667 | for (i = 0; i < len; i++) | |
668 | devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset; | |
669 | else | |
670 | for (i = 0; i < len; i++) | |
671 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; | |
672 | analog.channels = g_slist_append(NULL, ch); | |
673 | analog.num_samples = len; | |
674 | analog.data = devc->data; | |
675 | analog.mq = SR_MQ_VOLTAGE; | |
676 | analog.unit = SR_UNIT_VOLT; | |
677 | analog.mqflags = 0; | |
5faebab2 | 678 | packet.type = SR_DF_ANALOG_OLD; |
dc89faea UH |
679 | packet.payload = &analog; |
680 | sr_session_send(cb_data, &packet); | |
681 | g_slist_free(analog.channels); | |
682 | } else { | |
683 | logic.length = len; | |
684 | // TODO: For the MSO1000Z series, we need a way to express that | |
685 | // this data is in fact just for a single channel, with the valid | |
686 | // data for that channel in the LSB of each byte. | |
687 | logic.unitsize = devc->model->series->protocol == PROTOCOL_V4 ? 1 : 2; | |
688 | logic.data = devc->buffer; | |
689 | packet.type = SR_DF_LOGIC; | |
690 | packet.payload = &logic; | |
691 | sr_session_send(cb_data, &packet); | |
692 | } | |
693 | ||
694 | if (devc->num_block_read == devc->num_block_bytes) { | |
695 | sr_dbg("Block has been completed"); | |
696 | if (devc->model->series->protocol >= PROTOCOL_V3) { | |
697 | /* Discard the terminating linefeed */ | |
698 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); | |
699 | } | |
700 | if (devc->format == FORMAT_IEEE488_2) { | |
701 | /* Prepare for possible next block */ | |
702 | devc->num_header_bytes = 0; | |
703 | devc->num_block_bytes = 0; | |
babab622 | 704 | if (devc->data_source != DATA_SOURCE_LIVE) |
dc89faea | 705 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
babab622 | 706 | } |
dc89faea UH |
707 | if (!sr_scpi_read_complete(scpi)) { |
708 | sr_err("Read should have been completed"); | |
702f42e8 ML |
709 | packet.type = SR_DF_FRAME_END; |
710 | sr_session_send(cb_data, &packet); | |
dc89faea UH |
711 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
712 | return TRUE; | |
713 | } | |
714 | devc->num_block_read = 0; | |
715 | } else { | |
6433156c DE |
716 | sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read", |
717 | devc->num_block_read, devc->num_block_bytes); | |
dc89faea | 718 | } |
f76c24f6 | 719 | |
dc89faea | 720 | devc->num_channel_bytes += len; |
f76c24f6 | 721 | |
dc89faea UH |
722 | if (devc->num_channel_bytes < expected_data_bytes) |
723 | /* Don't have the full data for this channel yet, re-run. */ | |
724 | return TRUE; | |
f76c24f6 | 725 | |
dc89faea UH |
726 | /* End of data for this channel. */ |
727 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
728 | /* Signal end of data download to scope */ | |
729 | if (devc->data_source != DATA_SOURCE_LIVE) | |
730 | /* | |
731 | * This causes a query error, without it switching | |
732 | * to the next channel causes an error. Fun with | |
733 | * firmware... | |
734 | */ | |
735 | rigol_ds_config_set(sdi, ":WAV:END"); | |
736 | } | |
737 | ||
738 | if (devc->channel_entry->next) { | |
739 | /* We got the frame for this channel, now get the next channel. */ | |
740 | devc->channel_entry = devc->channel_entry->next; | |
741 | rigol_ds_channel_start(sdi); | |
742 | } else { | |
743 | /* Done with this frame. */ | |
744 | packet.type = SR_DF_FRAME_END; | |
745 | sr_session_send(cb_data, &packet); | |
746 | ||
747 | if (++devc->num_frames == devc->limit_frames) { | |
748 | /* Last frame, stop capture. */ | |
749 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
750 | } else { | |
751 | /* Get the next frame, starting with the first channel. */ | |
752 | devc->channel_entry = devc->enabled_channels; | |
753 | ||
754 | rigol_ds_capture_start(sdi); | |
755 | ||
756 | /* Start of next frame. */ | |
757 | packet.type = SR_DF_FRAME_BEGIN; | |
758 | sr_session_send(cb_data, &packet); | |
75d8a4e5 | 759 | } |
f4816ac6 ML |
760 | } |
761 | ||
762 | return TRUE; | |
763 | } | |
e0b7d23c | 764 | |
3086efdd | 765 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) |
254dd102 BV |
766 | { |
767 | struct dev_context *devc; | |
98bfc474 | 768 | char *cmd; |
821fbcad ML |
769 | unsigned int i; |
770 | int res; | |
254dd102 BV |
771 | |
772 | devc = sdi->priv; | |
773 | ||
6bb192bc | 774 | /* Analog channel state. */ |
821fbcad ML |
775 | for (i = 0; i < devc->model->analog_channels; i++) { |
776 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
98bfc474 | 777 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]); |
821fbcad ML |
778 | g_free(cmd); |
779 | if (res != SR_OK) | |
780 | return SR_ERR; | |
821fbcad ML |
781 | } |
782 | sr_dbg("Current analog channel state:"); | |
783 | for (i = 0; i < devc->model->analog_channels; i++) | |
784 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
6bb192bc ML |
785 | |
786 | /* Digital channel state. */ | |
bafd4890 | 787 | if (devc->model->has_digital) { |
702f42e8 ML |
788 | if (sr_scpi_get_bool(sdi->conn, |
789 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
790 | ":LA:STAT?" : ":LA:DISP?", | |
98bfc474 | 791 | &devc->la_enabled) != SR_OK) |
04e8e01e | 792 | return SR_ERR; |
04e8e01e ML |
793 | sr_dbg("Logic analyzer %s, current digital channel state:", |
794 | devc->la_enabled ? "enabled" : "disabled"); | |
effb9dd1 | 795 | for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) { |
702f42e8 ML |
796 | cmd = g_strdup_printf( |
797 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
798 | ":LA:DIG%d:DISP?" : ":DIG%d:TURN?", i); | |
98bfc474 | 799 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]); |
6bb192bc ML |
800 | g_free(cmd); |
801 | if (res != SR_OK) | |
802 | return SR_ERR; | |
bfaf112b | 803 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); |
6bb192bc ML |
804 | } |
805 | } | |
254dd102 BV |
806 | |
807 | /* Timebase. */ | |
334fbc2a | 808 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) |
254dd102 | 809 | return SR_ERR; |
bafd4890 | 810 | sr_dbg("Current timebase %g", devc->timebase); |
254dd102 BV |
811 | |
812 | /* Vertical gain. */ | |
821fbcad ML |
813 | for (i = 0; i < devc->model->analog_channels; i++) { |
814 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
334fbc2a | 815 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); |
821fbcad ML |
816 | g_free(cmd); |
817 | if (res != SR_OK) | |
818 | return SR_ERR; | |
819 | } | |
820 | sr_dbg("Current vertical gain:"); | |
821 | for (i = 0; i < devc->model->analog_channels; i++) | |
822 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
bafd4890 | 823 | |
254dd102 | 824 | /* Vertical offset. */ |
821fbcad ML |
825 | for (i = 0; i < devc->model->analog_channels; i++) { |
826 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
334fbc2a | 827 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); |
821fbcad ML |
828 | g_free(cmd); |
829 | if (res != SR_OK) | |
830 | return SR_ERR; | |
831 | } | |
832 | sr_dbg("Current vertical offset:"); | |
833 | for (i = 0; i < devc->model->analog_channels; i++) | |
834 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
254dd102 BV |
835 | |
836 | /* Coupling. */ | |
821fbcad ML |
837 | for (i = 0; i < devc->model->analog_channels; i++) { |
838 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
334fbc2a | 839 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); |
821fbcad ML |
840 | g_free(cmd); |
841 | if (res != SR_OK) | |
842 | return SR_ERR; | |
843 | } | |
844 | sr_dbg("Current coupling:"); | |
845 | for (i = 0; i < devc->model->analog_channels; i++) | |
846 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
254dd102 BV |
847 | |
848 | /* Trigger source. */ | |
334fbc2a | 849 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) |
254dd102 BV |
850 | return SR_ERR; |
851 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
852 | ||
853 | /* Horizontal trigger position. */ | |
334fbc2a | 854 | if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK) |
254dd102 | 855 | return SR_ERR; |
bafd4890 | 856 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); |
254dd102 BV |
857 | |
858 | /* Trigger slope. */ | |
334fbc2a | 859 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) |
254dd102 BV |
860 | return SR_ERR; |
861 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
862 | ||
863 | return SR_OK; | |
864 | } |