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f4816ac6 ML |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
88e429c9 | 5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
bafd4890 | 6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> |
f4816ac6 ML |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <stdlib.h> | |
e0b7d23c ML |
23 | #include <stdarg.h> |
24 | #include <unistd.h> | |
25 | #include <errno.h> | |
a3df166f | 26 | #include <string.h> |
254dd102 | 27 | #include <math.h> |
bafd4890 ML |
28 | #include <ctype.h> |
29 | #include <time.h> | |
f4816ac6 ML |
30 | #include <glib.h> |
31 | #include "libsigrok.h" | |
32 | #include "libsigrok-internal.h" | |
33 | #include "protocol.h" | |
34 | ||
bafd4890 ML |
35 | /* |
36 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
37 | * | |
38 | * DS1000 support tested with a Rigol DS1102D. | |
39 | * | |
40 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
41 | * | |
42 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
43 | * standard. If you want to read it - it costs real money... | |
44 | * | |
45 | * Every response from the scope has a linefeed appended because the | |
46 | * standard says so. In principle this could be ignored because sending the | |
47 | * next command clears the output queue of the scope. This driver tries to | |
48 | * avoid doing that because it may cause an error being generated inside the | |
49 | * scope and who knows what bugs the firmware has WRT this. | |
50 | * | |
51 | * Waveform data is transferred in a format called "arbitrary block program | |
52 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
53 | * 2000/3000 series scopes for a nice description. | |
54 | * | |
55 | * Each data block from the scope has a header, e.g. "#900000001400". | |
56 | * The '#' marks the start of a block. | |
57 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
58 | * ASCII decimal digits following. | |
59 | * Last are the ASCII decimal digits giving the number of bytes (not | |
60 | * samples!) in the block. | |
61 | * | |
62 | * After this header as many data bytes as indicated follow. | |
63 | * | |
64 | * Each data block has a trailing linefeed too. | |
65 | */ | |
66 | ||
bafd4890 ML |
67 | static int parse_int(const char *str, int *ret) |
68 | { | |
69 | char *e; | |
70 | long tmp; | |
71 | ||
72 | errno = 0; | |
73 | tmp = strtol(str, &e, 10); | |
74 | if (e == str || *e != '\0') { | |
75 | sr_dbg("Failed to parse integer: '%s'", str); | |
76 | return SR_ERR; | |
77 | } | |
78 | if (errno) { | |
79 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
80 | return SR_ERR; | |
81 | } | |
82 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
83 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
84 | return SR_ERR; | |
85 | } | |
86 | ||
87 | *ret = (int)tmp; | |
88 | return SR_OK; | |
89 | } | |
90 | ||
babab622 ML |
91 | /* Set the next event to wait for in rigol_ds_receive */ |
92 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
93 | { | |
94 | if (event == WAIT_STOP) | |
95 | devc->wait_status = 2; | |
96 | else | |
97 | devc->wait_status = 1; | |
98 | devc->wait_event = event; | |
99 | } | |
100 | ||
bafd4890 | 101 | /* |
babab622 ML |
102 | * Waiting for a event will return a timeout after 2 to 3 seconds in order |
103 | * to not block the application. | |
bafd4890 | 104 | */ |
babab622 | 105 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) |
bafd4890 | 106 | { |
334fbc2a | 107 | char *buf; |
bafd4890 ML |
108 | struct dev_context *devc; |
109 | time_t start; | |
110 | ||
111 | if (!(devc = sdi->priv)) | |
112 | return SR_ERR; | |
113 | ||
114 | start = time(NULL); | |
115 | ||
116 | /* | |
117 | * Trigger status may return: | |
babab622 ML |
118 | * "TD" or "T'D" - triggered |
119 | * "AUTO" - autotriggered | |
120 | * "RUN" - running | |
121 | * "WAIT" - waiting for trigger | |
122 | * "STOP" - stopped | |
bafd4890 ML |
123 | */ |
124 | ||
babab622 | 125 | if (devc->wait_status == 1) { |
bafd4890 ML |
126 | do { |
127 | if (time(NULL) - start >= 3) { | |
128 | sr_dbg("Timeout waiting for trigger"); | |
129 | return SR_ERR_TIMEOUT; | |
130 | } | |
131 | ||
334fbc2a | 132 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 133 | return SR_ERR; |
babab622 | 134 | } while (buf[0] == status1 || buf[0] == status2); |
bafd4890 | 135 | |
babab622 | 136 | devc->wait_status = 2; |
bafd4890 | 137 | } |
babab622 | 138 | if (devc->wait_status == 2) { |
bafd4890 ML |
139 | do { |
140 | if (time(NULL) - start >= 3) { | |
141 | sr_dbg("Timeout waiting for trigger"); | |
142 | return SR_ERR_TIMEOUT; | |
143 | } | |
144 | ||
334fbc2a | 145 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 146 | return SR_ERR; |
babab622 | 147 | } while (buf[0] != status1 && buf[0] != status2); |
bafd4890 | 148 | |
babab622 | 149 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
bafd4890 ML |
150 | } |
151 | ||
152 | return SR_OK; | |
153 | } | |
154 | ||
155 | /* | |
babab622 ML |
156 | * For live capture we need to wait for a new trigger event to ensure that |
157 | * sample data is not returned twice. | |
bafd4890 ML |
158 | * |
159 | * Unfortunately this will never really work because for sufficiently fast | |
babab622 | 160 | * timebases and trigger rates it just can't catch the status changes. |
bafd4890 ML |
161 | * |
162 | * What would be needed is a trigger event register with autoreset like the | |
163 | * Agilents have. The Rigols don't seem to have anything like this. | |
164 | * | |
165 | * The workaround is to only wait for the trigger when the timebase is slow | |
166 | * enough. Of course this means that for faster timebases sample data can be | |
babab622 ML |
167 | * returned multiple times, this effect is mitigated somewhat by sleeping |
168 | * for about one sweep time in that case. | |
bafd4890 | 169 | */ |
babab622 | 170 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) |
bafd4890 ML |
171 | { |
172 | struct dev_context *devc; | |
babab622 | 173 | long s; |
bafd4890 ML |
174 | |
175 | if (!(devc = sdi->priv)) | |
176 | return SR_ERR; | |
177 | ||
babab622 ML |
178 | /* |
179 | * If timebase < 50 msecs/DIV just sleep about one sweep time except | |
180 | * for really fast sweeps. | |
181 | */ | |
c2b394d5 | 182 | if (devc->timebase < 0.0499) { |
babab622 ML |
183 | if (devc->timebase > 0.99e-6) { |
184 | /* | |
185 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
186 | * -> 85 percent of sweep time | |
187 | */ | |
569d4dbd | 188 | s = (devc->timebase * devc->model->series->num_horizontal_divs |
babab622 ML |
189 | * 85e6) / 100L; |
190 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
191 | g_usleep(s); | |
192 | } | |
193 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
194 | return SR_OK; | |
195 | } else { | |
196 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
197 | } | |
198 | } | |
bafd4890 | 199 | |
babab622 ML |
200 | /* Wait for scope to got to "Stop" in single shot mode */ |
201 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
202 | { | |
203 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
204 | } | |
205 | ||
206 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
207 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
208 | { | |
209 | struct dev_context *devc; | |
821fbcad | 210 | struct sr_probe *probe; |
babab622 ML |
211 | int tmp; |
212 | ||
213 | if (!(devc = sdi->priv)) | |
bafd4890 | 214 | return SR_ERR; |
babab622 | 215 | |
821fbcad ML |
216 | probe = devc->channel_entry->data; |
217 | ||
569d4dbd | 218 | if (devc->model->series->protocol <= PROTOCOL_V2) |
e086b750 ML |
219 | return SR_OK; |
220 | ||
38354d9d | 221 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
821fbcad | 222 | probe->index + 1) != SR_OK) |
babab622 ML |
223 | return SR_ERR; |
224 | /* Check that the number of samples will be accepted */ | |
38354d9d | 225 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK) |
babab622 | 226 | return SR_ERR; |
334fbc2a | 227 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) |
bafd4890 | 228 | return SR_ERR; |
babab622 ML |
229 | /* |
230 | * If we get an "Execution error" the scope went from "Single" to | |
231 | * "Stop" without actually triggering. There is no waveform | |
232 | * displayed and trying to download one will fail - the scope thinks | |
233 | * it has 1400 samples (like display memory) and the driver thinks | |
234 | * it has a different number of samples. | |
235 | * | |
236 | * In that case just try to capture something again. Might still | |
237 | * fail in interesting ways. | |
238 | * | |
239 | * Ain't firmware fun? | |
240 | */ | |
241 | if (tmp & 0x10) { | |
242 | sr_warn("Single shot acquisition failed, retrying..."); | |
243 | /* Sleep a bit, otherwise the single shot will often fail */ | |
244 | g_usleep(500000); | |
38354d9d | 245 | rigol_ds_config_set(sdi, ":SING"); |
babab622 | 246 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
bafd4890 | 247 | return SR_ERR; |
babab622 | 248 | } |
bafd4890 | 249 | |
babab622 ML |
250 | return SR_OK; |
251 | } | |
bafd4890 | 252 | |
babab622 ML |
253 | /* Wait for enough data becoming available in scope output buffer */ |
254 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
255 | { | |
334fbc2a | 256 | char *buf; |
babab622 ML |
257 | struct dev_context *devc; |
258 | time_t start; | |
259 | int len; | |
260 | ||
261 | if (!(devc = sdi->priv)) | |
262 | return SR_ERR; | |
263 | ||
264 | start = time(NULL); | |
265 | ||
266 | do { | |
267 | if (time(NULL) - start >= 3) { | |
268 | sr_dbg("Timeout waiting for data block"); | |
269 | return SR_ERR_TIMEOUT; | |
270 | } | |
271 | ||
272 | /* | |
273 | * The scope copies data really slowly from sample | |
274 | * memory to its output buffer, so try not to bother | |
275 | * it too much with SCPI requests but don't wait too | |
276 | * long for short sample frame sizes. | |
277 | */ | |
278 | g_usleep(devc->analog_frame_size < 15000 ? 100000 : 1000000); | |
279 | ||
280 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
334fbc2a | 281 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) |
babab622 ML |
282 | return SR_ERR; |
283 | ||
284 | if (parse_int(buf + 5, &len) != SR_OK) | |
285 | return SR_ERR; | |
286 | } while (buf[0] == 'R' && len < 1000000); | |
287 | ||
288 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
289 | ||
290 | return SR_OK; | |
291 | } | |
292 | ||
38354d9d ML |
293 | /* Send a configuration setting. */ |
294 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
295 | { | |
296 | struct dev_context *devc = sdi->priv; | |
297 | va_list args; | |
298 | int ret; | |
299 | ||
300 | va_start(args, format); | |
301 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
302 | va_end(args); | |
303 | ||
304 | if (ret != SR_OK) | |
305 | return SR_ERR; | |
306 | ||
569d4dbd | 307 | if (devc->model->series->protocol == PROTOCOL_V2) { |
38354d9d ML |
308 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ |
309 | sr_spew("delay %dms", 100); | |
310 | g_usleep(100000); | |
311 | return SR_OK; | |
312 | } else { | |
313 | return sr_scpi_get_opc(sdi->conn); | |
314 | } | |
315 | } | |
316 | ||
babab622 ML |
317 | /* Start capturing a new frameset */ |
318 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
319 | { | |
320 | struct dev_context *devc; | |
e086b750 | 321 | gchar *trig_mode; |
babab622 ML |
322 | |
323 | if (!(devc = sdi->priv)) | |
324 | return SR_ERR; | |
325 | ||
326 | sr_dbg("Starting data capture for frameset %lu of %lu", | |
327 | devc->num_frames + 1, devc->limit_frames); | |
328 | ||
569d4dbd ML |
329 | switch (devc->model->series->protocol) { |
330 | case PROTOCOL_V1: | |
331 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
332 | break; | |
333 | case PROTOCOL_V2: | |
334 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
335 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
e086b750 | 336 | return SR_ERR; |
569d4dbd | 337 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 338 | } else { |
e086b750 ML |
339 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) |
340 | return SR_ERR; | |
341 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
342 | return SR_ERR; | |
343 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
344 | return SR_ERR; | |
345 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
346 | return SR_ERR; | |
347 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
348 | return SR_ERR; | |
569d4dbd ML |
349 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
350 | } | |
351 | break; | |
352 | case PROTOCOL_V3: | |
353 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) | |
354 | return SR_ERR; | |
355 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
356 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
357 | return SR_ERR; | |
358 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
e086b750 ML |
359 | } else { |
360 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
361 | return SR_ERR; | |
362 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) | |
363 | return SR_ERR; | |
569d4dbd | 364 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
e086b750 | 365 | } |
569d4dbd | 366 | break; |
bafd4890 ML |
367 | } |
368 | ||
369 | return SR_OK; | |
370 | } | |
371 | ||
babab622 ML |
372 | /* Start reading data from the current channel */ |
373 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
374 | { | |
375 | struct dev_context *devc; | |
821fbcad | 376 | struct sr_probe *probe; |
babab622 ML |
377 | |
378 | if (!(devc = sdi->priv)) | |
379 | return SR_ERR; | |
380 | ||
821fbcad ML |
381 | probe = devc->channel_entry->data; |
382 | ||
383 | sr_dbg("Starting reading data from channel %d", probe->index + 1); | |
babab622 | 384 | |
569d4dbd | 385 | if (devc->model->series->protocol <= PROTOCOL_V2) { |
821fbcad | 386 | if (probe->type == SR_PROBE_LOGIC) { |
677f85d0 ML |
387 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) |
388 | return SR_ERR; | |
389 | } else { | |
821fbcad ML |
390 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", |
391 | probe->index + 1) != SR_OK) | |
677f85d0 ML |
392 | return SR_ERR; |
393 | } | |
e086b750 | 394 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
677f85d0 | 395 | } else { |
38354d9d | 396 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
821fbcad | 397 | probe->index + 1) != SR_OK) |
babab622 | 398 | return SR_ERR; |
677f85d0 | 399 | if (devc->data_source != DATA_SOURCE_LIVE) { |
38354d9d | 400 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) |
677f85d0 | 401 | return SR_ERR; |
38354d9d | 402 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) |
677f85d0 | 403 | return SR_ERR; |
aff00e40 | 404 | } |
677f85d0 | 405 | } |
babab622 | 406 | |
aff00e40 ML |
407 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
408 | ||
f76c24f6 | 409 | devc->num_channel_bytes = 0; |
aff00e40 | 410 | devc->num_header_bytes = 0; |
babab622 ML |
411 | devc->num_block_bytes = 0; |
412 | ||
413 | return SR_OK; | |
414 | } | |
415 | ||
416 | /* Read the header of a data block */ | |
aff00e40 | 417 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) |
bafd4890 | 418 | { |
aff00e40 ML |
419 | struct sr_scpi_dev_inst *scpi = sdi->conn; |
420 | struct dev_context *devc = sdi->priv; | |
421 | char *buf = (char *) devc->buffer; | |
422 | int len; | |
423 | int tmp; | |
424 | ||
425 | /* Try to read the hashsign and length digit. */ | |
426 | if (devc->num_header_bytes < 2) { | |
427 | tmp = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
428 | 2 - devc->num_header_bytes); | |
429 | if (tmp < 0) { | |
430 | sr_err("Read error while reading data header."); | |
431 | return SR_ERR; | |
432 | } | |
433 | devc->num_header_bytes += tmp; | |
bafd4890 | 434 | } |
aff00e40 ML |
435 | |
436 | if (devc->num_header_bytes < 2) | |
437 | return 0; | |
438 | ||
439 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
440 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
441 | return SR_ERR; | |
bafd4890 | 442 | } |
bafd4890 | 443 | |
aff00e40 ML |
444 | len = buf[1] - '0'; |
445 | ||
446 | /* Try to read the length. */ | |
447 | if (devc->num_header_bytes < 2 + len) { | |
448 | tmp = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
449 | 2 + len - devc->num_header_bytes); | |
450 | if (tmp < 0) { | |
451 | sr_err("Read error while reading data header."); | |
452 | return SR_ERR; | |
453 | } | |
454 | devc->num_header_bytes += tmp; | |
bafd4890 | 455 | } |
aff00e40 ML |
456 | |
457 | if (devc->num_header_bytes < 2 + len) | |
458 | return 0; | |
459 | ||
460 | /* Read the data length. */ | |
461 | buf[2 + len] = '\0'; | |
462 | ||
463 | if (parse_int(buf + 2, &len) != SR_OK) { | |
464 | sr_err("Received invalid data block length '%s'.", buf + 2); | |
bafd4890 ML |
465 | return -1; |
466 | } | |
467 | ||
aff00e40 | 468 | sr_dbg("Received data block header: '%s' -> block length %d", buf, len); |
bafd4890 ML |
469 | |
470 | return len; | |
471 | } | |
472 | ||
3086efdd | 473 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) |
f4816ac6 | 474 | { |
e0b7d23c | 475 | struct sr_dev_inst *sdi; |
ae1bc1cc | 476 | struct sr_scpi_dev_inst *scpi; |
f4816ac6 | 477 | struct dev_context *devc; |
e0b7d23c ML |
478 | struct sr_datafeed_packet packet; |
479 | struct sr_datafeed_analog analog; | |
6bb192bc | 480 | struct sr_datafeed_logic logic; |
254dd102 | 481 | double vdiv, offset; |
f80a0bf2 | 482 | int len, i, vref; |
6bb192bc | 483 | struct sr_probe *probe; |
bac11aeb | 484 | gsize expected_data_bytes; |
f4816ac6 | 485 | |
decfe89d | 486 | (void)fd; |
9bd4c956 | 487 | |
f4816ac6 ML |
488 | if (!(sdi = cb_data)) |
489 | return TRUE; | |
490 | ||
491 | if (!(devc = sdi->priv)) | |
492 | return TRUE; | |
493 | ||
ae1bc1cc | 494 | scpi = sdi->conn; |
9bd4c956 | 495 | |
d5876cfb | 496 | if (revents == G_IO_IN || revents == 0) { |
e086b750 ML |
497 | switch(devc->wait_event) { |
498 | case WAIT_NONE: | |
499 | break; | |
500 | case WAIT_TRIGGER: | |
501 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
bafd4890 | 502 | return TRUE; |
e086b750 ML |
503 | if (rigol_ds_channel_start(sdi) != SR_OK) |
504 | return TRUE; | |
505 | break; | |
506 | case WAIT_BLOCK: | |
507 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
508 | return TRUE; | |
509 | break; | |
510 | case WAIT_STOP: | |
511 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
512 | return TRUE; | |
513 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
514 | return TRUE; | |
515 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
516 | return TRUE; | |
517 | return TRUE; | |
518 | default: | |
519 | sr_err("BUG: Unknown event target encountered"); | |
f80a0bf2 ML |
520 | } |
521 | ||
821fbcad | 522 | probe = devc->channel_entry->data; |
bac11aeb ML |
523 | |
524 | expected_data_bytes = probe->type == SR_PROBE_ANALOG ? | |
525 | devc->analog_frame_size : devc->digital_frame_size; | |
f76c24f6 | 526 | |
e086b750 | 527 | if (devc->num_block_bytes == 0) { |
569d4dbd | 528 | if (devc->model->series->protocol >= PROTOCOL_V3) |
a53278de AJ |
529 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) |
530 | return TRUE; | |
bac11aeb | 531 | |
05c644ea ML |
532 | if (sr_scpi_read_begin(scpi) != SR_OK) |
533 | return TRUE; | |
bac11aeb | 534 | |
569d4dbd | 535 | if (devc->format == FORMAT_IEEE488_2) { |
babab622 | 536 | sr_dbg("New block header expected"); |
aff00e40 ML |
537 | len = rigol_ds_read_header(sdi); |
538 | if (len == 0) | |
539 | /* Still reading the header. */ | |
540 | return TRUE; | |
541 | if (len == -1) { | |
542 | sr_err("Read error, aborting capture."); | |
543 | packet.type = SR_DF_FRAME_END; | |
544 | sr_session_send(cb_data, &packet); | |
545 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
babab622 | 546 | return TRUE; |
aff00e40 | 547 | } |
babab622 ML |
548 | /* At slow timebases in live capture the DS2072 |
549 | * sometimes returns "short" data blocks, with | |
550 | * apparently no way to get the rest of the data. | |
551 | * Discard these, the complete data block will | |
552 | * appear eventually. | |
553 | */ | |
554 | if (devc->data_source == DATA_SOURCE_LIVE | |
bac11aeb | 555 | && (unsigned)len < expected_data_bytes) { |
babab622 | 556 | sr_dbg("Discarding short data block"); |
05c644ea | 557 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); |
babab622 ML |
558 | return TRUE; |
559 | } | |
560 | devc->num_block_bytes = len; | |
f80a0bf2 | 561 | } else { |
bac11aeb | 562 | devc->num_block_bytes = expected_data_bytes; |
f80a0bf2 ML |
563 | } |
564 | devc->num_block_read = 0; | |
bafd4890 | 565 | } |
f80a0bf2 ML |
566 | |
567 | len = devc->num_block_bytes - devc->num_block_read; | |
ae3a1913 ML |
568 | if (len > ACQ_BUFFER_SIZE) |
569 | len = ACQ_BUFFER_SIZE; | |
570 | sr_dbg("Requesting read of %d bytes", len); | |
571 | ||
572 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); | |
f80a0bf2 | 573 | |
7d63347e ML |
574 | if (len == -1) { |
575 | sr_err("Read error, aborting capture."); | |
576 | packet.type = SR_DF_FRAME_END; | |
577 | sr_session_send(cb_data, &packet); | |
578 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
579 | return TRUE; | |
580 | } | |
ae3a1913 ML |
581 | |
582 | sr_dbg("Received %d bytes.", len); | |
75d8a4e5 | 583 | |
48460c6f ML |
584 | devc->num_block_read += len; |
585 | ||
6bb192bc | 586 | if (probe->type == SR_PROBE_ANALOG) { |
bafd4890 ML |
587 | vref = devc->vert_reference[probe->index]; |
588 | vdiv = devc->vdiv[probe->index] / 25.6; | |
589 | offset = devc->vert_offset[probe->index]; | |
569d4dbd | 590 | if (devc->model->series->protocol >= PROTOCOL_V3) |
bafd4890 | 591 | for (i = 0; i < len; i++) |
babab622 | 592 | devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset; |
bafd4890 ML |
593 | else |
594 | for (i = 0; i < len; i++) | |
babab622 | 595 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; |
6bb192bc ML |
596 | analog.probes = g_slist_append(NULL, probe); |
597 | analog.num_samples = len; | |
babab622 | 598 | analog.data = devc->data; |
6bb192bc ML |
599 | analog.mq = SR_MQ_VOLTAGE; |
600 | analog.unit = SR_UNIT_VOLT; | |
601 | analog.mqflags = 0; | |
602 | packet.type = SR_DF_ANALOG; | |
603 | packet.payload = &analog; | |
604 | sr_session_send(cb_data, &packet); | |
605 | g_slist_free(analog.probes); | |
6bb192bc | 606 | } else { |
470140fc | 607 | logic.length = len; |
6bb192bc | 608 | logic.unitsize = 2; |
470140fc | 609 | logic.data = devc->buffer; |
6bb192bc ML |
610 | packet.type = SR_DF_LOGIC; |
611 | packet.payload = &logic; | |
612 | sr_session_send(cb_data, &packet); | |
48460c6f | 613 | } |
6bb192bc | 614 | |
48460c6f ML |
615 | if (devc->num_block_read == devc->num_block_bytes) { |
616 | sr_dbg("Block has been completed"); | |
2b399703 | 617 | if (devc->model->series->protocol >= PROTOCOL_V3) { |
470140fc | 618 | /* Discard the terminating linefeed */ |
05c644ea | 619 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); |
2b399703 ML |
620 | } |
621 | if (devc->format == FORMAT_IEEE488_2) { | |
470140fc | 622 | /* Prepare for possible next block */ |
aff00e40 | 623 | devc->num_header_bytes = 0; |
48460c6f ML |
624 | devc->num_block_bytes = 0; |
625 | if (devc->data_source != DATA_SOURCE_LIVE) | |
626 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); | |
627 | } | |
3ed7a40c ML |
628 | if (!sr_scpi_read_complete(scpi)) { |
629 | sr_err("Read should have been completed"); | |
7d63347e ML |
630 | packet.type = SR_DF_FRAME_END; |
631 | sr_session_send(cb_data, &packet); | |
3ed7a40c ML |
632 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
633 | return TRUE; | |
634 | } | |
48460c6f ML |
635 | devc->num_block_read = 0; |
636 | } else { | |
637 | sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes); | |
ee7e9bee | 638 | } |
75d8a4e5 | 639 | |
f76c24f6 | 640 | devc->num_channel_bytes += len; |
48460c6f | 641 | |
f76c24f6 ML |
642 | if (devc->num_channel_bytes < expected_data_bytes) |
643 | /* Don't have the full data for this channel yet, re-run. */ | |
48460c6f ML |
644 | return TRUE; |
645 | ||
f76c24f6 | 646 | /* End of data for this channel. */ |
569d4dbd | 647 | if (devc->model->series->protocol >= PROTOCOL_V3) { |
babab622 ML |
648 | /* Signal end of data download to scope */ |
649 | if (devc->data_source != DATA_SOURCE_LIVE) | |
650 | /* | |
651 | * This causes a query error, without it switching | |
652 | * to the next channel causes an error. Fun with | |
653 | * firmware... | |
654 | */ | |
38354d9d | 655 | rigol_ds_config_set(sdi, ":WAV:END"); |
babab622 | 656 | } |
254dd102 | 657 | |
821fbcad ML |
658 | if (probe->type == SR_PROBE_ANALOG |
659 | && devc->channel_entry->next != NULL) { | |
660 | /* We got the frame for this analog channel, but | |
661 | * there's another analog channel. */ | |
662 | devc->channel_entry = devc->channel_entry->next; | |
677f85d0 | 663 | rigol_ds_channel_start(sdi); |
254dd102 | 664 | } else { |
821fbcad | 665 | /* Done with all analog channels in this frame. */ |
6bb192bc | 666 | if (devc->enabled_digital_probes |
821fbcad | 667 | && devc->channel_entry != devc->enabled_digital_probes) { |
6bb192bc | 668 | /* Now we need to get the digital data. */ |
821fbcad | 669 | devc->channel_entry = devc->enabled_digital_probes; |
677f85d0 | 670 | rigol_ds_channel_start(sdi); |
254dd102 | 671 | } else { |
f76c24f6 ML |
672 | /* Done with this frame. */ |
673 | packet.type = SR_DF_FRAME_END; | |
674 | sr_session_send(cb_data, &packet); | |
675 | ||
676 | if (++devc->num_frames == devc->limit_frames) { | |
677 | /* Last frame, stop capture. */ | |
678 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
679 | } else { | |
680 | /* Get the next frame, starting with the first analog channel. */ | |
681 | if (devc->enabled_analog_probes) | |
682 | devc->channel_entry = devc->enabled_analog_probes; | |
683 | else | |
684 | devc->channel_entry = devc->enabled_digital_probes; | |
685 | ||
e086b750 | 686 | rigol_ds_capture_start(sdi); |
f76c24f6 ML |
687 | |
688 | /* Start of next frame. */ | |
689 | packet.type = SR_DF_FRAME_BEGIN; | |
690 | sr_session_send(cb_data, &packet); | |
691 | } | |
254dd102 | 692 | } |
75d8a4e5 | 693 | } |
f4816ac6 ML |
694 | } |
695 | ||
696 | return TRUE; | |
697 | } | |
e0b7d23c | 698 | |
3086efdd | 699 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) |
254dd102 BV |
700 | { |
701 | struct dev_context *devc; | |
6bb192bc | 702 | char *t_s, *cmd; |
821fbcad ML |
703 | unsigned int i; |
704 | int res; | |
254dd102 BV |
705 | |
706 | devc = sdi->priv; | |
707 | ||
6bb192bc | 708 | /* Analog channel state. */ |
821fbcad ML |
709 | for (i = 0; i < devc->model->analog_channels; i++) { |
710 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
334fbc2a | 711 | res = sr_scpi_get_string(sdi->conn, cmd, &t_s); |
821fbcad ML |
712 | g_free(cmd); |
713 | if (res != SR_OK) | |
714 | return SR_ERR; | |
715 | devc->analog_channels[i] = !strcmp(t_s, "ON") || !strcmp(t_s, "1"); | |
716 | } | |
717 | sr_dbg("Current analog channel state:"); | |
718 | for (i = 0; i < devc->model->analog_channels; i++) | |
719 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
6bb192bc ML |
720 | |
721 | /* Digital channel state. */ | |
bafd4890 | 722 | if (devc->model->has_digital) { |
334fbc2a | 723 | if (sr_scpi_get_string(sdi->conn, ":LA:DISP?", &t_s) != SR_OK) |
04e8e01e ML |
724 | return SR_ERR; |
725 | devc->la_enabled = !strcmp(t_s, "ON") ? TRUE : FALSE; | |
726 | sr_dbg("Logic analyzer %s, current digital channel state:", | |
727 | devc->la_enabled ? "enabled" : "disabled"); | |
6bb192bc | 728 | for (i = 0; i < 16; i++) { |
bfaf112b | 729 | cmd = g_strdup_printf(":DIG%d:TURN?", i); |
334fbc2a | 730 | res = sr_scpi_get_string(sdi->conn, cmd, &t_s); |
6bb192bc ML |
731 | g_free(cmd); |
732 | if (res != SR_OK) | |
733 | return SR_ERR; | |
734 | devc->digital_channels[i] = !strcmp(t_s, "ON") ? TRUE : FALSE; | |
735 | g_free(t_s); | |
bfaf112b | 736 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); |
6bb192bc ML |
737 | } |
738 | } | |
254dd102 BV |
739 | |
740 | /* Timebase. */ | |
334fbc2a | 741 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) |
254dd102 | 742 | return SR_ERR; |
bafd4890 | 743 | sr_dbg("Current timebase %g", devc->timebase); |
254dd102 BV |
744 | |
745 | /* Vertical gain. */ | |
821fbcad ML |
746 | for (i = 0; i < devc->model->analog_channels; i++) { |
747 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
334fbc2a | 748 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); |
821fbcad ML |
749 | g_free(cmd); |
750 | if (res != SR_OK) | |
751 | return SR_ERR; | |
752 | } | |
753 | sr_dbg("Current vertical gain:"); | |
754 | for (i = 0; i < devc->model->analog_channels; i++) | |
755 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
bafd4890 | 756 | |
821fbcad | 757 | sr_dbg("Current vertical reference:"); |
569d4dbd | 758 | if (devc->model->series->protocol >= PROTOCOL_V3) { |
bafd4890 | 759 | /* Vertical reference - not certain if this is the place to read it. */ |
821fbcad | 760 | for (i = 0; i < devc->model->analog_channels; i++) { |
38354d9d | 761 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", i + 1) != SR_OK) |
821fbcad | 762 | return SR_ERR; |
334fbc2a | 763 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", &devc->vert_reference[i]) != SR_OK) |
821fbcad ML |
764 | return SR_ERR; |
765 | sr_dbg("CH%d %d", i + 1, devc->vert_reference[i]); | |
766 | } | |
bafd4890 | 767 | } |
254dd102 BV |
768 | |
769 | /* Vertical offset. */ | |
821fbcad ML |
770 | for (i = 0; i < devc->model->analog_channels; i++) { |
771 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
334fbc2a | 772 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); |
821fbcad ML |
773 | g_free(cmd); |
774 | if (res != SR_OK) | |
775 | return SR_ERR; | |
776 | } | |
777 | sr_dbg("Current vertical offset:"); | |
778 | for (i = 0; i < devc->model->analog_channels; i++) | |
779 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
254dd102 BV |
780 | |
781 | /* Coupling. */ | |
821fbcad ML |
782 | for (i = 0; i < devc->model->analog_channels; i++) { |
783 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
334fbc2a | 784 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); |
821fbcad ML |
785 | g_free(cmd); |
786 | if (res != SR_OK) | |
787 | return SR_ERR; | |
788 | } | |
789 | sr_dbg("Current coupling:"); | |
790 | for (i = 0; i < devc->model->analog_channels; i++) | |
791 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
254dd102 BV |
792 | |
793 | /* Trigger source. */ | |
334fbc2a | 794 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) |
254dd102 BV |
795 | return SR_ERR; |
796 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
797 | ||
798 | /* Horizontal trigger position. */ | |
334fbc2a | 799 | if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK) |
254dd102 | 800 | return SR_ERR; |
bafd4890 | 801 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); |
254dd102 BV |
802 | |
803 | /* Trigger slope. */ | |
334fbc2a | 804 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) |
254dd102 BV |
805 | return SR_ERR; |
806 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
807 | ||
808 | return SR_OK; | |
809 | } |