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kingst-la2016: rephrase samplerate list code path, prepare 500MHz
[libsigrok.git] / src / hardware / kingst-la2016 / protocol.h
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#ifndef LIBSIGROK_HARDWARE_KINGST_LA2016_PROTOCOL_H
24#define LIBSIGROK_HARDWARE_KINGST_LA2016_PROTOCOL_H
25
f2cd2deb 26#include <libsigrok/libsigrok.h>
a7740b06 27#include <stdint.h>
f2cd2deb 28
e9430410 29#define LOG_PREFIX "kingst-la2016"
f2cd2deb 30
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31#define LA2016_VID 0x77a1
32#define LA2016_PID 0x01a2
852c7d14 33#define LA2016_IPRODUCT_INDEX 2
f2cd2deb 34#define USB_INTERFACE 0
40a0b2f4 35#define USB_CONFIGURATION 1
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36#define USB_EP_FPGA_BITSTREAM 2
37#define USB_EP_CAPTURE_DATA 6
f2cd2deb 38
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39/*
40 * On Windows sigrok uses WinUSB RAW_IO policy which requires the
41 * USB transfer buffer size to be a multiple of the endpoint max packet
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42 * size, which is 512 bytes in this case. Also, the maximum allowed size
43 * of the transfer buffer is normally read from WinUSB_GetPipePolicy API
44 * but libusb does not expose this function. Typically, max size is 2MB.
e847645b 45 */
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46#define LA2016_EP6_PKTSZ 512 /* Max packet size of USB endpoint 6. */
47#define LA2016_USB_BUFSZ (256 * 2 * LA2016_EP6_PKTSZ) /* 256KiB buffer. */
e847645b 48
22cb067a 49/* USB communication timeout during regular operation. */
e9430410 50#define DEFAULT_TIMEOUT_MS 200
f2cd2deb 51
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52/*
53 * Check for MCU firmware to take effect after upload. Check the device
54 * presence for a maximum period of time, delay between checks in that
55 * phase. Allow for the device to vanish after upload and before checks,
56 * to not mistake its earlier incarnation for the successful operation
57 * of the most recently loaded firmware.
58 */
59#define RENUM_CHECK_PERIOD_MS 3000
60#define RENUM_GONE_DELAY_MS 1800
61#define RENUM_POLL_INTERVAL_MS 200
62
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63/*
64 * The device expects some zero padding to follow the content of the
65 * file which contains the FPGA bitstream. Specify the chunk size here.
66 */
67#define LA2016_EP2_PADDING 2048
68
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69#define LA2016_THR_VOLTAGE_MIN 0.40
70#define LA2016_THR_VOLTAGE_MAX 4.00
f2cd2deb 71
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72#define LA2016_NUM_SAMPLES_MIN (UINT64_C(256))
73#define LA2016_NUM_SAMPLES_MAX (UINT64_C(10 * 1000 * 1000 * 1000))
74
75/* Maximum device capabilities. May differ between models. */
76#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
77#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
78#define MIN_SAMPLE_RATE_LA2016 SR_KHZ(10)
79#define MAX_PWM_FREQ SR_MHZ(20)
80#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */
81
82/* TODO
83 * What is the origin and motivation of that 128Mi literal? What is its
84 * unit? How does it relate to a device's hardware capabilities? How to
85 * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value?
86 * It cannot be sample count. Is it memory size in bytes perhaps?
87 */
88#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024)
f2cd2deb 89
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90#define LA2016_NUM_PWMCH_MAX 2
91
92#define LA2016_CONVBUFFER_SIZE (4 * 1024 * 1024)
93
66f5f697 94struct pwm_setting_dev {
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95 uint32_t period;
96 uint32_t duty;
66f5f697 97};
f2cd2deb 98
66f5f697 99struct trigger_cfg {
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100 uint32_t channels;
101 uint32_t enabled;
102 uint32_t level;
103 uint32_t high_or_falling;
66f5f697 104};
f2cd2deb 105
66f5f697 106struct capture_info {
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107 uint32_t n_rep_packets;
108 uint32_t n_rep_packets_before_trigger;
109 uint32_t write_pos;
66f5f697 110};
f2cd2deb 111
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112#define NUM_PACKETS_IN_CHUNK 5
113#define TRANSFER_PACKET_LENGTH 16
f2cd2deb 114
66f5f697 115struct pwm_setting {
86d77b75 116 gboolean enabled;
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117 float freq;
118 float duty;
66f5f697 119};
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120
121struct dev_context {
520a20e9 122 uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
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123
124 /* User specified parameters. */
66f5f697 125 struct pwm_setting pwm_setting[LA2016_NUM_PWMCH_MAX];
5eb1b63d 126 size_t threshold_voltage_idx;
f2cd2deb 127 float threshold_voltage;
8b172e78 128 uint64_t max_samplerate;
f2cd2deb 129 uint64_t cur_samplerate;
a38f0f5e 130 struct sr_sw_limits sw_limits;
f2cd2deb 131 uint64_t capture_ratio;
f2cd2deb 132
96dc954e 133 /* Internal acquisition and download state. */
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134 gboolean trigger_involved;
135 gboolean completion_seen;
136 gboolean download_finished;
66f5f697 137 struct capture_info info;
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138 uint32_t n_transfer_packets_to_read; /* each with 5 acq packets */
139 uint32_t n_bytes_to_read;
140 uint32_t n_reps_until_trigger;
cf057ac4 141 gboolean trigger_marked;
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142 uint64_t total_samples;
143 uint32_t read_pos;
144
a38f0f5e 145 struct feed_queue_logic *feed_queue;
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146 struct libusb_transfer *transfer;
147};
148
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149SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx,
150 libusb_device *dev, uint16_t product_id);
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151SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi);
152SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi);
f2cd2deb 153SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi);
388438e4 154SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data);
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155SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi);
156SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi);
157
f2cd2deb 158#endif