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3b533202 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
3b533202 BV |
3 | * |
4 | * Copyright (C) 2012 Bert Vermeulen <bert@biot.com> | |
5 | * With protocol information from the hantekdso project, | |
6 | * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
ce4d26dd UH |
22 | #ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_DSO_H |
23 | #define LIBSIGROK_HARDWARE_HANTEK_DSO_DSO_H | |
3b533202 | 24 | |
3544f848 | 25 | #define LOG_PREFIX "hantek-dso" |
cbc6f3b2 | 26 | |
8c971b6e BV |
27 | #define USB_INTERFACE 0 |
28 | #define USB_CONFIGURATION 1 | |
29 | #define DSO_EP_IN 0x86 | |
30 | #define DSO_EP_OUT 0x02 | |
3b533202 BV |
31 | |
32 | /* FX2 renumeration delay in ms */ | |
8c971b6e | 33 | #define MAX_RENUM_DELAY_MS 3000 |
3b533202 | 34 | |
8c971b6e | 35 | #define MAX_CAPTURE_EMPTY 3 |
3b533202 | 36 | |
8c971b6e BV |
37 | #define DEFAULT_VOLTAGE VDIV_500MV |
38 | #define DEFAULT_FRAMESIZE FRAMESIZE_SMALL | |
39 | #define DEFAULT_TIMEBASE TIME_100us | |
40 | #define DEFAULT_TRIGGER_SOURCE "CH1" | |
41 | #define DEFAULT_COUPLING COUPLING_DC | |
42 | #define DEFAULT_HORIZ_TRIGGERPOS 0.5 | |
43 | #define DEFAULT_VERT_OFFSET 0.5 | |
44 | #define DEFAULT_VERT_TRIGGERPOS 0.5 | |
3b533202 | 45 | |
8c971b6e | 46 | #define MAX_VERT_TRIGGER 0xfe |
3b533202 BV |
47 | |
48 | /* Hantek DSO-specific protocol values */ | |
8c971b6e | 49 | #define EEPROM_CHANNEL_OFFSETS 0x08 |
3b533202 | 50 | |
034accb5 | 51 | /* All models have this for their "fast" mode. */ |
1a46cc62 | 52 | #define FRAMESIZE_SMALL (10 * 1024) |
3b533202 BV |
53 | |
54 | enum control_requests { | |
55 | CTRL_READ_EEPROM = 0xa2, | |
56 | CTRL_GETSPEED = 0xb2, | |
57 | CTRL_BEGINCOMMAND = 0xb3, | |
58 | CTRL_SETOFFSET = 0xb4, | |
e98b7f1b | 59 | CTRL_SETRELAYS = 0xb5, |
3b533202 BV |
60 | }; |
61 | ||
62 | enum dso_commands { | |
63 | CMD_SET_FILTERS = 0, | |
64 | CMD_SET_TRIGGER_SAMPLERATE, | |
65 | CMD_FORCE_TRIGGER, | |
66 | CMD_CAPTURE_START, | |
67 | CMD_ENABLE_TRIGGER, | |
68 | CMD_GET_CHANNELDATA, | |
69 | CMD_GET_CAPTURESTATE, | |
70 | CMD_SET_VOLTAGE, | |
313deed2 | 71 | /* unused */ |
ce4d26dd UH |
72 | CMD_SET_LOGICALDATA, |
73 | CMD_GET_LOGICALDATA, | |
3b533202 BV |
74 | }; |
75 | ||
b58fbd99 | 76 | /* Must match the coupling table. */ |
3b533202 BV |
77 | enum couplings { |
78 | COUPLING_AC = 0, | |
79 | COUPLING_DC, | |
2715c0b8 | 80 | /* TODO not used, how to enable? */ |
e98b7f1b | 81 | COUPLING_GND, |
3b533202 BV |
82 | }; |
83 | ||
b58fbd99 | 84 | /* Must match the timebases table. */ |
3b533202 BV |
85 | enum time_bases { |
86 | TIME_10us = 0, | |
87 | TIME_20us, | |
88 | TIME_40us, | |
89 | TIME_100us, | |
90 | TIME_200us, | |
91 | TIME_400us, | |
92 | TIME_1ms, | |
93 | TIME_2ms, | |
94 | TIME_4ms, | |
95 | TIME_10ms, | |
96 | TIME_20ms, | |
97 | TIME_40ms, | |
98 | TIME_100ms, | |
99 | TIME_200ms, | |
e98b7f1b | 100 | TIME_400ms, |
3b533202 BV |
101 | }; |
102 | ||
b58fbd99 | 103 | /* Must match the vdivs table. */ |
313deed2 BV |
104 | enum { |
105 | VDIV_10MV, | |
106 | VDIV_20MV, | |
107 | VDIV_50MV, | |
108 | VDIV_100MV, | |
109 | VDIV_200MV, | |
110 | VDIV_500MV, | |
111 | VDIV_1V, | |
112 | VDIV_2V, | |
113 | VDIV_5V, | |
114 | }; | |
115 | ||
3b533202 BV |
116 | enum trigger_slopes { |
117 | SLOPE_POSITIVE = 0, | |
e98b7f1b | 118 | SLOPE_NEGATIVE, |
3b533202 BV |
119 | }; |
120 | ||
121 | enum trigger_sources { | |
122 | TRIGGER_CH2 = 0, | |
123 | TRIGGER_CH1, | |
3b533202 | 124 | TRIGGER_EXT, |
3b533202 BV |
125 | }; |
126 | ||
3b533202 BV |
127 | enum capturestates { |
128 | CAPTURE_EMPTY = 0, | |
129 | CAPTURE_FILLING = 1, | |
130 | CAPTURE_READY_8BIT = 2, | |
131 | CAPTURE_READY_9BIT = 7, | |
132 | CAPTURE_TIMEOUT = 127, | |
e98b7f1b | 133 | CAPTURE_UNKNOWN = 255, |
3b533202 BV |
134 | }; |
135 | ||
136 | enum triggermodes { | |
137 | TRIGGERMODE_AUTO, | |
138 | TRIGGERMODE_NORMAL, | |
e98b7f1b | 139 | TRIGGERMODE_SINGLE, |
3b533202 BV |
140 | }; |
141 | ||
142 | enum states { | |
143 | IDLE, | |
144 | NEW_CAPTURE, | |
145 | CAPTURE, | |
a3508e33 BV |
146 | FETCH_DATA, |
147 | STOPPING, | |
3b533202 BV |
148 | }; |
149 | ||
150 | struct dso_profile { | |
151 | /* VID/PID after cold boot */ | |
152 | uint16_t orig_vid; | |
153 | uint16_t orig_pid; | |
154 | /* VID/PID after firmware upload */ | |
155 | uint16_t fw_vid; | |
156 | uint16_t fw_pid; | |
157 | char *vendor; | |
158 | char *model; | |
034accb5 | 159 | const uint64_t *buffersizes; |
3b533202 BV |
160 | char *firmware; |
161 | }; | |
162 | ||
269971dd | 163 | struct dev_context { |
62bb8840 | 164 | const struct dso_profile *profile; |
3b533202 | 165 | void *cb_data; |
ae88b97b BV |
166 | uint64_t limit_frames; |
167 | uint64_t num_frames; | |
ba7dd8bb | 168 | GSList *enabled_channels; |
3b533202 BV |
169 | /* We can't keep track of an FX2-based device after upgrading |
170 | * the firmware (it re-enumerates into a different device address | |
171 | * after the upgrade) this is like a global lock. No device will open | |
172 | * until a proper delay after the last device was upgraded. | |
173 | */ | |
fc8fe3e3 | 174 | int64_t fw_updated; |
3b533202 BV |
175 | int epin_maxpacketsize; |
176 | int capture_empty_count; | |
3b533202 BV |
177 | int dev_state; |
178 | ||
e749a8cb | 179 | /* Oscilloscope settings. */ |
3b533202 BV |
180 | int timebase; |
181 | gboolean ch1_enabled; | |
182 | gboolean ch2_enabled; | |
933defaa BV |
183 | int voltage[2]; |
184 | int coupling[2]; | |
3b533202 BV |
185 | // voltage offset (vertical position) |
186 | float voffset_ch1; | |
187 | float voffset_ch2; | |
188 | float voffset_trigger; | |
189 | uint16_t channel_levels[2][9][2]; | |
e749a8cb | 190 | unsigned int framesize; |
933defaa | 191 | gboolean filter[2]; |
3b533202 | 192 | int triggerslope; |
a370ef19 | 193 | char *triggersource; |
bc79e906 | 194 | float triggerposition; |
3b533202 | 195 | int triggermode; |
e749a8cb BV |
196 | |
197 | /* Frame transfer */ | |
198 | unsigned int samp_received; | |
199 | unsigned int samp_buffered; | |
200 | unsigned int trigger_offset; | |
201 | unsigned char *framebuf; | |
3b533202 BV |
202 | }; |
203 | ||
25a0f108 | 204 | SR_PRIV int dso_open(struct sr_dev_inst *sdi); |
3b533202 | 205 | SR_PRIV void dso_close(struct sr_dev_inst *sdi); |
c118080b BV |
206 | SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi); |
207 | SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi); | |
208 | SR_PRIV int dso_init(const struct sr_dev_inst *sdi); | |
209 | SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi, | |
e98b7f1b | 210 | uint8_t *capturestate, uint32_t *trigger_offset); |
c118080b | 211 | SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi); |
69e19dd7 | 212 | SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi, |
e98b7f1b | 213 | libusb_transfer_cb_fn cb); |
3b533202 BV |
214 | |
215 | #endif |