[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

#define FW_BUFSIZE (4 * 1024)

int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *filename)
{
	FILE *fw;
	struct stat st;
	struct sr_usb_dev_inst *usb;
	int chunksize, result, ret;
	unsigned char *buf;
	int sum, transferred;

	sr_dbg("Uploading FPGA firmware at %s.", filename);

	usb = sdi->conn;
	if (stat(filename, &st) < 0) {
		sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
		return SR_ERR;
	}

	/* Tell the device firmware is coming. */
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
			NULL, 0, 3000)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		return SR_ERR;
	}
	buf = g_malloc(FW_BUFSIZE);

	if ((fw = g_fopen(filename, "rb")) == NULL) {
		sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(10 * 1000);

	sum = 0;
	result = SR_OK;
	while (1) {
		if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, 1000)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	fclose(fw);
	g_free(buf);
	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	devc = sdi->priv;
	mode.flags = 0;
	mode.sample_delay_h = mode.sample_delay_l = 0;
	if (devc->sample_wide)
		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), 3000);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");
	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	WL32(&cfg.count_header, DS_CFG_COUNT);
	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			c, 3, 100);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	/*
	 * 15	1 = internal test mode
	 * 14	1 = external test mode
	 * 13	1 = loopback test mode
	 * 8-12	unused
	 * 7	1 = analog mode
	 * 6	1 = samplerate 400MHz
	 * 5	1 = samplerate 200MHz or analog mode
	 * 4	0 = logic, 1 = dso or analog
	 * 2-3	unused
	 * 1	0 = internal clock, 1 = external clock
	 * 0	1 = trigger enabled
	 */
	v16 = 0x0000;
	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
		v16 = 1 << 15;
	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
		v16 = 1 << 14;
	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
		v16 = 1 << 13;
	if (devc->dslogic_external_clock)
		v16 |= 1 << 2;
	WL16(&cfg.mode, v16);

	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len,
			&transferred, 100);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <sys/types.h>
	22	#include <sys/stat.h>
	23	#include <unistd.h>
	24	#include <errno.h>
	25	#include <math.h>
	26	#include <glib.h>
	27	#include <glib/gstdio.h>
	28	#include "protocol.h"
	29	#include "dslogic.h"
	30
1a46cc62 UH	31	#define FW_BUFSIZE (4 * 1024)
1a46cc62 UH	32
b9d53092 BV	33	int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
	34	const char *filename)
	35	{
	36	FILE *fw;
	37	struct stat st;
	38	struct sr_usb_dev_inst *usb;
	39	int chunksize, result, ret;
	40	unsigned char *buf;
	41	int sum, transferred;
	42
	43	sr_dbg("Uploading FPGA firmware at %s.", filename);
	44
	45	usb = sdi->conn;
	46	if (stat(filename, &st) < 0) {
	47	sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
	48	return SR_ERR;
	49	}
	50
	51	/* Tell the device firmware is coming. */
	52	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	53	LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
	54	NULL, 0, 3000)) < 0) {
	55	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
	56	return SR_ERR;
	57	}
	58	buf = g_malloc(FW_BUFSIZE);
	59
	60	if ((fw = g_fopen(filename, "rb")) == NULL) {
	61	sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
	62	return SR_ERR;
	63	}
	64
	65	/* Give the FX2 time to get ready for FPGA firmware upload. */
	66	g_usleep(10 * 1000);
	67
	68	sum = 0;
	69	result = SR_OK;
	70	while (1) {
	71	if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
	72	break;
	73
	74	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
	75	buf, chunksize, &transferred, 1000)) < 0) {
	76	sr_err("Unable to configure FPGA firmware: %s.",
	77	libusb_error_name(ret));
	78	result = SR_ERR;
	79	break;
	80	}
	81	sum += transferred;
	82	sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
	83
	84	if (transferred != chunksize) {
	85	sr_err("Short transfer while uploading FPGA firmware.");
	86	result = SR_ERR;
	87	break;
	88	}
	89	}
	90	fclose(fw);
	91	g_free(buf);
	92	if (result == SR_OK)
	93	sr_dbg("FPGA firmware upload done.");
	94
	95	return result;
	96	}
97
98	int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
99	{
100	struct dev_context *devc;
101	struct sr_usb_dev_inst *usb;
102	struct dslogic_mode mode;
103	int ret;
104
105	devc = sdi->priv;
106	mode.flags = 0;
107	mode.sample_delay_h = mode.sample_delay_l = 0;
108	if (devc->sample_wide)
109	mode.flags \|= DS_START_FLAGS_SAMPLE_WIDE;
110
111	usb = sdi->conn;
112	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
113	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
114	(unsigned char *)&mode, sizeof(mode), 3000);
115	if (ret < 0) {
116	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
117	return SR_ERR;
118	}
119
120	return SR_OK;
121	}
122
123	int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
124	{
125	struct sr_usb_dev_inst *usb;
126	struct dslogic_mode mode;
127	int ret;
128
129	mode.flags = DS_START_FLAGS_STOP;
130	mode.sample_delay_h = mode.sample_delay_l = 0;
131
132	usb = sdi->conn;
133	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
134	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
135	(unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
136	if (ret < 0) {
137	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
138	return SR_ERR;
139	}
140
141	return SR_OK;
142	}
143
144	int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
145	{
146	struct dev_context *devc;
147	struct sr_usb_dev_inst *usb;
148	uint8_t c[3];
149	struct dslogic_fpga_config cfg;
150	uint16_t v16;
151	uint32_t v32;
152	int transferred, len, ret;
153
154	sr_dbg("Configuring FPGA.");
155	usb = sdi->conn;
156	devc = sdi->priv;
157
158	WL32(&cfg.sync, DS_CFG_START);
159	WL16(&cfg.mode_header, DS_CFG_MODE);
160	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
161	WL32(&cfg.count_header, DS_CFG_COUNT);
162	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
163	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
164	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
165	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
166	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
167	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
168	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
169	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
170	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
171	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
172	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
173	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
174	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
175	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
176	WL32(&cfg.end_sync, DS_CFG_END);
177
178	/* Pass in the length of a fixed-size struct. Really. */
179	len = sizeof(struct dslogic_fpga_config) / 2;
180	c[0] = len & 0xff;
181	c[1] = (len >> 8) & 0xff;
182	c[2] = (len >> 16) & 0xff;
183
184	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
185	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
186	c, 3, 100);
187	if (ret < 0) {
188	sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
189	return SR_ERR;
190	}
191
192	/*
193	* 15 1 = internal test mode
194	* 14 1 = external test mode
195	* 13 1 = loopback test mode
196	* 8-12 unused
197	* 7 1 = analog mode
198	* 6 1 = samplerate 400MHz
199	* 5 1 = samplerate 200MHz or analog mode
200	* 4 0 = logic, 1 = dso or analog
201	* 2-3 unused
202	* 1 0 = internal clock, 1 = external clock
203	* 0 1 = trigger enabled
204	*/
205	v16 = 0x0000;
206	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
207	v16 = 1 << 15;
208	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
209	v16 = 1 << 14;
210	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
211	v16 = 1 << 13;
212	if (devc->dslogic_external_clock)
213	v16 \|= 1 << 2;
214	WL16(&cfg.mode, v16);
215
216	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
217	WL32(&cfg.divider, v32);
218	WL32(&cfg.count, devc->limit_samples);
219
220	len = sizeof(struct dslogic_fpga_config);
221	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
222	(unsigned char *)&cfg, len,
223	&transferred, 100);
224	if (ret < 0 \|\| transferred != len) {
225	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
226	return SR_ERR;
227	}
228
229	return SR_OK;
230	}