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b9d53092 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <sys/types.h> | |
22 | #include <sys/stat.h> | |
23 | #include <unistd.h> | |
24 | #include <errno.h> | |
25 | #include <math.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include "protocol.h" | |
29 | #include "dslogic.h" | |
30 | ||
1a46cc62 UH |
31 | #define FW_BUFSIZE (4 * 1024) |
32 | ||
4df5739a UH |
33 | #define FPGA_UPLOAD_DELAY (10 * 1000) |
34 | ||
35 | #define USB_TIMEOUT (3 * 1000) | |
36 | ||
b9d53092 BV |
37 | int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, |
38 | const char *filename) | |
39 | { | |
40 | FILE *fw; | |
6433156c | 41 | GStatBuf st; |
b9d53092 BV |
42 | struct sr_usb_dev_inst *usb; |
43 | int chunksize, result, ret; | |
44 | unsigned char *buf; | |
45 | int sum, transferred; | |
d93c1470 | 46 | uint8_t cmd[3]; |
b9d53092 BV |
47 | |
48 | sr_dbg("Uploading FPGA firmware at %s.", filename); | |
49 | ||
50 | usb = sdi->conn; | |
6433156c | 51 | if (g_stat(filename, &st) < 0) { |
7237e912 | 52 | sr_err("Unable to upload FPGA firmware: %s", g_strerror(errno)); |
b9d53092 BV |
53 | return SR_ERR; |
54 | } | |
55 | ||
56 | /* Tell the device firmware is coming. */ | |
d93c1470 | 57 | memset(cmd, 0, sizeof(cmd)); |
b9d53092 BV |
58 | if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | |
59 | LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000, | |
d93c1470 | 60 | (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) { |
b9d53092 BV |
61 | sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); |
62 | return SR_ERR; | |
63 | } | |
64 | buf = g_malloc(FW_BUFSIZE); | |
65 | ||
98fec29e | 66 | if (!(fw = g_fopen(filename, "rb"))) { |
7237e912 | 67 | sr_err("Unable to open %s for reading: %s.", filename, g_strerror(errno)); |
b9d53092 BV |
68 | return SR_ERR; |
69 | } | |
70 | ||
71 | /* Give the FX2 time to get ready for FPGA firmware upload. */ | |
4df5739a | 72 | g_usleep(FPGA_UPLOAD_DELAY); |
b9d53092 BV |
73 | |
74 | sum = 0; | |
75 | result = SR_OK; | |
76 | while (1) { | |
77 | if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0) | |
78 | break; | |
79 | ||
80 | if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 81 | buf, chunksize, &transferred, USB_TIMEOUT)) < 0) { |
b9d53092 BV |
82 | sr_err("Unable to configure FPGA firmware: %s.", |
83 | libusb_error_name(ret)); | |
84 | result = SR_ERR; | |
85 | break; | |
86 | } | |
87 | sum += transferred; | |
6433156c DE |
88 | sr_spew("Uploaded %d/%" PRIu64 " bytes.", |
89 | sum, (uint64_t)st.st_size); | |
b9d53092 BV |
90 | |
91 | if (transferred != chunksize) { | |
92 | sr_err("Short transfer while uploading FPGA firmware."); | |
93 | result = SR_ERR; | |
94 | break; | |
95 | } | |
96 | } | |
97 | fclose(fw); | |
98 | g_free(buf); | |
99 | if (result == SR_OK) | |
100 | sr_dbg("FPGA firmware upload done."); | |
101 | ||
102 | return result; | |
103 | } | |
104 | ||
105 | int dslogic_start_acquisition(const struct sr_dev_inst *sdi) | |
106 | { | |
107 | struct dev_context *devc; | |
108 | struct sr_usb_dev_inst *usb; | |
109 | struct dslogic_mode mode; | |
110 | int ret; | |
111 | ||
112 | devc = sdi->priv; | |
113 | mode.flags = 0; | |
114 | mode.sample_delay_h = mode.sample_delay_l = 0; | |
115 | if (devc->sample_wide) | |
116 | mode.flags |= DS_START_FLAGS_SAMPLE_WIDE; | |
117 | ||
118 | usb = sdi->conn; | |
119 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
120 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 121 | (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT); |
b9d53092 BV |
122 | if (ret < 0) { |
123 | sr_err("Failed to send start command: %s.", libusb_error_name(ret)); | |
124 | return SR_ERR; | |
125 | } | |
126 | ||
127 | return SR_OK; | |
128 | } | |
129 | ||
130 | int dslogic_stop_acquisition(const struct sr_dev_inst *sdi) | |
131 | { | |
132 | struct sr_usb_dev_inst *usb; | |
133 | struct dslogic_mode mode; | |
134 | int ret; | |
135 | ||
136 | mode.flags = DS_START_FLAGS_STOP; | |
137 | mode.sample_delay_h = mode.sample_delay_l = 0; | |
138 | ||
139 | usb = sdi->conn; | |
140 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
141 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 142 | (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT); |
b9d53092 BV |
143 | if (ret < 0) { |
144 | sr_err("Failed to send stop command: %s.", libusb_error_name(ret)); | |
145 | return SR_ERR; | |
146 | } | |
147 | ||
148 | return SR_OK; | |
149 | } | |
150 | ||
151 | int dslogic_fpga_configure(const struct sr_dev_inst *sdi) | |
152 | { | |
153 | struct dev_context *devc; | |
154 | struct sr_usb_dev_inst *usb; | |
155 | uint8_t c[3]; | |
156 | struct dslogic_fpga_config cfg; | |
157 | uint16_t v16; | |
158 | uint32_t v32; | |
159 | int transferred, len, ret; | |
160 | ||
161 | sr_dbg("Configuring FPGA."); | |
162 | usb = sdi->conn; | |
163 | devc = sdi->priv; | |
164 | ||
165 | WL32(&cfg.sync, DS_CFG_START); | |
166 | WL16(&cfg.mode_header, DS_CFG_MODE); | |
167 | WL32(&cfg.divider_header, DS_CFG_DIVIDER); | |
168 | WL32(&cfg.count_header, DS_CFG_COUNT); | |
169 | WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS); | |
170 | WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); | |
171 | WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP); | |
172 | WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA); | |
173 | WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0); | |
174 | WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1); | |
175 | WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0); | |
176 | WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1); | |
177 | WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0); | |
178 | WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1); | |
179 | WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0); | |
180 | WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1); | |
181 | WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0); | |
182 | WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1); | |
183 | WL32(&cfg.end_sync, DS_CFG_END); | |
184 | ||
185 | /* Pass in the length of a fixed-size struct. Really. */ | |
186 | len = sizeof(struct dslogic_fpga_config) / 2; | |
187 | c[0] = len & 0xff; | |
188 | c[1] = (len >> 8) & 0xff; | |
189 | c[2] = (len >> 16) & 0xff; | |
190 | ||
191 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
192 | LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, | |
4df5739a | 193 | c, 3, USB_TIMEOUT); |
b9d53092 BV |
194 | if (ret < 0) { |
195 | sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret)); | |
196 | return SR_ERR; | |
197 | } | |
198 | ||
199 | /* | |
200 | * 15 1 = internal test mode | |
201 | * 14 1 = external test mode | |
202 | * 13 1 = loopback test mode | |
203 | * 8-12 unused | |
204 | * 7 1 = analog mode | |
205 | * 6 1 = samplerate 400MHz | |
206 | * 5 1 = samplerate 200MHz or analog mode | |
207 | * 4 0 = logic, 1 = dso or analog | |
208 | * 2-3 unused | |
209 | * 1 0 = internal clock, 1 = external clock | |
210 | * 0 1 = trigger enabled | |
211 | */ | |
212 | v16 = 0x0000; | |
213 | if (devc->dslogic_mode == DS_OP_INTERNAL_TEST) | |
214 | v16 = 1 << 15; | |
215 | else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST) | |
216 | v16 = 1 << 14; | |
217 | else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST) | |
218 | v16 = 1 << 13; | |
219 | if (devc->dslogic_external_clock) | |
220 | v16 |= 1 << 2; | |
221 | WL16(&cfg.mode, v16); | |
222 | ||
223 | v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate); | |
224 | WL32(&cfg.divider, v32); | |
225 | WL32(&cfg.count, devc->limit_samples); | |
226 | ||
227 | len = sizeof(struct dslogic_fpga_config); | |
228 | ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 229 | (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT); |
b9d53092 BV |
230 | if (ret < 0 || transferred != len) { |
231 | sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret)); | |
232 | return SR_ERR; | |
233 | } | |
234 | ||
235 | return SR_OK; | |
236 | } |