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Commit | Line | Data |
---|---|---|
281603c3 OR |
1 | ------------------------------------------------------------------------------- |
2 | SPI / SSI32 | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a set of SPI captures for the SSI32 protocol. | |
6 | ||
7 | ||
8 | Logic analyzer | |
9 | -------------- | |
10 | ||
11 | The logic analyzer used was a DP Open Bench Logic Sniffer (with different | |
12 | sample rate configurations). | |
13 | ||
14 | ||
15 | Probing | |
16 | ------- | |
17 | ||
18 | The sigrok command line used was: | |
19 | ||
20 | sigrok-cli --driver=ols:conn=/dev/ttyACM0 --config samplerate=<srate> \ | |
21 | --time=100 -t 3=0 -C 0-4 -o <file> | |
22 | ||
23 | ||
24 | ssi32_bananapi_loop_test.sr, samplerate 5m | |
25 | ------------------------------------------ | |
26 | ||
27 | Created on Banana Pi with SPI clock = 1MHz. MISO connected in a loop to itself. | |
28 | ||
29 | Pins: | |
30 | ||
31 | Banana Pi LA LOOP | |
32 | ---------------------------------- | |
33 | (CON3) SPI-CLK ---> CLK ---~ (NC) | |
34 | (CON3) SPI-MISO <-- MISO <--- | |
35 | (CON3) SPI-MOSI --> MOSI -->^ | |
36 | (CON3) IO-4 <--- FC# <--- | |
37 | (CON3) SPI-CE0 ---> CS# -->^ | |
38 | ||
39 | ||
40 | ssi32_watchdog.sr, samplerate 10m | |
41 | --------------------------------- | |
42 | ||
43 | Created on Banana Pi attached to STM32F3 Discovery. SPI clock = 5MHz. | |
44 | STM32F3 was running ssi32_slave example with soft watchdog on LUN=9. | |
45 | ||
46 | Pins: | |
47 | ||
48 | Banana Pi LA STM32F3 Discovery | |
49 | ------------------------------------------------ | |
50 | (CON3) SPI-CLK ---> CLK ---> (P2) PC10 | |
51 | (CON3) SPI-MISO <-- MISO <--- (P2) PC11 | |
52 | (CON3) SPI-MOSI --> MOSI ---> (P2) PC12 | |
53 | (CON3) SPI-CE0 ---> CS# ---> (P3) PD12 | |
54 | (CON3) IO-4 <--- FC# <--- (P2) PB4 | |
55 |