projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 44fbf096 UH |
1 | ------------------------------------------------------------------------------- |
| 2 | Atmel ATtiny13 I²C | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a set of example captures of the I²C traffic to/from the Atmel | |
| 6 | ATtiny13 chip and the Cypress FX2 in the Braintechnology USB-LPS device. | |
| 7 | ||
| 8 | Details: | |
| 9 | http://www.atmel.com/images/doc2535.pdf | |
| 10 | http://www.braintechnology.de/braintechnology/usb_lps.html | |
| 11 | ||
| 12 | ||
| 13 | Logic analyzer setup | |
| 14 | -------------------- | |
| 15 | ||
| 16 | The logic analyzer used was a CWAV USBee SX (at 12MHz): | |
| 17 | ||
| 18 | Probe ATtiny13 pin | |
| 19 | ------------------------ | |
| 20 | 0 (black) PB0 | |
| 21 | 1 (brown) PB1/SDA | |
| 22 | 2 (red) PB2/SCL | |
| 23 | 3 (orange) PB3 | |
| 24 | 4 (yellow) PB4 | |
| 25 | 5 (green) PB5 | |
| 26 | ||
| 27 | ||
| 28 | Data | |
| 29 | ---- | |
| 30 | ||
| 31 | The data contains the power-up sequence when the USB cable is attached. | |
| 32 |