[libsigrok.git] / hardware / zeroplus-logic-cube / analyzer.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *  THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <assert.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"
#include "analyzer.h"
#include "gl_usb.h"
#include "protocol.h"

enum {
	HARD_DATA_CHECK_SUM		= 0x00,
	PASS_WORD,

	DEV_ID0				= 0x10,
	DEV_ID1,

	START_STATUS			= 0x20,
	DEV_STATUS			= 0x21,
	FREQUENCY_REG0			= 0x30,
	FREQUENCY_REG1,
	FREQUENCY_REG2,
	FREQUENCY_REG3,
	FREQUENCY_REG4,
	MEMORY_LENGTH,
	CLOCK_SOURCE,

	TRIGGER_STATUS0			= 0x40,
	TRIGGER_STATUS1,
	TRIGGER_STATUS2,
	TRIGGER_STATUS3,
	TRIGGER_STATUS4,
	TRIGGER_STATUS5,
	TRIGGER_STATUS6,
	TRIGGER_STATUS7,
	TRIGGER_STATUS8,

	TRIGGER_COUNT0			= 0x50,
	TRIGGER_COUNT1,

	TRIGGER_LEVEL0			= 0x55,
	TRIGGER_LEVEL1,
	TRIGGER_LEVEL2,
	TRIGGER_LEVEL3,

	RAMSIZE_TRIGGERBAR_ADDRESS0	= 0x60,
	RAMSIZE_TRIGGERBAR_ADDRESS1,
	RAMSIZE_TRIGGERBAR_ADDRESS2,
	TRIGGERBAR_ADDRESS0,
	TRIGGERBAR_ADDRESS1,
	TRIGGERBAR_ADDRESS2,
	DONT_CARE_TRIGGERBAR,

	FILTER_ENABLE			= 0x70,
	FILTER_STATUS,

	ENABLE_DELAY_TIME0		= 0x7a,
	ENABLE_DELAY_TIME1,

	ENABLE_INSERT_DATA0		= 0x80,
	ENABLE_INSERT_DATA1,
	ENABLE_INSERT_DATA2,
	ENABLE_INSERT_DATA3,
	COMPRESSION_TYPE0,
	COMPRESSION_TYPE1,

	TRIGGER_ADDRESS0		= 0x90,
	TRIGGER_ADDRESS1,
	TRIGGER_ADDRESS2,

	NOW_ADDRESS0			= 0x96,
	NOW_ADDRESS1,
	NOW_ADDRESS2,

	STOP_ADDRESS0			= 0x9b,
	STOP_ADDRESS1,
	STOP_ADDRESS2,

	READ_RAM_STATUS			= 0xa0,
};

static int g_trigger_status[9] = { 0 };
static int g_trigger_count = 1;
static int g_filter_status[8] = { 0 };
static int g_filter_enable = 0;

static int g_freq_value = 1;
static int g_freq_scale = FREQ_SCALE_MHZ;
static int g_memory_size = MEMORY_SIZE_8K;
static int g_ramsize_triggerbar_addr = 2 * 1024;
static int g_triggerbar_addr = 0;
static int g_compression = COMPRESSION_NONE;

/* Maybe unk specifies an "endpoint" or "register" of sorts. */
static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
				 unsigned char flags)
{
	assert(unk <= 3);
	return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
}

#if 0
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	int reg0 = 0, divisor = 0, reg2 = 0;

	switch (scale) {
	case FREQ_SCALE_MHZ: /* MHz */
		if (freq >= 100 && freq <= 200) {
			reg0 = freq * 0.1;
			divisor = 1;
			reg2 = 0;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.2;
			divisor = 2;
			reg2 = 0;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 1;
				break;
			} else {
				reg0 = freq * 0.5;
				divisor = 5;
				reg2 = 1;
				break;
			}
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 2;
			break;
		}
		if (freq == 1) {
			divisor = 5;
			reg2 = 16;
			reg0 = 5;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_HZ: /* Hz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 10;
			reg2 = 64;
			break;
		}
		if (freq >= 300 && freq < 500) {
			reg0 = freq * 0.005 * 8;
			divisor = 5;
			reg2 = 67;
			break;
		}
		if (freq >= 100 && freq < 300) {
			reg0 = freq * 0.005 * 16;
			divisor = 5;
			reg2 = 68;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_KHZ: /* kHz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 5;
			reg2 = 17;
			break;
		}
		if (freq >= 100 && freq < 500) {
			reg0 = freq * 0.05;
			divisor = 5;
			reg2 = 32;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.1;
			divisor = 5;
			reg2 = 33;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 49;
				break;
			}
			reg0 = freq * 0.5;
			divisor = 5;
			reg2 = 48;
			break;
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 50;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	default:
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	}

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, divisor, reg0, 0x02, reg2);

	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
		return -1; /* Divisor maybe? */

	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
		return -1; /* 10 / 0.2 */

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1; /* Always 2 */

	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
		return -1;

	return 0;
}
#endif

/*
 * It seems that ...
 *	FREQUENCT_REG0 - division factor (?)
 *	FREQUENCT_REG1 - multiplication factor (?)
 *	FREQUENCT_REG4 - clock selection (?)
 *
 *	clock selection
 *	0  10MHz  16   1MHz  32 100kHz  48  10kHz  64   1kHz
 *	1   5MHz  17 500kHz  33  50kHz  49   5kHz  65  500Hz
 *	2 2.5MHz   .          .         50 2.5kHz  66  250Hz
 *	.          .          .          .         67  125Hz
 *	.          .          .          .         68 62.5Hz
 */
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	struct freq_factor {
		int freq;
		int scale;
		int sel;
		int div;
		int mul;
	};

	static const struct freq_factor f[] = {
		{ 200, FREQ_SCALE_MHZ,  0,  1, 20 },
		{ 150, FREQ_SCALE_MHZ,  0,  1, 15 },
		{ 100, FREQ_SCALE_MHZ,  0,  1, 10 },
		{  80, FREQ_SCALE_MHZ,  0,  2, 16 },
		{  50, FREQ_SCALE_MHZ,  0,  2, 10 },
		{  25, FREQ_SCALE_MHZ,  1,  5, 25 },
		{  10, FREQ_SCALE_MHZ,  1,  5, 10 },
		{   1, FREQ_SCALE_MHZ, 16,  5,  5 },
		{ 800, FREQ_SCALE_KHZ, 17,  5,  8 },
		{ 400, FREQ_SCALE_KHZ, 32,  5, 20 },
		{ 200, FREQ_SCALE_KHZ, 32,  5, 10 },
		{ 100, FREQ_SCALE_KHZ, 32,  5,  5 },
		{  50, FREQ_SCALE_KHZ, 33,  5,  5 },
		{  25, FREQ_SCALE_KHZ, 49,  5, 25 },
		{   5, FREQ_SCALE_KHZ, 50,  5, 10 },
		{   1, FREQ_SCALE_KHZ, 64,  5,  5 },
		{ 500, FREQ_SCALE_HZ,  64, 10,  5 },
		{ 100, FREQ_SCALE_HZ,  68,  5,  8 },
		{   0, 0,              0,   0,  0 }
	};

	int i;

	for (i = 0; f[i].freq; i++) {
		if (scale == f[i].scale && freq == f[i].freq)
			break;
	}
	if (!f[i].freq)
		return -1;

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);

	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
		return -1;

	return 0;
}

static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
						   unsigned int address)
{
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
					      unsigned int address)
{
	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_compression(libusb_device_handle *devh,
				       unsigned int type)
{
	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
}

static void __analyzer_set_trigger_count(libusb_device_handle *devh,
					 unsigned int count)
{
	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
}

static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
{
	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
}

static void analyzer_set_filter(libusb_device_handle *devh)
{
	int i;
	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	for (i = 0; i < 8; i++)
		gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
}

SR_PRIV void analyzer_reset(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);	// reset device
	analyzer_write_status(devh, 3, STATUS_FLAG_RESET);	// reset device
}

SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
{
	int status;

	while (1) {
		status = gl_reg_read(devh, DEV_STATUS);
		if ((status & set) && ((status & unset) == 0))
			return;
	}
}

SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
{
	int i;

	analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);

	for (i = 0; i < 8; i++)
		(void)gl_reg_read(devh, READ_RAM_STATUS);
}

SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
		       unsigned int size)
{
	return gl_read_bulk(devh, buffer, size);
}

SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
}

SR_PRIV void analyzer_configure(libusb_device_handle *devh)
{
	int i;

	/* Write_Start_Status */
	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* Start_Config_Outside_Device ? */
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* SetData_To_Frequence_Reg */
	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);

	/* SetMemory_Length */
	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);

	/* Sele_Inside_Outside_Clock */
	gl_reg_write(devh, CLOCK_SOURCE, 0x03);

	/* Set_Trigger_Status */
	for (i = 0; i < 9; i++)
		gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);

	__analyzer_set_trigger_count(devh, g_trigger_count);

	/* Set_Trigger_Level */
	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);

	/* Size of actual memory >> 2 */
	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);

	/* Set_Dont_Care_TriggerBar */
	if (g_triggerbar_addr)
		gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x00);
	else
		gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);

	/* Enable_Status */
	analyzer_set_filter(devh);

	/* Set_Enable_Delay_Time */
	gl_reg_write(devh, 0x7a, 0x00);
	gl_reg_write(devh, 0x7b, 0x00);
	analyzer_write_enable_insert_data(devh);
	__analyzer_set_compression(devh, g_compression);
}

SR_PRIV void analyzer_add_trigger(int channel, int type)
{
	switch (type) {
	case TRIGGER_HIGH:
		g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
		break;
	case TRIGGER_LOW:
		g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
		break;
#if 0
	case TRIGGER_POSEDGE:
		g_trigger_status[8] = 0x40 | channel;
		break;
	case TRIGGER_NEGEDGE:
		g_trigger_status[8] = 0x80 | channel;
		break;
	case TRIGGER_ANYEDGE:
		g_trigger_status[8] = 0xc0 | channel;
		break;
#endif
	default:
		break;
	}
}

SR_PRIV void analyzer_add_filter(int channel, int type)
{
	int i;

	if (type != FILTER_HIGH && type != FILTER_LOW)
		return;
	if ((channel & 0xf) >= 8)
		return;

	if (channel & CHANNEL_A)
		i = 0;
	else if (channel & CHANNEL_B)
		i = 2;
	else if (channel & CHANNEL_C)
		i = 4;
	else if (channel & CHANNEL_D)
		i = 6;
	else
		return;

	if ((channel & 0xf) >= 4) {
		i++;
		channel -= 4;
	}

	g_filter_status[i] |=
	    1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));

	g_filter_enable = 1;
}

SR_PRIV void analyzer_set_trigger_count(int count)
{
	g_trigger_count = count;
}

SR_PRIV void analyzer_set_freq(int freq, int scale)
{
	g_freq_value = freq;
	g_freq_scale = scale;
}

SR_PRIV void analyzer_set_memory_size(unsigned int size)
{
	g_memory_size = size;
}

SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
{
	g_ramsize_triggerbar_addr = address;
}

SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
{
	g_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_STATUS);
}

SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
}

SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
			STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
			NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
		TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
}

SR_PRIV void analyzer_set_compression(unsigned int type)
{
	g_compression = type;
}

SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
}

SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
}

SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
				void *output, unsigned int output_len)
{
	unsigned char *in = input;
	unsigned char *out = output;
	unsigned int A, B, C, count;
	unsigned int written = 0;

	while (input_len > 0) {
		A = *in++;
		B = *in++;
		C = *in++;
		count = (*in++) + 1;

		if (count > output_len)
			count = output_len;
		output_len -= count;
		written += count;

		while (count--) {
			*out++ = A;
			*out++ = B;
			*out++ = C;
			*out++ = 0; /* Channel D */
		}

		input_len -= 4;
		if (output_len == 0)
			break;
	}

	return written;
}
Commit	Line	Data
a1bb33af	1	/*
fed16f06 UH	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
	5	* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or
	9	* without modification, are permitted provided that the following
	10	* conditions are met:
	11	*
	12	* * Redistributions of source code must retain the above copyright notice,
	13	* this list of conditions and the following disclaimer.
	14	*
	15	* * Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	29	* THE POSSIBILITY OF SUCH DAMAGE.
	30	*/
a1bb33af	31
fed16f06	32	#include <assert.h>
6d116114 UH	33	#include "libsigrok.h"
6d116114 UH	34	#include "libsigrok-internal.h"
a1bb33af UH	35	#include "analyzer.h"
a1bb33af UH	36	#include "gl_usb.h"
6d116114	37	#include "protocol.h"
a1bb33af UH	38
a1bb33af UH	39	enum {
fed16f06	40	HARD_DATA_CHECK_SUM = 0x00,
a1bb33af UH	41	PASS_WORD,
a1bb33af UH	42
bb7ef793 UH	43	DEV_ID0 = 0x10,
bb7ef793 UH	44	DEV_ID1,
a1bb33af	45
fed16f06	46	START_STATUS = 0x20,
bb7ef793	47	DEV_STATUS = 0x21,
fed16f06	48	FREQUENCY_REG0 = 0x30,
a1bb33af UH	49	FREQUENCY_REG1,
	50	FREQUENCY_REG2,
	51	FREQUENCY_REG3,
	52	FREQUENCY_REG4,
	53	MEMORY_LENGTH,
	54	CLOCK_SOURCE,
	55
fed16f06	56	TRIGGER_STATUS0 = 0x40,
a1bb33af UH	57	TRIGGER_STATUS1,
	58	TRIGGER_STATUS2,
	59	TRIGGER_STATUS3,
	60	TRIGGER_STATUS4,
	61	TRIGGER_STATUS5,
	62	TRIGGER_STATUS6,
	63	TRIGGER_STATUS7,
	64	TRIGGER_STATUS8,
	65
fed16f06	66	TRIGGER_COUNT0 = 0x50,
a1bb33af UH	67	TRIGGER_COUNT1,
a1bb33af UH	68
fed16f06	69	TRIGGER_LEVEL0 = 0x55,
a1bb33af UH	70	TRIGGER_LEVEL1,
	71	TRIGGER_LEVEL2,
	72	TRIGGER_LEVEL3,
	73
	74	RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
	75	RAMSIZE_TRIGGERBAR_ADDRESS1,
	76	RAMSIZE_TRIGGERBAR_ADDRESS2,
	77	TRIGGERBAR_ADDRESS0,
	78	TRIGGERBAR_ADDRESS1,
	79	TRIGGERBAR_ADDRESS2,
	80	DONT_CARE_TRIGGERBAR,
	81
	82	FILTER_ENABLE = 0x70,
	83	FILTER_STATUS,
	84
fed16f06	85	ENABLE_DELAY_TIME0 = 0x7a,
a1bb33af UH	86	ENABLE_DELAY_TIME1,
a1bb33af UH	87
fed16f06	88	ENABLE_INSERT_DATA0 = 0x80,
a1bb33af UH	89	ENABLE_INSERT_DATA1,
	90	ENABLE_INSERT_DATA2,
	91	ENABLE_INSERT_DATA3,
	92	COMPRESSION_TYPE0,
	93	COMPRESSION_TYPE1,
	94
fed16f06	95	TRIGGER_ADDRESS0 = 0x90,
a1bb33af UH	96	TRIGGER_ADDRESS1,
	97	TRIGGER_ADDRESS2,
	98
fed16f06	99	NOW_ADDRESS0 = 0x96,
a1bb33af UH	100	NOW_ADDRESS1,
	101	NOW_ADDRESS2,
	102
fed16f06	103	STOP_ADDRESS0 = 0x9b,
a1bb33af UH	104	STOP_ADDRESS1,
	105	STOP_ADDRESS2,
	106
fed16f06	107	READ_RAM_STATUS = 0xa0,
a1bb33af UH	108	};
a1bb33af UH	109
fed16f06	110	static int g_trigger_status[9] = { 0 };
a1bb33af	111	static int g_trigger_count = 1;
fed16f06	112	static int g_filter_status[8] = { 0 };
a1bb33af UH	113	static int g_filter_enable = 0;
a1bb33af UH	114
0ab0cb94	115	static int g_freq_value = 1;
a1bb33af	116	static int g_freq_scale = FREQ_SCALE_MHZ;
0ab0cb94 TY	117	static int g_memory_size = MEMORY_SIZE_8K;
	118	static int g_ramsize_triggerbar_addr = 2 * 1024;
	119	static int g_triggerbar_addr = 0;
a1bb33af UH	120	static int g_compression = COMPRESSION_NONE;
a1bb33af UH	121
fed16f06 UH	122	/* Maybe unk specifies an "endpoint" or "register" of sorts. */
	123	static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
	124	unsigned char flags)
a1bb33af UH	125	{
	126	assert(unk <= 3);
	127	return gl_reg_write(devh, START_STATUS, unk << 6 \| flags);
	128	}
	129
0ab0cb94	130	#if 0
a1bb33af UH	131	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
a1bb33af UH	132	{
fed16f06 UH	133	int reg0 = 0, divisor = 0, reg2 = 0;
fed16f06 UH	134
a1bb33af	135	switch (scale) {
fed16f06 UH	136	case FREQ_SCALE_MHZ: /* MHz */
	137	if (freq >= 100 && freq <= 200) {
	138	reg0 = freq * 0.1;
	139	divisor = 1;
	140	reg2 = 0;
	141	break;
	142	}
	143	if (freq >= 50 && freq < 100) {
	144	reg0 = freq * 0.2;
	145	divisor = 2;
	146	reg2 = 0;
	147	break;
	148	}
	149	if (freq >= 10 && freq < 50) {
	150	if (freq == 25) {
	151	reg0 = 25;
a1bb33af	152	divisor = 5;
fed16f06	153	reg2 = 1;
a1bb33af	154	break;
fed16f06 UH	155	} else {
fed16f06 UH	156	reg0 = freq * 0.5;
a1bb33af	157	divisor = 5;
fed16f06	158	reg2 = 1;
a1bb33af UH	159	break;
a1bb33af UH	160	}
fed16f06 UH	161	}
fed16f06 UH	162	if (freq >= 2 && freq < 10) {
a1bb33af	163	divisor = 5;
fed16f06 UH	164	reg0 = freq * 2;
fed16f06 UH	165	reg2 = 2;
a1bb33af	166	break;
fed16f06 UH	167	}
fed16f06 UH	168	if (freq == 1) {
a1bb33af	169	divisor = 5;
fed16f06	170	reg2 = 16;
a1bb33af	171	reg0 = 5;
fed16f06 UH	172	break;
	173	}
	174	divisor = 5;
	175	reg0 = 5;
	176	reg2 = 64;
	177	break;
	178	case FREQ_SCALE_HZ: /* Hz */
	179	if (freq >= 500 && freq < 1000) {
	180	reg0 = freq * 0.01;
	181	divisor = 10;
a1bb33af UH	182	reg2 = 64;
a1bb33af UH	183	break;
fed16f06 UH	184	}
	185	if (freq >= 300 && freq < 500) {
	186	reg0 = freq * 0.005 * 8;
	187	divisor = 5;
	188	reg2 = 67;
	189	break;
	190	}
	191	if (freq >= 100 && freq < 300) {
	192	reg0 = freq * 0.005 * 16;
	193	divisor = 5;
	194	reg2 = 68;
	195	break;
	196	}
	197	divisor = 5;
	198	reg0 = 5;
	199	reg2 = 64;
	200	break;
38ba2522	201	case FREQ_SCALE_KHZ: /* kHz */
fed16f06 UH	202	if (freq >= 500 && freq < 1000) {
	203	reg0 = freq * 0.01;
	204	divisor = 5;
	205	reg2 = 17;
	206	break;
	207	}
	208	if (freq >= 100 && freq < 500) {
	209	reg0 = freq * 0.05;
	210	divisor = 5;
	211	reg2 = 32;
	212	break;
	213	}
	214	if (freq >= 50 && freq < 100) {
	215	reg0 = freq * 0.1;
	216	divisor = 5;
	217	reg2 = 33;
	218	break;
	219	}
	220	if (freq >= 10 && freq < 50) {
	221	if (freq == 25) {
	222	reg0 = 25;
a1bb33af	223	divisor = 5;
fed16f06	224	reg2 = 49;
a1bb33af UH	225	break;
a1bb33af UH	226	}
fed16f06	227	reg0 = freq * 0.5;
a1bb33af	228	divisor = 5;
fed16f06	229	reg2 = 48;
a1bb33af	230	break;
fed16f06 UH	231	}
fed16f06 UH	232	if (freq >= 2 && freq < 10) {
a1bb33af	233	divisor = 5;
fed16f06 UH	234	reg0 = freq * 2;
fed16f06 UH	235	reg2 = 50;
a1bb33af	236	break;
fed16f06 UH	237	}
	238	divisor = 5;
	239	reg0 = 5;
	240	reg2 = 64;
	241	break;
	242	default:
	243	divisor = 5;
	244	reg0 = 5;
	245	reg2 = 64;
	246	break;
a1bb33af	247	}
c13536fa	248
6d116114	249	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
c13536fa UH	250	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	251	freq, scale, divisor, reg0, 0x02, reg2);
	252
a1bb33af	253	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
fed16f06	254	return -1; /* Divisor maybe? */
a1bb33af UH	255
a1bb33af UH	256	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
fed16f06	257	return -1; /* 10 / 0.2 */
a1bb33af UH	258
a1bb33af UH	259	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
fed16f06	260	return -1; /* Always 2 */
a1bb33af UH	261
	262	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
	263	return -1;
	264
	265	return 0;
	266	}
0ab0cb94 TY	267	#endif
	268
	269	/*
	270	* It seems that ...
	271	* FREQUENCT_REG0 - division factor (?)
	272	* FREQUENCT_REG1 - multiplication factor (?)
	273	* FREQUENCT_REG4 - clock selection (?)
	274	*
	275	* clock selection
	276	* 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
	277	* 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
	278	* 2 2.5MHz . . 50 2.5kHz 66 250Hz
	279	* . . . . 67 125Hz
	280	* . . . . 68 62.5Hz
	281	*/
	282	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
	283	{
	284	struct freq_factor {
	285	int freq;
	286	int scale;
	287	int sel;
	288	int div;
	289	int mul;
	290	};
	291
	292	static const struct freq_factor f[] = {
	293	{ 200, FREQ_SCALE_MHZ, 0, 1, 20 },
	294	{ 150, FREQ_SCALE_MHZ, 0, 1, 15 },
	295	{ 100, FREQ_SCALE_MHZ, 0, 1, 10 },
	296	{ 80, FREQ_SCALE_MHZ, 0, 2, 16 },
	297	{ 50, FREQ_SCALE_MHZ, 0, 2, 10 },
	298	{ 25, FREQ_SCALE_MHZ, 1, 5, 25 },
	299	{ 10, FREQ_SCALE_MHZ, 1, 5, 10 },
	300	{ 1, FREQ_SCALE_MHZ, 16, 5, 5 },
	301	{ 800, FREQ_SCALE_KHZ, 17, 5, 8 },
	302	{ 400, FREQ_SCALE_KHZ, 32, 5, 20 },
	303	{ 200, FREQ_SCALE_KHZ, 32, 5, 10 },
	304	{ 100, FREQ_SCALE_KHZ, 32, 5, 5 },
	305	{ 50, FREQ_SCALE_KHZ, 33, 5, 5 },
	306	{ 25, FREQ_SCALE_KHZ, 49, 5, 25 },
	307	{ 5, FREQ_SCALE_KHZ, 50, 5, 10 },
	308	{ 1, FREQ_SCALE_KHZ, 64, 5, 5 },
	309	{ 500, FREQ_SCALE_HZ, 64, 10, 5 },
	310	{ 100, FREQ_SCALE_HZ, 68, 5, 8 },
	311	{ 0, 0, 0, 0, 0 }
	312	};
	313
	314	int i;
	315
	316	for (i = 0; f[i].freq; i++) {
	317	if (scale == f[i].scale && freq == f[i].freq)
	318	break;
	319	}
	320	if (!f[i].freq)
	321	return -1;
	322
6d116114	323	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
0ab0cb94 TY	324	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	325	freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
	326
	327	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
	328	return -1;
	329
	330	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
	331	return -1;
	332
	333	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
	334	return -1;
	335
	336	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
	337	return -1;
	338
	339	return 0;
	340	}
a1bb33af	341
fed16f06 UH	342	static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
fed16f06 UH	343	unsigned int address)
a1bb33af	344	{
fed16f06 UH	345	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	346	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	347	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	348	}
	349
fed16f06 UH	350	static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
fed16f06 UH	351	unsigned int address)
a1bb33af	352	{
fed16f06 UH	353	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	354	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	355	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	356	}
	357
fed16f06 UH	358	static void __analyzer_set_compression(libusb_device_handle *devh,
fed16f06 UH	359	unsigned int type)
a1bb33af UH	360	{
	361	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	362	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
	363	}
	364
fed16f06 UH	365	static void __analyzer_set_trigger_count(libusb_device_handle *devh,
fed16f06 UH	366	unsigned int count)
a1bb33af UH	367	{
	368	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	369	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
	370	}
	371
	372	static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
	373	{
	374	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	375	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	376	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	377	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
	378	}
	379
	380	static void analyzer_set_filter(libusb_device_handle *devh)
	381	{
	382	int i;
	383	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	384	for (i = 0; i < 8; i++)
	385	gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
	386	}
	387
ca070ed9	388	SR_PRIV void analyzer_reset(libusb_device_handle *devh)
a1bb33af	389	{
fed16f06 UH	390	analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
fed16f06 UH	391	analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
a1bb33af UH	392	}
a1bb33af UH	393
ca070ed9	394	SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
a1bb33af UH	395	{
	396	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	397	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	398	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	399	}
	400
ca070ed9	401	SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
a1bb33af UH	402	{
a1bb33af UH	403	int status;
6d116114	404
fed16f06	405	while (1) {
bb7ef793	406	status = gl_reg_read(devh, DEV_STATUS);
a1bb33af UH	407	if ((status & set) && ((status & unset) == 0))
	408	return;
	409	}
	410	}
	411
ca070ed9	412	SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
a1bb33af UH	413	{
	414	int i;
	415
	416	analyzer_write_status(devh, 3, STATUS_FLAG_20 \| STATUS_FLAG_READ);
	417
	418	for (i = 0; i < 8; i++)
	419	(void)gl_reg_read(devh, READ_RAM_STATUS);
	420	}
	421
ca070ed9	422	SR_PRIV int analyzer_read_data(libusb_device_handle devh, void buffer,
fed16f06	423	unsigned int size)
a1bb33af UH	424	{
	425	return gl_read_bulk(devh, buffer, size);
	426	}
	427
ca070ed9	428	SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
a1bb33af UH	429	{
	430	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	431	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
	432	}
	433
ca070ed9	434	SR_PRIV void analyzer_start(libusb_device_handle *devh)
a1bb33af UH	435	{
	436	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	437	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	438	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	439	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
	440	}
	441
ca070ed9	442	SR_PRIV void analyzer_configure(libusb_device_handle *devh)
a1bb33af	443	{
fed16f06 UH	444	int i;
	445
	446	/* Write_Start_Status */
a1bb33af UH	447	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	448	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	449
fed16f06	450	/* Start_Config_Outside_Device ? */
a1bb33af UH	451	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	452	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	453
fed16f06	454	/* SetData_To_Frequence_Reg */
a1bb33af UH	455	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
a1bb33af UH	456
fed16f06	457	/* SetMemory_Length */
a1bb33af UH	458	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
a1bb33af UH	459
fed16f06	460	/* Sele_Inside_Outside_Clock */
a1bb33af UH	461	gl_reg_write(devh, CLOCK_SOURCE, 0x03);
a1bb33af UH	462
fed16f06	463	/* Set_Trigger_Status */
a1bb33af UH	464	for (i = 0; i < 9; i++)
	465	gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
	466
	467	__analyzer_set_trigger_count(devh, g_trigger_count);
	468
fed16f06	469	/* Set_Trigger_Level */
a1bb33af UH	470	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	471	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	472	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	473	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
	474
fed16f06 UH	475	/* Size of actual memory >> 2 */
fed16f06 UH	476	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
a1bb33af UH	477	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
a1bb33af UH	478
fed16f06	479	/* Set_Dont_Care_TriggerBar */
0ab0cb94 TY	480	if (g_triggerbar_addr)
	481	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x00);
	482	else
	483	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
a1bb33af	484
fed16f06	485	/* Enable_Status */
a1bb33af UH	486	analyzer_set_filter(devh);
a1bb33af UH	487
fed16f06	488	/* Set_Enable_Delay_Time */
a1bb33af UH	489	gl_reg_write(devh, 0x7a, 0x00);
	490	gl_reg_write(devh, 0x7b, 0x00);
	491	analyzer_write_enable_insert_data(devh);
fed16f06	492	__analyzer_set_compression(devh, g_compression);
a1bb33af UH	493	}
a1bb33af UH	494
ca070ed9	495	SR_PRIV void analyzer_add_trigger(int channel, int type)
a1bb33af	496	{
0ab0cb94 TY	497	switch (type) {
	498	case TRIGGER_HIGH:
	499	g_trigger_status[channel / 4] \|= 1 << (channel % 4 * 2);
	500	break;
	501	case TRIGGER_LOW:
	502	g_trigger_status[channel / 4] \|= 2 << (channel % 4 * 2);
	503	break;
	504	#if 0
	505	case TRIGGER_POSEDGE:
	506	g_trigger_status[8] = 0x40 \| channel;
	507	break;
	508	case TRIGGER_NEGEDGE:
	509	g_trigger_status[8] = 0x80 \| channel;
	510	break;
	511	case TRIGGER_ANYEDGE:
	512	g_trigger_status[8] = 0xc0 \| channel;
	513	break;
	514	#endif
	515	default:
	516	break;
a1bb33af UH	517	}
	518	}
	519
ca070ed9	520	SR_PRIV void analyzer_add_filter(int channel, int type)
a1bb33af	521	{
fed16f06 UH	522	int i;
fed16f06 UH	523
a1bb33af UH	524	if (type != FILTER_HIGH && type != FILTER_LOW)
	525	return;
	526	if ((channel & 0xf) >= 8)
	527	return;
	528
a1bb33af UH	529	if (channel & CHANNEL_A)
	530	i = 0;
	531	else if (channel & CHANNEL_B)
	532	i = 2;
	533	else if (channel & CHANNEL_C)
	534	i = 4;
	535	else if (channel & CHANNEL_D)
	536	i = 6;
	537	else
	538	return;
fed16f06	539
a1bb33af UH	540	if ((channel & 0xf) >= 4) {
	541	i++;
	542	channel -= 4;
	543	}
fed16f06 UH	544
	545	g_filter_status[i] \|=
	546	1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
	547
a1bb33af UH	548	g_filter_enable = 1;
	549	}
	550
ca070ed9	551	SR_PRIV void analyzer_set_trigger_count(int count)
a1bb33af UH	552	{
	553	g_trigger_count = count;
	554	}
	555
ca070ed9	556	SR_PRIV void analyzer_set_freq(int freq, int scale)
a1bb33af UH	557	{
	558	g_freq_value = freq;
	559	g_freq_scale = scale;
	560	}
	561
ca070ed9	562	SR_PRIV void analyzer_set_memory_size(unsigned int size)
a1bb33af UH	563	{
	564	g_memory_size = size;
	565	}
	566
ca070ed9	567	SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
a1bb33af UH	568	{
	569	g_ramsize_triggerbar_addr = address;
	570	}
	571
ca070ed9	572	SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
a1bb33af UH	573	{
	574	g_triggerbar_addr = address;
	575	}
	576
0ab0cb94 TY	577	SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
	578	{
	579	return gl_reg_read(devh, DEV_STATUS);
	580	}
	581
ca070ed9	582	SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
a1bb33af	583	{
bb7ef793	584	return gl_reg_read(devh, DEV_ID1) << 8 \| gl_reg_read(devh, DEV_ID0);
a1bb33af UH	585	}
a1bb33af UH	586
ca070ed9	587	SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
a1bb33af	588	{
fed16f06 UH	589	return gl_reg_read(devh, STOP_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	590	STOP_ADDRESS1) << 8 \| gl_reg_read(devh, STOP_ADDRESS0);
a1bb33af UH	591	}
a1bb33af UH	592
ca070ed9	593	SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
a1bb33af	594	{
fed16f06 UH	595	return gl_reg_read(devh, NOW_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	596	NOW_ADDRESS1) << 8 \| gl_reg_read(devh, NOW_ADDRESS0);
a1bb33af UH	597	}
a1bb33af UH	598
ca070ed9	599	SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
a1bb33af	600	{
fed16f06 UH	601	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	602	TRIGGER_ADDRESS1) << 8 \| gl_reg_read(devh, TRIGGER_ADDRESS0);
a1bb33af UH	603	}
a1bb33af UH	604
ca070ed9	605	SR_PRIV void analyzer_set_compression(unsigned int type)
a1bb33af UH	606	{
	607	g_compression = type;
	608	}
	609
ca070ed9	610	SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
a1bb33af UH	611	{
	612	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
	613	}
	614
ca070ed9	615	SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
a1bb33af UH	616	{
	617	analyzer_wait(devh, STATUS_READY \| 8, STATUS_BUSY);
	618	}
	619
ca070ed9 UH	620	SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
ca070ed9 UH	621	void *output, unsigned int output_len)
a1bb33af UH	622	{
	623	unsigned char *in = input;
	624	unsigned char *out = output;
	625	unsigned int A, B, C, count;
	626	unsigned int written = 0;
	627
	628	while (input_len > 0) {
	629	A = *in++;
	630	B = *in++;
	631	C = *in++;
	632	count = (*in++) + 1;
	633
	634	if (count > output_len)
	635	count = output_len;
	636	output_len -= count;
	637	written += count;
	638
	639	while (count--) {
	640	*out++ = A;
	641	*out++ = B;
	642	*out++ = C;
fed16f06	643	out++ = 0; / Channel D */
a1bb33af UH	644	}
	645
	646	input_len -= 4;
	647	if (output_len == 0)
	648	break;
	649	}
	650
	651	return written;
	652	}