[libsigrok.git] / hardware / zeroplus-logic-cube / analyzer.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *  THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <assert.h>
#include "analyzer.h"
#include "gl_usb.h"
#include "libsigrok-internal.h"

enum {
	HARD_DATA_CHECK_SUM		= 0x00,
	PASS_WORD,

	DEV_ID0				= 0x10,
	DEV_ID1,

	START_STATUS			= 0x20,
	DEV_STATUS			= 0x21,
	FREQUENCY_REG0			= 0x30,
	FREQUENCY_REG1,
	FREQUENCY_REG2,
	FREQUENCY_REG3,
	FREQUENCY_REG4,
	MEMORY_LENGTH,
	CLOCK_SOURCE,

	TRIGGER_STATUS0			= 0x40,
	TRIGGER_STATUS1,
	TRIGGER_STATUS2,
	TRIGGER_STATUS3,
	TRIGGER_STATUS4,
	TRIGGER_STATUS5,
	TRIGGER_STATUS6,
	TRIGGER_STATUS7,
	TRIGGER_STATUS8,

	TRIGGER_COUNT0			= 0x50,
	TRIGGER_COUNT1,

	TRIGGER_LEVEL0			= 0x55,
	TRIGGER_LEVEL1,
	TRIGGER_LEVEL2,
	TRIGGER_LEVEL3,

	RAMSIZE_TRIGGERBAR_ADDRESS0	= 0x60,
	RAMSIZE_TRIGGERBAR_ADDRESS1,
	RAMSIZE_TRIGGERBAR_ADDRESS2,
	TRIGGERBAR_ADDRESS0,
	TRIGGERBAR_ADDRESS1,
	TRIGGERBAR_ADDRESS2,
	DONT_CARE_TRIGGERBAR,

	FILTER_ENABLE			= 0x70,
	FILTER_STATUS,

	ENABLE_DELAY_TIME0		= 0x7a,
	ENABLE_DELAY_TIME1,

	ENABLE_INSERT_DATA0		= 0x80,
	ENABLE_INSERT_DATA1,
	ENABLE_INSERT_DATA2,
	ENABLE_INSERT_DATA3,
	COMPRESSION_TYPE0,
	COMPRESSION_TYPE1,

	TRIGGER_ADDRESS0		= 0x90,
	TRIGGER_ADDRESS1,
	TRIGGER_ADDRESS2,

	NOW_ADDRESS0			= 0x96,
	NOW_ADDRESS1,
	NOW_ADDRESS2,

	STOP_ADDRESS0			= 0x9b,
	STOP_ADDRESS1,
	STOP_ADDRESS2,

	READ_RAM_STATUS			= 0xa0,
};

static int g_trigger_status[9] = { 0 };
static int g_trigger_count = 1;
static int g_filter_status[8] = { 0 };
static int g_filter_enable = 0;

static int g_freq_value = 100;
static int g_freq_scale = FREQ_SCALE_MHZ;
static int g_memory_size = MEMORY_SIZE_512K;
static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
static int g_triggerbar_addr = 0x3fe;
static int g_compression = COMPRESSION_NONE;

/* Maybe unk specifies an "endpoint" or "register" of sorts. */
static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
				 unsigned char flags)
{
	assert(unk <= 3);
	return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
}

static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	int reg0 = 0, divisor = 0, reg2 = 0;

	switch (scale) {
	case FREQ_SCALE_MHZ: /* MHz */
		if (freq >= 100 && freq <= 200) {
			reg0 = freq * 0.1;
			divisor = 1;
			reg2 = 0;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.2;
			divisor = 2;
			reg2 = 0;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 1;
				break;
			} else {
				reg0 = freq * 0.5;
				divisor = 5;
				reg2 = 1;
				break;
			}
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 2;
			break;
		}
		if (freq == 1) {
			divisor = 5;
			reg2 = 16;
			reg0 = 5;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_HZ: /* Hz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 10;
			reg2 = 64;
			break;
		}
		if (freq >= 300 && freq < 500) {
			reg0 = freq * 0.005 * 8;
			divisor = 5;
			reg2 = 67;
			break;
		}
		if (freq >= 100 && freq < 300) {
			reg0 = freq * 0.005 * 16;
			divisor = 5;
			reg2 = 68;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_KHZ: /* kHz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 5;
			reg2 = 17;
			break;
		}
		if (freq >= 100 && freq < 500) {
			reg0 = freq * 0.05;
			divisor = 5;
			reg2 = 32;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.1;
			divisor = 5;
			reg2 = 33;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 49;
				break;
			}
			reg0 = freq * 0.5;
			divisor = 5;
			reg2 = 48;
			break;
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 50;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	default:
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	}

	sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, divisor, reg0, 0x02, reg2);

	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
		return -1; /* Divisor maybe? */

	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
		return -1; /* 10 / 0.2 */

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1; /* Always 2 */

	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
		return -1;

	return 0;
}

static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
						   unsigned int address)
{
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
					      unsigned int address)
{
	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_compression(libusb_device_handle *devh,
				       unsigned int type)
{
	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
}

static void __analyzer_set_trigger_count(libusb_device_handle *devh,
					 unsigned int count)
{
	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
}

static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
{
	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
}

static void analyzer_set_filter(libusb_device_handle *devh)
{
	int i;
	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	for (i = 0; i < 8; i++)
		gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
}

SR_PRIV void analyzer_reset(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);	// reset device
	analyzer_write_status(devh, 3, STATUS_FLAG_RESET);	// reset device
}

SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
{
	int status;
	while (1) {
		status = gl_reg_read(devh, DEV_STATUS);
		if ((status & set) && ((status & unset) == 0))
			return;
	}
}

SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
{
	int i;

	analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);

	for (i = 0; i < 8; i++)
		(void)gl_reg_read(devh, READ_RAM_STATUS);
}

SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
		       unsigned int size)
{
	return gl_read_bulk(devh, buffer, size);
}

SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
}

SR_PRIV void analyzer_configure(libusb_device_handle *devh)
{
	int i;

	/* Write_Start_Status */
	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* Start_Config_Outside_Device ? */
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* SetData_To_Frequence_Reg */
	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);

	/* SetMemory_Length */
	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);

	/* Sele_Inside_Outside_Clock */
	gl_reg_write(devh, CLOCK_SOURCE, 0x03);

	/* Set_Trigger_Status */
	for (i = 0; i < 9; i++)
		gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);

	__analyzer_set_trigger_count(devh, g_trigger_count);

	/* Set_Trigger_Level */
	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);

	/* Size of actual memory >> 2 */
	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);

	/* Set_Dont_Care_TriggerBar */
	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);

	/* Enable_Status */
	analyzer_set_filter(devh);

	/* Set_Enable_Delay_Time */
	gl_reg_write(devh, 0x7a, 0x00);
	gl_reg_write(devh, 0x7b, 0x00);
	analyzer_write_enable_insert_data(devh);
	__analyzer_set_compression(devh, g_compression);
}

SR_PRIV void analyzer_add_trigger(int channel, int type)
{
	int i;

	if ((channel & 0xf) >= 8)
		return;

	if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
		if (channel & CHANNEL_A)
			i = 0;
		else if (channel & CHANNEL_B)
			i = 2;
		else if (channel & CHANNEL_C)
			i = 4;
		else if (channel & CHANNEL_D)
			i = 6;
		else
			return;
		if ((channel & 0xf) >= 4) {
			i++;
			channel -= 4;
		}
		g_trigger_status[i] |=
		    1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
	} else {
		if (type == TRIGGER_POSEDGE)
			g_trigger_status[8] = 0x40;
		else if (type == TRIGGER_NEGEDGE)
			g_trigger_status[8] = 0x80;
		else
			g_trigger_status[8] = 0xc0;

		/* FIXME: Just guessed the index; need to verify. */
		if (channel & CHANNEL_B)
			g_trigger_status[8] += 8;
		else if (channel & CHANNEL_C)
			g_trigger_status[8] += 16;
		else if (channel & CHANNEL_D)
			g_trigger_status[8] += 24;
		g_trigger_status[8] += channel % 8;
	}
}

SR_PRIV void analyzer_add_filter(int channel, int type)
{
	int i;

	if (type != FILTER_HIGH && type != FILTER_LOW)
		return;
	if ((channel & 0xf) >= 8)
		return;

	if (channel & CHANNEL_A)
		i = 0;
	else if (channel & CHANNEL_B)
		i = 2;
	else if (channel & CHANNEL_C)
		i = 4;
	else if (channel & CHANNEL_D)
		i = 6;
	else
		return;

	if ((channel & 0xf) >= 4) {
		i++;
		channel -= 4;
	}

	g_filter_status[i] |=
	    1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));

	g_filter_enable = 1;
}

SR_PRIV void analyzer_set_trigger_count(int count)
{
	g_trigger_count = count;
}

SR_PRIV void analyzer_set_freq(int freq, int scale)
{
	g_freq_value = freq;
	g_freq_scale = scale;
}

SR_PRIV void analyzer_set_memory_size(unsigned int size)
{
	g_memory_size = size;
}

SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
{
	g_ramsize_triggerbar_addr = address;
}

SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
{
	g_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
}

SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
			STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
			NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
		TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
}

SR_PRIV void analyzer_set_compression(unsigned int type)
{
	g_compression = type;
}

SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
}

SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
}

SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
				void *output, unsigned int output_len)
{
	unsigned char *in = input;
	unsigned char *out = output;
	unsigned int A, B, C, count;
	unsigned int written = 0;

	while (input_len > 0) {
		A = *in++;
		B = *in++;
		C = *in++;
		count = (*in++) + 1;

		if (count > output_len)
			count = output_len;
		output_len -= count;
		written += count;

		while (count--) {
			*out++ = A;
			*out++ = B;
			*out++ = C;
			*out++ = 0; /* Channel D */
		}

		input_len -= 4;
		if (output_len == 0)
			break;
	}

	return written;
}
Commit	Line	Data
a1bb33af	1	/*
fed16f06 UH	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
	5	* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or
	9	* without modification, are permitted provided that the following
	10	* conditions are met:
	11	*
	12	* * Redistributions of source code must retain the above copyright notice,
	13	* this list of conditions and the following disclaimer.
	14	*
	15	* * Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	29	* THE POSSIBILITY OF SUCH DAMAGE.
	30	*/
a1bb33af	31
fed16f06	32	#include <assert.h>
a1bb33af UH	33	#include "analyzer.h"
a1bb33af UH	34	#include "gl_usb.h"
45c59c8b	35	#include "libsigrok-internal.h"
a1bb33af UH	36
a1bb33af UH	37	enum {
fed16f06	38	HARD_DATA_CHECK_SUM = 0x00,
a1bb33af UH	39	PASS_WORD,
a1bb33af UH	40
bb7ef793 UH	41	DEV_ID0 = 0x10,
bb7ef793 UH	42	DEV_ID1,
a1bb33af	43
fed16f06	44	START_STATUS = 0x20,
bb7ef793	45	DEV_STATUS = 0x21,
fed16f06	46	FREQUENCY_REG0 = 0x30,
a1bb33af UH	47	FREQUENCY_REG1,
	48	FREQUENCY_REG2,
	49	FREQUENCY_REG3,
	50	FREQUENCY_REG4,
	51	MEMORY_LENGTH,
	52	CLOCK_SOURCE,
	53
fed16f06	54	TRIGGER_STATUS0 = 0x40,
a1bb33af UH	55	TRIGGER_STATUS1,
	56	TRIGGER_STATUS2,
	57	TRIGGER_STATUS3,
	58	TRIGGER_STATUS4,
	59	TRIGGER_STATUS5,
	60	TRIGGER_STATUS6,
	61	TRIGGER_STATUS7,
	62	TRIGGER_STATUS8,
	63
fed16f06	64	TRIGGER_COUNT0 = 0x50,
a1bb33af UH	65	TRIGGER_COUNT1,
a1bb33af UH	66
fed16f06	67	TRIGGER_LEVEL0 = 0x55,
a1bb33af UH	68	TRIGGER_LEVEL1,
	69	TRIGGER_LEVEL2,
	70	TRIGGER_LEVEL3,
	71
	72	RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
	73	RAMSIZE_TRIGGERBAR_ADDRESS1,
	74	RAMSIZE_TRIGGERBAR_ADDRESS2,
	75	TRIGGERBAR_ADDRESS0,
	76	TRIGGERBAR_ADDRESS1,
	77	TRIGGERBAR_ADDRESS2,
	78	DONT_CARE_TRIGGERBAR,
	79
	80	FILTER_ENABLE = 0x70,
	81	FILTER_STATUS,
	82
fed16f06	83	ENABLE_DELAY_TIME0 = 0x7a,
a1bb33af UH	84	ENABLE_DELAY_TIME1,
a1bb33af UH	85
fed16f06	86	ENABLE_INSERT_DATA0 = 0x80,
a1bb33af UH	87	ENABLE_INSERT_DATA1,
	88	ENABLE_INSERT_DATA2,
	89	ENABLE_INSERT_DATA3,
	90	COMPRESSION_TYPE0,
	91	COMPRESSION_TYPE1,
	92
fed16f06	93	TRIGGER_ADDRESS0 = 0x90,
a1bb33af UH	94	TRIGGER_ADDRESS1,
	95	TRIGGER_ADDRESS2,
	96
fed16f06	97	NOW_ADDRESS0 = 0x96,
a1bb33af UH	98	NOW_ADDRESS1,
	99	NOW_ADDRESS2,
	100
fed16f06	101	STOP_ADDRESS0 = 0x9b,
a1bb33af UH	102	STOP_ADDRESS1,
	103	STOP_ADDRESS2,
	104
fed16f06	105	READ_RAM_STATUS = 0xa0,
a1bb33af UH	106	};
a1bb33af UH	107
fed16f06	108	static int g_trigger_status[9] = { 0 };
a1bb33af	109	static int g_trigger_count = 1;
fed16f06	110	static int g_filter_status[8] = { 0 };
a1bb33af UH	111	static int g_filter_enable = 0;
	112
	113	static int g_freq_value = 100;
	114	static int g_freq_scale = FREQ_SCALE_MHZ;
	115	static int g_memory_size = MEMORY_SIZE_512K;
fed16f06	116	static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
a1bb33af UH	117	static int g_triggerbar_addr = 0x3fe;
	118	static int g_compression = COMPRESSION_NONE;
	119
fed16f06 UH	120	/* Maybe unk specifies an "endpoint" or "register" of sorts. */
	121	static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
	122	unsigned char flags)
a1bb33af UH	123	{
	124	assert(unk <= 3);
	125	return gl_reg_write(devh, START_STATUS, unk << 6 \| flags);
	126	}
	127
	128	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
	129	{
fed16f06 UH	130	int reg0 = 0, divisor = 0, reg2 = 0;
fed16f06 UH	131
a1bb33af	132	switch (scale) {
fed16f06 UH	133	case FREQ_SCALE_MHZ: /* MHz */
	134	if (freq >= 100 && freq <= 200) {
	135	reg0 = freq * 0.1;
	136	divisor = 1;
	137	reg2 = 0;
	138	break;
	139	}
	140	if (freq >= 50 && freq < 100) {
	141	reg0 = freq * 0.2;
	142	divisor = 2;
	143	reg2 = 0;
	144	break;
	145	}
	146	if (freq >= 10 && freq < 50) {
	147	if (freq == 25) {
	148	reg0 = 25;
a1bb33af	149	divisor = 5;
fed16f06	150	reg2 = 1;
a1bb33af	151	break;
fed16f06 UH	152	} else {
fed16f06 UH	153	reg0 = freq * 0.5;
a1bb33af	154	divisor = 5;
fed16f06	155	reg2 = 1;
a1bb33af UH	156	break;
a1bb33af UH	157	}
fed16f06 UH	158	}
fed16f06 UH	159	if (freq >= 2 && freq < 10) {
a1bb33af	160	divisor = 5;
fed16f06 UH	161	reg0 = freq * 2;
fed16f06 UH	162	reg2 = 2;
a1bb33af	163	break;
fed16f06 UH	164	}
fed16f06 UH	165	if (freq == 1) {
a1bb33af	166	divisor = 5;
fed16f06	167	reg2 = 16;
a1bb33af	168	reg0 = 5;
fed16f06 UH	169	break;
	170	}
	171	divisor = 5;
	172	reg0 = 5;
	173	reg2 = 64;
	174	break;
	175	case FREQ_SCALE_HZ: /* Hz */
	176	if (freq >= 500 && freq < 1000) {
	177	reg0 = freq * 0.01;
	178	divisor = 10;
a1bb33af UH	179	reg2 = 64;
a1bb33af UH	180	break;
fed16f06 UH	181	}
	182	if (freq >= 300 && freq < 500) {
	183	reg0 = freq * 0.005 * 8;
	184	divisor = 5;
	185	reg2 = 67;
	186	break;
	187	}
	188	if (freq >= 100 && freq < 300) {
	189	reg0 = freq * 0.005 * 16;
	190	divisor = 5;
	191	reg2 = 68;
	192	break;
	193	}
	194	divisor = 5;
	195	reg0 = 5;
	196	reg2 = 64;
	197	break;
38ba2522	198	case FREQ_SCALE_KHZ: /* kHz */
fed16f06 UH	199	if (freq >= 500 && freq < 1000) {
	200	reg0 = freq * 0.01;
	201	divisor = 5;
	202	reg2 = 17;
	203	break;
	204	}
	205	if (freq >= 100 && freq < 500) {
	206	reg0 = freq * 0.05;
	207	divisor = 5;
	208	reg2 = 32;
	209	break;
	210	}
	211	if (freq >= 50 && freq < 100) {
	212	reg0 = freq * 0.1;
	213	divisor = 5;
	214	reg2 = 33;
	215	break;
	216	}
	217	if (freq >= 10 && freq < 50) {
	218	if (freq == 25) {
	219	reg0 = 25;
a1bb33af	220	divisor = 5;
fed16f06	221	reg2 = 49;
a1bb33af UH	222	break;
a1bb33af UH	223	}
fed16f06	224	reg0 = freq * 0.5;
a1bb33af	225	divisor = 5;
fed16f06	226	reg2 = 48;
a1bb33af	227	break;
fed16f06 UH	228	}
fed16f06 UH	229	if (freq >= 2 && freq < 10) {
a1bb33af	230	divisor = 5;
fed16f06 UH	231	reg0 = freq * 2;
fed16f06 UH	232	reg2 = 50;
a1bb33af	233	break;
fed16f06 UH	234	}
	235	divisor = 5;
	236	reg0 = 5;
	237	reg2 = 64;
	238	break;
	239	default:
	240	divisor = 5;
	241	reg0 = 5;
	242	reg2 = 64;
	243	break;
a1bb33af	244	}
c13536fa UH	245
	246	sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
	247	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	248	freq, scale, divisor, reg0, 0x02, reg2);
	249
a1bb33af	250	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
fed16f06	251	return -1; /* Divisor maybe? */
a1bb33af UH	252
a1bb33af UH	253	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
fed16f06	254	return -1; /* 10 / 0.2 */
a1bb33af UH	255
a1bb33af UH	256	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
fed16f06	257	return -1; /* Always 2 */
a1bb33af UH	258
	259	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
	260	return -1;
	261
	262	return 0;
	263	}
	264
fed16f06 UH	265	static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
fed16f06 UH	266	unsigned int address)
a1bb33af	267	{
fed16f06 UH	268	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	269	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	270	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	271	}
	272
fed16f06 UH	273	static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
fed16f06 UH	274	unsigned int address)
a1bb33af	275	{
fed16f06 UH	276	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	277	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	278	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	279	}
	280
fed16f06 UH	281	static void __analyzer_set_compression(libusb_device_handle *devh,
fed16f06 UH	282	unsigned int type)
a1bb33af UH	283	{
	284	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	285	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
	286	}
	287
fed16f06 UH	288	static void __analyzer_set_trigger_count(libusb_device_handle *devh,
fed16f06 UH	289	unsigned int count)
a1bb33af UH	290	{
	291	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	292	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
	293	}
	294
	295	static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
	296	{
	297	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	298	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	299	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	300	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
	301	}
	302
	303	static void analyzer_set_filter(libusb_device_handle *devh)
	304	{
	305	int i;
	306	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	307	for (i = 0; i < 8; i++)
	308	gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
	309	}
	310
ca070ed9	311	SR_PRIV void analyzer_reset(libusb_device_handle *devh)
a1bb33af	312	{
fed16f06 UH	313	analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
fed16f06 UH	314	analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
a1bb33af UH	315	}
a1bb33af UH	316
ca070ed9	317	SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
a1bb33af UH	318	{
	319	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	320	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	321	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	322	}
	323
ca070ed9	324	SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
a1bb33af UH	325	{
a1bb33af UH	326	int status;
fed16f06	327	while (1) {
bb7ef793	328	status = gl_reg_read(devh, DEV_STATUS);
a1bb33af UH	329	if ((status & set) && ((status & unset) == 0))
	330	return;
	331	}
	332	}
	333
ca070ed9	334	SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
a1bb33af UH	335	{
	336	int i;
	337
	338	analyzer_write_status(devh, 3, STATUS_FLAG_20 \| STATUS_FLAG_READ);
	339
	340	for (i = 0; i < 8; i++)
	341	(void)gl_reg_read(devh, READ_RAM_STATUS);
	342	}
	343
ca070ed9	344	SR_PRIV int analyzer_read_data(libusb_device_handle devh, void buffer,
fed16f06	345	unsigned int size)
a1bb33af UH	346	{
	347	return gl_read_bulk(devh, buffer, size);
	348	}
	349
ca070ed9	350	SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
a1bb33af UH	351	{
	352	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	353	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
	354	}
	355
ca070ed9	356	SR_PRIV void analyzer_start(libusb_device_handle *devh)
a1bb33af UH	357	{
	358	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	359	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	360	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	361	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
	362	}
	363
ca070ed9	364	SR_PRIV void analyzer_configure(libusb_device_handle *devh)
a1bb33af	365	{
fed16f06 UH	366	int i;
	367
	368	/* Write_Start_Status */
a1bb33af UH	369	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	370	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	371
fed16f06	372	/* Start_Config_Outside_Device ? */
a1bb33af UH	373	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	374	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	375
fed16f06	376	/* SetData_To_Frequence_Reg */
a1bb33af UH	377	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
a1bb33af UH	378
fed16f06	379	/* SetMemory_Length */
a1bb33af UH	380	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
a1bb33af UH	381
fed16f06	382	/* Sele_Inside_Outside_Clock */
a1bb33af UH	383	gl_reg_write(devh, CLOCK_SOURCE, 0x03);
a1bb33af UH	384
fed16f06	385	/* Set_Trigger_Status */
a1bb33af UH	386	for (i = 0; i < 9; i++)
	387	gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
	388
	389	__analyzer_set_trigger_count(devh, g_trigger_count);
	390
fed16f06	391	/* Set_Trigger_Level */
a1bb33af UH	392	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	393	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	394	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	395	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
	396
fed16f06 UH	397	/* Size of actual memory >> 2 */
fed16f06 UH	398	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
a1bb33af UH	399	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
a1bb33af UH	400
fed16f06	401	/* Set_Dont_Care_TriggerBar */
a1bb33af UH	402	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
a1bb33af UH	403
fed16f06	404	/* Enable_Status */
a1bb33af UH	405	analyzer_set_filter(devh);
a1bb33af UH	406
fed16f06	407	/* Set_Enable_Delay_Time */
a1bb33af UH	408	gl_reg_write(devh, 0x7a, 0x00);
	409	gl_reg_write(devh, 0x7b, 0x00);
	410	analyzer_write_enable_insert_data(devh);
fed16f06	411	__analyzer_set_compression(devh, g_compression);
a1bb33af UH	412	}
a1bb33af UH	413
ca070ed9	414	SR_PRIV void analyzer_add_trigger(int channel, int type)
a1bb33af	415	{
fed16f06 UH	416	int i;
fed16f06 UH	417
a1bb33af UH	418	if ((channel & 0xf) >= 8)
	419	return;
	420
	421	if (type == TRIGGER_HIGH \|\| type == TRIGGER_LOW) {
a1bb33af UH	422	if (channel & CHANNEL_A)
	423	i = 0;
	424	else if (channel & CHANNEL_B)
	425	i = 2;
	426	else if (channel & CHANNEL_C)
	427	i = 4;
	428	else if (channel & CHANNEL_D)
	429	i = 6;
	430	else
	431	return;
	432	if ((channel & 0xf) >= 4) {
	433	i++;
	434	channel -= 4;
	435	}
fed16f06 UH	436	g_trigger_status[i] \|=
fed16f06 UH	437	1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
a1bb33af UH	438	} else {
	439	if (type == TRIGGER_POSEDGE)
	440	g_trigger_status[8] = 0x40;
fed16f06	441	else if (type == TRIGGER_NEGEDGE)
a1bb33af UH	442	g_trigger_status[8] = 0x80;
	443	else
	444	g_trigger_status[8] = 0xc0;
	445
fed16f06	446	/* FIXME: Just guessed the index; need to verify. */
a1bb33af UH	447	if (channel & CHANNEL_B)
	448	g_trigger_status[8] += 8;
	449	else if (channel & CHANNEL_C)
	450	g_trigger_status[8] += 16;
	451	else if (channel & CHANNEL_D)
	452	g_trigger_status[8] += 24;
	453	g_trigger_status[8] += channel % 8;
	454	}
	455	}
	456
ca070ed9	457	SR_PRIV void analyzer_add_filter(int channel, int type)
a1bb33af	458	{
fed16f06 UH	459	int i;
fed16f06 UH	460
a1bb33af UH	461	if (type != FILTER_HIGH && type != FILTER_LOW)
	462	return;
	463	if ((channel & 0xf) >= 8)
	464	return;
	465
a1bb33af UH	466	if (channel & CHANNEL_A)
	467	i = 0;
	468	else if (channel & CHANNEL_B)
	469	i = 2;
	470	else if (channel & CHANNEL_C)
	471	i = 4;
	472	else if (channel & CHANNEL_D)
	473	i = 6;
	474	else
	475	return;
fed16f06	476
a1bb33af UH	477	if ((channel & 0xf) >= 4) {
	478	i++;
	479	channel -= 4;
	480	}
fed16f06 UH	481
	482	g_filter_status[i] \|=
	483	1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
	484
a1bb33af UH	485	g_filter_enable = 1;
	486	}
	487
ca070ed9	488	SR_PRIV void analyzer_set_trigger_count(int count)
a1bb33af UH	489	{
	490	g_trigger_count = count;
	491	}
	492
ca070ed9	493	SR_PRIV void analyzer_set_freq(int freq, int scale)
a1bb33af UH	494	{
	495	g_freq_value = freq;
	496	g_freq_scale = scale;
	497	}
	498
ca070ed9	499	SR_PRIV void analyzer_set_memory_size(unsigned int size)
a1bb33af UH	500	{
	501	g_memory_size = size;
	502	}
	503
ca070ed9	504	SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
a1bb33af UH	505	{
	506	g_ramsize_triggerbar_addr = address;
	507	}
	508
ca070ed9	509	SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
a1bb33af UH	510	{
	511	g_triggerbar_addr = address;
	512	}
	513
ca070ed9	514	SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
a1bb33af	515	{
bb7ef793	516	return gl_reg_read(devh, DEV_ID1) << 8 \| gl_reg_read(devh, DEV_ID0);
a1bb33af UH	517	}
a1bb33af UH	518
ca070ed9	519	SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
a1bb33af	520	{
fed16f06 UH	521	return gl_reg_read(devh, STOP_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	522	STOP_ADDRESS1) << 8 \| gl_reg_read(devh, STOP_ADDRESS0);
a1bb33af UH	523	}
a1bb33af UH	524
ca070ed9	525	SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
a1bb33af	526	{
fed16f06 UH	527	return gl_reg_read(devh, NOW_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	528	NOW_ADDRESS1) << 8 \| gl_reg_read(devh, NOW_ADDRESS0);
a1bb33af UH	529	}
a1bb33af UH	530
ca070ed9	531	SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
a1bb33af	532	{
fed16f06 UH	533	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	534	TRIGGER_ADDRESS1) << 8 \| gl_reg_read(devh, TRIGGER_ADDRESS0);
a1bb33af UH	535	}
a1bb33af UH	536
ca070ed9	537	SR_PRIV void analyzer_set_compression(unsigned int type)
a1bb33af UH	538	{
	539	g_compression = type;
	540	}
	541
ca070ed9	542	SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
a1bb33af UH	543	{
	544	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
	545	}
	546
ca070ed9	547	SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
a1bb33af UH	548	{
	549	analyzer_wait(devh, STATUS_READY \| 8, STATUS_BUSY);
	550	}
	551
ca070ed9 UH	552	SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
ca070ed9 UH	553	void *output, unsigned int output_len)
a1bb33af UH	554	{
	555	unsigned char *in = input;
	556	unsigned char *out = output;
	557	unsigned int A, B, C, count;
	558	unsigned int written = 0;
	559
	560	while (input_len > 0) {
	561	A = *in++;
	562	B = *in++;
	563	C = *in++;
	564	count = (*in++) + 1;
	565
	566	if (count > output_len)
	567	count = output_len;
	568	output_len -= count;
	569	written += count;
	570
	571	while (count--) {
	572	*out++ = A;
	573	*out++ = B;
	574	*out++ = C;
fed16f06	575	out++ = 0; / Channel D */
a1bb33af UH	576	}
	577
	578	input_len -= 4;
	579	if (output_len == 0)
	580	break;
	581	}
	582
	583	return written;
	584	}