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Commit | Line | Data |
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01cf8814 DR |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> | |
a2936073 | 5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> |
01cf8814 DR |
6 | * |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
8a839354 UH |
11 | * |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
01cf8814 DR |
19 | */ |
20 | ||
21 | #include <stdio.h> | |
22 | #include <stdlib.h> | |
23 | #include <string.h> | |
24 | #include <unistd.h> | |
25 | #include <fcntl.h> | |
26 | #include <sys/time.h> | |
27 | #include <inttypes.h> | |
28 | #include <glib.h> | |
29 | #include <libudev.h> | |
01cf8814 | 30 | #include <arpa/inet.h> |
45c59c8b BV |
31 | #include "libsigrok.h" |
32 | #include "libsigrok-internal.h" | |
01cf8814 DR |
33 | #include "link-mso19.h" |
34 | ||
35 | #define USB_VENDOR "3195" | |
36 | #define USB_PRODUCT "f190" | |
37 | ||
464d12c7 KS |
38 | #define NUM_PROBES 8 |
39 | ||
915f7cc8 | 40 | static const int hwcaps[] = { |
5a2326a7 UH |
41 | SR_HWCAP_LOGIC_ANALYZER, |
42 | // SR_HWCAP_OSCILLOSCOPE, | |
43 | // SR_HWCAP_PAT_GENERATOR, | |
01cf8814 | 44 | |
5a2326a7 UH |
45 | SR_HWCAP_SAMPLERATE, |
46 | // SR_HWCAP_CAPTURE_RATIO, | |
47 | SR_HWCAP_LIMIT_SAMPLES, | |
01cf8814 DR |
48 | 0, |
49 | }; | |
50 | ||
d261dbbf UH |
51 | /* |
52 | * Probes are numbered 0 to 7. | |
53 | * | |
54 | * See also: http://www.linkinstruments.com/images/mso19_1113.gif | |
55 | */ | |
464d12c7 | 56 | static const char *probe_names[NUM_PROBES + 1] = { |
78693401 | 57 | "0", "1", "2", "3", "4", "5", "6", "7", |
464d12c7 KS |
58 | NULL, |
59 | }; | |
60 | ||
a533743d | 61 | static const uint64_t supported_samplerates[] = { |
c9140419 UH |
62 | SR_HZ(100), |
63 | SR_HZ(200), | |
64 | SR_HZ(500), | |
59df0c77 UH |
65 | SR_KHZ(1), |
66 | SR_KHZ(2), | |
67 | SR_KHZ(5), | |
68 | SR_KHZ(10), | |
69 | SR_KHZ(20), | |
70 | SR_KHZ(50), | |
71 | SR_KHZ(100), | |
72 | SR_KHZ(200), | |
73 | SR_KHZ(500), | |
74 | SR_MHZ(1), | |
75 | SR_MHZ(2), | |
76 | SR_MHZ(5), | |
77 | SR_MHZ(10), | |
78 | SR_MHZ(20), | |
79 | SR_MHZ(50), | |
80 | SR_MHZ(100), | |
81 | SR_MHZ(200), | |
82 | 0, | |
01cf8814 DR |
83 | }; |
84 | ||
a533743d | 85 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
86 | 0, |
87 | 0, | |
88 | 0, | |
59df0c77 | 89 | supported_samplerates, |
01cf8814 DR |
90 | }; |
91 | ||
d68e2d1a | 92 | static GSList *dev_insts = NULL; |
01cf8814 | 93 | |
d68e2d1a UH |
94 | static int mso_send_control_message(struct sr_dev_inst *sdi, |
95 | uint16_t payload[], int n) | |
01cf8814 DR |
96 | { |
97 | int fd = sdi->serial->fd; | |
98 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
99 | char *p, *buf; | |
100 | ||
ecad043f UH |
101 | ret = SR_ERR; |
102 | ||
01cf8814 DR |
103 | if (fd < 0) |
104 | goto ret; | |
105 | ||
ecad043f | 106 | if (!(buf = g_try_malloc(s))) { |
56eb9f95 | 107 | sr_err("Failed to malloc message buffer."); |
ecad043f | 108 | ret = SR_ERR_MALLOC; |
01cf8814 | 109 | goto ret; |
ecad043f | 110 | } |
01cf8814 DR |
111 | |
112 | p = buf; | |
113 | memcpy(p, mso_head, sizeof(mso_head)); | |
114 | p += sizeof(mso_head); | |
115 | ||
116 | for (i = 0; i < n; i++) { | |
117 | *(uint16_t *) p = htons(payload[i]); | |
118 | p += 2; | |
119 | } | |
120 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
121 | ||
122 | w = 0; | |
123 | while (w < s) { | |
2119ab03 | 124 | ret = serial_write(fd, buf + w, s - w); |
01cf8814 | 125 | if (ret < 0) { |
e46b8fb1 | 126 | ret = SR_ERR; |
01cf8814 DR |
127 | goto free; |
128 | } | |
129 | w += ret; | |
130 | } | |
e46b8fb1 | 131 | ret = SR_OK; |
01cf8814 | 132 | free: |
ecad043f | 133 | g_free(buf); |
01cf8814 DR |
134 | ret: |
135 | return ret; | |
136 | } | |
137 | ||
d68e2d1a | 138 | static int mso_reset_adc(struct sr_dev_inst *sdi) |
01cf8814 | 139 | { |
ea9cfed7 | 140 | struct context *ctx = sdi->priv; |
01cf8814 DR |
141 | uint16_t ops[2]; |
142 | ||
ea9cfed7 UH |
143 | ops[0] = mso_trans(REG_CTL1, (ctx->ctlbase1 | BIT_CTL1_RESETADC)); |
144 | ops[1] = mso_trans(REG_CTL1, ctx->ctlbase1); | |
145 | ctx->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
01cf8814 | 146 | |
56eb9f95 | 147 | sr_dbg("Requesting ADC reset."); |
01cf8814 DR |
148 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
149 | } | |
150 | ||
d68e2d1a | 151 | static int mso_reset_fsm(struct sr_dev_inst *sdi) |
01cf8814 | 152 | { |
ea9cfed7 | 153 | struct context *ctx = sdi->priv; |
01cf8814 DR |
154 | uint16_t ops[1]; |
155 | ||
ea9cfed7 UH |
156 | ctx->ctlbase1 |= BIT_CTL1_RESETFSM; |
157 | ops[0] = mso_trans(REG_CTL1, ctx->ctlbase1); | |
01cf8814 | 158 | |
56eb9f95 | 159 | sr_dbg("Requesting ADC reset."); |
01cf8814 DR |
160 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
161 | } | |
162 | ||
d68e2d1a | 163 | static int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
01cf8814 | 164 | { |
ea9cfed7 | 165 | struct context *ctx = sdi->priv; |
01cf8814 DR |
166 | uint16_t ops[1]; |
167 | ||
ea9cfed7 | 168 | ctx->ctlbase1 &= ~BIT_CTL1_LED; |
01cf8814 | 169 | if (state) |
ea9cfed7 UH |
170 | ctx->ctlbase1 |= BIT_CTL1_LED; |
171 | ops[0] = mso_trans(REG_CTL1, ctx->ctlbase1); | |
01cf8814 | 172 | |
56eb9f95 | 173 | sr_dbg("Requesting LED toggle."); |
01cf8814 DR |
174 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
175 | } | |
176 | ||
d68e2d1a | 177 | static int mso_check_trigger(struct sr_dev_inst *sdi, uint8_t *info) |
01cf8814 DR |
178 | { |
179 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
180 | char buf[1]; | |
181 | int ret; | |
182 | ||
56eb9f95 | 183 | sr_dbg("Requesting trigger state."); |
01cf8814 | 184 | ret = mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
e46b8fb1 | 185 | if (info == NULL || ret != SR_OK) |
01cf8814 DR |
186 | return ret; |
187 | ||
188 | buf[0] = 0; | |
2119ab03 | 189 | if (serial_read(sdi->serial->fd, buf, 1) != 1) /* FIXME: Need timeout */ |
e46b8fb1 | 190 | ret = SR_ERR; |
01cf8814 DR |
191 | *info = buf[0]; |
192 | ||
56eb9f95 | 193 | sr_dbg("Trigger state is: 0x%x.", *info); |
01cf8814 DR |
194 | return ret; |
195 | } | |
196 | ||
d68e2d1a | 197 | static int mso_read_buffer(struct sr_dev_inst *sdi) |
01cf8814 DR |
198 | { |
199 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
200 | ||
56eb9f95 | 201 | sr_dbg("Requesting buffer dump."); |
01cf8814 DR |
202 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
203 | } | |
204 | ||
d68e2d1a | 205 | static int mso_arm(struct sr_dev_inst *sdi) |
01cf8814 | 206 | { |
ea9cfed7 | 207 | struct context *ctx = sdi->priv; |
01cf8814 | 208 | uint16_t ops[] = { |
ea9cfed7 UH |
209 | mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_RESETFSM), |
210 | mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_ARM), | |
211 | mso_trans(REG_CTL1, ctx->ctlbase1), | |
01cf8814 DR |
212 | }; |
213 | ||
56eb9f95 | 214 | sr_dbg("Requesting trigger arm."); |
01cf8814 DR |
215 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
216 | } | |
217 | ||
d68e2d1a | 218 | static int mso_force_capture(struct sr_dev_inst *sdi) |
01cf8814 | 219 | { |
ea9cfed7 | 220 | struct context *ctx = sdi->priv; |
01cf8814 | 221 | uint16_t ops[] = { |
ea9cfed7 UH |
222 | mso_trans(REG_CTL1, ctx->ctlbase1 | 8), |
223 | mso_trans(REG_CTL1, ctx->ctlbase1), | |
01cf8814 DR |
224 | }; |
225 | ||
56eb9f95 | 226 | sr_dbg("Requesting forced capture."); |
01cf8814 DR |
227 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
228 | } | |
229 | ||
d68e2d1a | 230 | static int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val) |
01cf8814 | 231 | { |
ea9cfed7 | 232 | struct context *ctx = sdi->priv; |
01cf8814 DR |
233 | uint16_t ops[] = { |
234 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
235 | mso_trans(REG_DAC2, val & 0xff), | |
ea9cfed7 | 236 | mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_RESETADC), |
01cf8814 DR |
237 | }; |
238 | ||
56eb9f95 | 239 | sr_dbg("Setting dac word to 0x%x.", val); |
01cf8814 DR |
240 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
241 | } | |
242 | ||
d68e2d1a | 243 | static int mso_clkrate_out(struct sr_dev_inst *sdi, uint16_t val) |
01cf8814 DR |
244 | { |
245 | uint16_t ops[] = { | |
246 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
247 | mso_trans(REG_CLKRATE2, val & 0xff), | |
248 | }; | |
249 | ||
56eb9f95 | 250 | sr_dbg("Setting clkrate word to 0x%x.", val); |
01cf8814 DR |
251 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); |
252 | } | |
253 | ||
d68e2d1a | 254 | static int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate) |
01cf8814 | 255 | { |
ea9cfed7 | 256 | struct context *ctx = sdi->priv; |
01cf8814 | 257 | unsigned int i; |
e46b8fb1 | 258 | int ret = SR_ERR; |
01cf8814 DR |
259 | |
260 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
261 | if (rate_map[i].rate == rate) { | |
ea9cfed7 | 262 | ctx->ctlbase2 = rate_map[i].slowmode; |
01cf8814 | 263 | ret = mso_clkrate_out(sdi, rate_map[i].val); |
e46b8fb1 | 264 | if (ret == SR_OK) |
ea9cfed7 | 265 | ctx->cur_rate = rate; |
01cf8814 DR |
266 | return ret; |
267 | } | |
268 | } | |
269 | return ret; | |
270 | } | |
271 | ||
ea9cfed7 | 272 | static inline uint16_t mso_calc_raw_from_mv(struct context *ctx) |
01cf8814 DR |
273 | { |
274 | return (uint16_t) (0x200 - | |
ea9cfed7 UH |
275 | ((ctx->dso_trigger_voltage / ctx->dso_probe_attn) / |
276 | ctx->vbit)); | |
01cf8814 DR |
277 | } |
278 | ||
d68e2d1a | 279 | static int mso_configure_trigger(struct sr_dev_inst *sdi) |
01cf8814 | 280 | { |
ea9cfed7 | 281 | struct context *ctx = sdi->priv; |
01cf8814 | 282 | uint16_t ops[16]; |
ea9cfed7 | 283 | uint16_t dso_trigger = mso_calc_raw_from_mv(ctx); |
01cf8814 DR |
284 | |
285 | dso_trigger &= 0x3ff; | |
ea9cfed7 UH |
286 | if ((!ctx->trigger_slope && ctx->trigger_chan == 1) || |
287 | (ctx->trigger_slope && | |
288 | (ctx->trigger_chan == 0 || | |
289 | ctx->trigger_chan == 2 || | |
290 | ctx->trigger_chan == 3))) | |
01cf8814 DR |
291 | dso_trigger |= 0x400; |
292 | ||
ea9cfed7 | 293 | switch (ctx->trigger_chan) { |
01cf8814 DR |
294 | case 1: |
295 | dso_trigger |= 0xe000; | |
296 | case 2: | |
297 | dso_trigger |= 0x4000; | |
298 | break; | |
299 | case 3: | |
300 | dso_trigger |= 0x2000; | |
301 | break; | |
302 | case 4: | |
303 | dso_trigger |= 0xa000; | |
304 | break; | |
305 | case 5: | |
306 | dso_trigger |= 0x8000; | |
307 | break; | |
308 | default: | |
309 | case 0: | |
310 | break; | |
311 | } | |
312 | ||
ea9cfed7 | 313 | switch (ctx->trigger_outsrc) { |
01cf8814 DR |
314 | case 1: |
315 | dso_trigger |= 0x800; | |
316 | break; | |
317 | case 2: | |
318 | dso_trigger |= 0x1000; | |
319 | break; | |
320 | case 3: | |
321 | dso_trigger |= 0x1800; | |
322 | break; | |
323 | ||
324 | } | |
325 | ||
ea9cfed7 UH |
326 | ops[0] = mso_trans(5, ctx->la_trigger); |
327 | ops[1] = mso_trans(6, ctx->la_trigger_mask); | |
01cf8814 DR |
328 | ops[2] = mso_trans(3, dso_trigger & 0xff); |
329 | ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff); | |
330 | ops[4] = mso_trans(11, | |
ea9cfed7 | 331 | ctx->dso_trigger_width / SR_HZ_TO_NS(ctx->cur_rate)); |
01cf8814 | 332 | |
a2936073 | 333 | /* Select the SPI/I2C trigger config bank */ |
ea9cfed7 | 334 | ops[5] = mso_trans(REG_CTL2, (ctx->ctlbase2 | BITS_CTL2_BANK(2))); |
a2936073 | 335 | /* Configure the SPI/I2C protocol trigger */ |
ea9cfed7 UH |
336 | ops[6] = mso_trans(REG_PT_WORD(0), ctx->protocol_trigger.word[0]); |
337 | ops[7] = mso_trans(REG_PT_WORD(1), ctx->protocol_trigger.word[1]); | |
338 | ops[8] = mso_trans(REG_PT_WORD(2), ctx->protocol_trigger.word[2]); | |
339 | ops[9] = mso_trans(REG_PT_WORD(3), ctx->protocol_trigger.word[3]); | |
340 | ops[10] = mso_trans(REG_PT_MASK(0), ctx->protocol_trigger.mask[0]); | |
341 | ops[11] = mso_trans(REG_PT_MASK(1), ctx->protocol_trigger.mask[1]); | |
342 | ops[12] = mso_trans(REG_PT_MASK(2), ctx->protocol_trigger.mask[2]); | |
343 | ops[13] = mso_trans(REG_PT_MASK(3), ctx->protocol_trigger.mask[3]); | |
344 | ops[14] = mso_trans(REG_PT_SPIMODE, ctx->protocol_trigger.spimode); | |
a2936073 | 345 | /* Select the default config bank */ |
ea9cfed7 | 346 | ops[15] = mso_trans(REG_CTL2, ctx->ctlbase2); |
01cf8814 DR |
347 | |
348 | return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops)); | |
349 | } | |
350 | ||
d68e2d1a | 351 | static int mso_configure_threshold_level(struct sr_dev_inst *sdi) |
01cf8814 | 352 | { |
ea9cfed7 | 353 | struct context *ctx = sdi->priv; |
01cf8814 | 354 | |
ea9cfed7 | 355 | return mso_dac_out(sdi, la_threshold_map[ctx->la_threshold]); |
01cf8814 DR |
356 | } |
357 | ||
358 | static int mso_parse_serial(const char *iSerial, const char *iProduct, | |
ea9cfed7 | 359 | struct context *ctx) |
01cf8814 DR |
360 | { |
361 | unsigned int u1, u2, u3, u4, u5, u6; | |
362 | ||
363 | iProduct = iProduct; | |
364 | /* FIXME: This code is in the original app, but I think its | |
365 | * used only for the GUI */ | |
366 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
ea9cfed7 | 367 | ctx->num_sample_rates = 0x16; |
01cf8814 | 368 | else |
ea9cfed7 | 369 | ctx->num_sample_rates = 0x10; */ |
01cf8814 DR |
370 | |
371 | /* parse iSerial */ | |
372 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
373 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) | |
e46b8fb1 | 374 | return SR_ERR; |
ea9cfed7 UH |
375 | ctx->hwmodel = u4; |
376 | ctx->hwrev = u5; | |
377 | ctx->serial = u6; | |
378 | ctx->vbit = u1 / 10000; | |
379 | if (ctx->vbit == 0) | |
380 | ctx->vbit = 4.19195; | |
381 | ctx->dac_offset = u2; | |
382 | if (ctx->dac_offset == 0) | |
383 | ctx->dac_offset = 0x1ff; | |
384 | ctx->offset_range = u3; | |
385 | if (ctx->offset_range == 0) | |
386 | ctx->offset_range = 0x17d; | |
01cf8814 DR |
387 | |
388 | /* | |
389 | * FIXME: There is more code on the original software to handle | |
390 | * bigger iSerial strings, but as I can't test on my device | |
391 | * I will not implement it yet | |
392 | */ | |
393 | ||
e46b8fb1 | 394 | return SR_OK; |
01cf8814 DR |
395 | } |
396 | ||
34f06b90 | 397 | static int hw_init(struct sr_context *sr_ctx) |
61136ea6 | 398 | { |
61136ea6 BV |
399 | /* Nothing to do. */ |
400 | ||
401 | return SR_OK; | |
402 | } | |
403 | ||
404 | static int hw_scan(void) | |
01cf8814 | 405 | { |
d68e2d1a | 406 | struct sr_dev_inst *sdi; |
01cf8814 DR |
407 | int devcnt = 0; |
408 | struct udev *udev; | |
409 | struct udev_enumerate *enumerate; | |
bb7ef793 | 410 | struct udev_list_entry *devs, *dev_list_entry; |
ea9cfed7 | 411 | struct context *ctx; |
01cf8814 | 412 | |
01cf8814 DR |
413 | /* It's easier to map usb<->serial using udev */ |
414 | /* | |
415 | * FIXME: On windows we can get the same information from the | |
416 | * registry, add an #ifdef here later | |
417 | */ | |
418 | udev = udev_new(); | |
419 | if (!udev) { | |
56eb9f95 | 420 | sr_err("Failed to initialize udev."); |
01cf8814 DR |
421 | goto ret; |
422 | } | |
423 | enumerate = udev_enumerate_new(udev); | |
424 | udev_enumerate_add_match_subsystem(enumerate, "usb-serial"); | |
425 | udev_enumerate_scan_devices(enumerate); | |
bb7ef793 UH |
426 | devs = udev_enumerate_get_list_entry(enumerate); |
427 | udev_list_entry_foreach(dev_list_entry, devs) { | |
01cf8814 DR |
428 | const char *syspath, *sysname, *idVendor, *idProduct, |
429 | *iSerial, *iProduct; | |
430 | char path[32], manufacturer[32], product[32], hwrev[32]; | |
431 | struct udev_device *dev, *parent; | |
432 | size_t s; | |
433 | ||
434 | syspath = udev_list_entry_get_name(dev_list_entry); | |
435 | dev = udev_device_new_from_syspath(udev, syspath); | |
436 | sysname = udev_device_get_sysname(dev); | |
437 | parent = udev_device_get_parent_with_subsystem_devtype( | |
438 | dev, "usb", "usb_device"); | |
439 | if (!parent) { | |
56eb9f95 | 440 | sr_err("Unable to find parent usb device for %s", |
133a37bf | 441 | sysname); |
01cf8814 DR |
442 | continue; |
443 | } | |
444 | ||
445 | idVendor = udev_device_get_sysattr_value(parent, "idVendor"); | |
446 | idProduct = udev_device_get_sysattr_value(parent, "idProduct"); | |
447 | if (strcmp(USB_VENDOR, idVendor) | |
448 | || strcmp(USB_PRODUCT, idProduct)) | |
449 | continue; | |
450 | ||
451 | iSerial = udev_device_get_sysattr_value(parent, "serial"); | |
452 | iProduct = udev_device_get_sysattr_value(parent, "product"); | |
453 | ||
454 | snprintf(path, sizeof(path), "/dev/%s", sysname); | |
455 | ||
456 | s = strcspn(iProduct, " "); | |
457 | if (s > sizeof(product) || | |
458 | strlen(iProduct) - s > sizeof(manufacturer)) { | |
56eb9f95 | 459 | sr_err("Could not parse iProduct: %s.", iProduct); |
01cf8814 DR |
460 | continue; |
461 | } | |
462 | strncpy(product, iProduct, s); | |
463 | product[s] = 0; | |
464 | strcpy(manufacturer, iProduct + s); | |
01cf8814 | 465 | |
ea9cfed7 | 466 | if (!(ctx = g_try_malloc0(sizeof(struct context)))) { |
56eb9f95 | 467 | sr_err("Context malloc failed."); |
ecad043f UH |
468 | continue; /* TODO: Errors handled correctly? */ |
469 | } | |
01cf8814 | 470 | |
ea9cfed7 | 471 | if (mso_parse_serial(iSerial, iProduct, ctx) != SR_OK) { |
56eb9f95 | 472 | sr_err("Invalid iSerial: %s.", iSerial); |
ea9cfed7 | 473 | goto err_free_ctx; |
01cf8814 | 474 | } |
ea9cfed7 | 475 | sprintf(hwrev, "r%d", ctx->hwrev); |
a2936073 | 476 | |
01cf8814 | 477 | /* hardware initial state */ |
ea9cfed7 | 478 | ctx->ctlbase1 = 0; |
a2936073 RC |
479 | { |
480 | /* Initialize the protocol trigger configuration */ | |
481 | int i; | |
7b48d6e1 | 482 | for (i = 0; i < 4; i++) { |
ea9cfed7 UH |
483 | ctx->protocol_trigger.word[i] = 0; |
484 | ctx->protocol_trigger.mask[i] = 0xff; | |
a2936073 | 485 | } |
ea9cfed7 | 486 | ctx->protocol_trigger.spimode = 0; |
a2936073 | 487 | } |
01cf8814 | 488 | |
d3683c42 | 489 | sdi = sr_dev_inst_new(devcnt, SR_ST_INITIALIZING, |
7b48d6e1 | 490 | manufacturer, product, hwrev); |
01cf8814 | 491 | if (!sdi) { |
56eb9f95 | 492 | sr_err("Unable to create device instance for %s", |
133a37bf | 493 | sysname); |
ea9cfed7 | 494 | goto err_free_ctx; |
01cf8814 DR |
495 | } |
496 | ||
497 | /* save a pointer to our private instance data */ | |
ea9cfed7 | 498 | sdi->priv = ctx; |
01cf8814 | 499 | |
d3683c42 | 500 | sdi->serial = sr_serial_dev_inst_new(path, -1); |
01cf8814 | 501 | if (!sdi->serial) |
d68e2d1a | 502 | goto err_dev_inst_free; |
01cf8814 | 503 | |
d68e2d1a | 504 | dev_insts = g_slist_append(dev_insts, sdi); |
01cf8814 DR |
505 | devcnt++; |
506 | continue; | |
507 | ||
d68e2d1a | 508 | err_dev_inst_free: |
d3683c42 | 509 | sr_dev_inst_free(sdi); |
ea9cfed7 UH |
510 | err_free_ctx: |
511 | g_free(ctx); | |
01cf8814 DR |
512 | } |
513 | ||
514 | udev_enumerate_unref(enumerate); | |
515 | udev_unref(udev); | |
516 | ||
517 | ret: | |
518 | return devcnt; | |
519 | } | |
520 | ||
57ab7d9f | 521 | static int hw_cleanup(void) |
01cf8814 DR |
522 | { |
523 | GSList *l; | |
d68e2d1a | 524 | struct sr_dev_inst *sdi; |
341ce415 | 525 | int ret; |
01cf8814 | 526 | |
341ce415 | 527 | ret = SR_OK; |
01cf8814 | 528 | /* Properly close all devices. */ |
d68e2d1a | 529 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
530 | if (!(sdi = l->data)) { |
531 | /* Log error, but continue cleaning up the rest. */ | |
56eb9f95 | 532 | sr_err("%s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
533 | ret = SR_ERR_BUG; |
534 | continue; | |
535 | } | |
01cf8814 DR |
536 | if (sdi->serial->fd != -1) |
537 | serial_close(sdi->serial->fd); | |
d3683c42 | 538 | sr_dev_inst_free(sdi); |
01cf8814 | 539 | } |
d68e2d1a UH |
540 | g_slist_free(dev_insts); |
541 | dev_insts = NULL; | |
57ab7d9f | 542 | |
341ce415 | 543 | return ret; |
01cf8814 DR |
544 | } |
545 | ||
e7eb703f | 546 | static int hw_dev_open(int dev_index) |
01cf8814 | 547 | { |
d68e2d1a | 548 | struct sr_dev_inst *sdi; |
ea9cfed7 | 549 | struct context *ctx; |
e46b8fb1 | 550 | int ret = SR_ERR; |
01cf8814 | 551 | |
bb7ef793 | 552 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
01cf8814 DR |
553 | return ret; |
554 | ||
ea9cfed7 | 555 | ctx = sdi->priv; |
a54dd31e | 556 | sdi->serial->fd = serial_open(sdi->serial->port, SERIAL_RDWR); |
01cf8814 DR |
557 | if (sdi->serial->fd == -1) |
558 | return ret; | |
559 | ||
560 | ret = serial_set_params(sdi->serial->fd, 460800, 8, 0, 1, 2); | |
e46b8fb1 | 561 | if (ret != SR_OK) |
01cf8814 DR |
562 | return ret; |
563 | ||
5a2326a7 | 564 | sdi->status = SR_ST_ACTIVE; |
01cf8814 DR |
565 | |
566 | /* FIXME: discard serial buffer */ | |
567 | ||
ea9cfed7 | 568 | mso_check_trigger(sdi, &ctx->trigger_state); |
56eb9f95 | 569 | sr_dbg("Trigger state: 0x%x.", ctx->trigger_state); |
01cf8814 DR |
570 | |
571 | ret = mso_reset_adc(sdi); | |
e46b8fb1 | 572 | if (ret != SR_OK) |
01cf8814 DR |
573 | return ret; |
574 | ||
ea9cfed7 | 575 | mso_check_trigger(sdi, &ctx->trigger_state); |
56eb9f95 | 576 | sr_dbg("Trigger state: 0x%x.", ctx->trigger_state); |
01cf8814 DR |
577 | |
578 | // ret = mso_reset_fsm(sdi); | |
e46b8fb1 | 579 | // if (ret != SR_OK) |
01cf8814 DR |
580 | // return ret; |
581 | ||
e46b8fb1 UH |
582 | // return SR_ERR; |
583 | return SR_OK; | |
01cf8814 DR |
584 | } |
585 | ||
e7eb703f | 586 | static int hw_dev_close(int dev_index) |
01cf8814 | 587 | { |
d68e2d1a | 588 | struct sr_dev_inst *sdi; |
01cf8814 | 589 | |
bb7ef793 | 590 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
56eb9f95 | 591 | sr_err("%s: sdi was NULL", __func__); |
0abee507 | 592 | return SR_ERR_BUG; |
697785d1 | 593 | } |
01cf8814 | 594 | |
697785d1 | 595 | /* TODO */ |
01cf8814 DR |
596 | if (sdi->serial->fd != -1) { |
597 | serial_close(sdi->serial->fd); | |
598 | sdi->serial->fd = -1; | |
5a2326a7 | 599 | sdi->status = SR_ST_INACTIVE; |
01cf8814 | 600 | } |
697785d1 UH |
601 | |
602 | return SR_OK; | |
01cf8814 DR |
603 | } |
604 | ||
b7f578be | 605 | static const void *hw_dev_info_get(int dev_index, int dev_info_id) |
01cf8814 | 606 | { |
d68e2d1a | 607 | struct sr_dev_inst *sdi; |
ea9cfed7 | 608 | struct context *ctx; |
b7f578be | 609 | const void *info = NULL; |
01cf8814 | 610 | |
bb7ef793 | 611 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
01cf8814 | 612 | return NULL; |
ea9cfed7 | 613 | ctx = sdi->priv; |
01cf8814 | 614 | |
bb7ef793 | 615 | switch (dev_info_id) { |
1d9a8a5f | 616 | case SR_DI_INST: |
01cf8814 DR |
617 | info = sdi; |
618 | break; | |
5a2326a7 | 619 | case SR_DI_NUM_PROBES: /* FIXME: How to report analog probe? */ |
464d12c7 KS |
620 | info = GINT_TO_POINTER(NUM_PROBES); |
621 | break; | |
622 | case SR_DI_PROBE_NAMES: | |
623 | info = probe_names; | |
01cf8814 | 624 | break; |
5a2326a7 | 625 | case SR_DI_SAMPLERATES: |
01cf8814 DR |
626 | info = &samplerates; |
627 | break; | |
5a2326a7 | 628 | case SR_DI_TRIGGER_TYPES: |
01cf8814 DR |
629 | info = "01"; /* FIXME */ |
630 | break; | |
5a2326a7 | 631 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 632 | info = &ctx->cur_rate; |
01cf8814 DR |
633 | break; |
634 | } | |
635 | return info; | |
636 | } | |
637 | ||
e7eb703f | 638 | static int hw_dev_status_get(int dev_index) |
01cf8814 | 639 | { |
d68e2d1a | 640 | struct sr_dev_inst *sdi; |
01cf8814 | 641 | |
bb7ef793 | 642 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
5a2326a7 | 643 | return SR_ST_NOT_FOUND; |
01cf8814 DR |
644 | |
645 | return sdi->status; | |
646 | } | |
647 | ||
915f7cc8 | 648 | static const int *hw_hwcap_get_all(void) |
01cf8814 | 649 | { |
ffedd0bf | 650 | return hwcaps; |
01cf8814 DR |
651 | } |
652 | ||
1b79df2f | 653 | static int hw_dev_config_set(int dev_index, int hwcap, const void *value) |
01cf8814 | 654 | { |
d68e2d1a | 655 | struct sr_dev_inst *sdi; |
01cf8814 | 656 | |
bb7ef793 | 657 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 658 | return SR_ERR; |
01cf8814 | 659 | |
ffedd0bf | 660 | switch (hwcap) { |
5a2326a7 | 661 | case SR_HWCAP_SAMPLERATE: |
1b79df2f | 662 | return mso_configure_rate(sdi, *(const uint64_t *) value); |
5a2326a7 UH |
663 | case SR_HWCAP_PROBECONFIG: |
664 | case SR_HWCAP_LIMIT_SAMPLES: | |
01cf8814 | 665 | default: |
e46b8fb1 | 666 | return SR_OK; /* FIXME */ |
01cf8814 | 667 | } |
01cf8814 DR |
668 | } |
669 | ||
670 | #define MSO_TRIGGER_UNKNOWN '!' | |
671 | #define MSO_TRIGGER_UNKNOWN1 '1' | |
672 | #define MSO_TRIGGER_UNKNOWN2 '2' | |
673 | #define MSO_TRIGGER_UNKNOWN3 '3' | |
674 | #define MSO_TRIGGER_WAIT '4' | |
675 | #define MSO_TRIGGER_FIRED '5' | |
676 | #define MSO_TRIGGER_DATAREADY '6' | |
677 | ||
678 | /* FIXME: Pass errors? */ | |
1f9813eb | 679 | static int receive_data(int fd, int revents, void *cb_data) |
01cf8814 | 680 | { |
1f9813eb | 681 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 682 | struct context *ctx = sdi->priv; |
b9c735a2 | 683 | struct sr_datafeed_packet packet; |
e42ef08d | 684 | struct sr_datafeed_logic logic; |
01cf8814 DR |
685 | uint8_t in[1024], logic_out[1024]; |
686 | double analog_out[1024]; | |
687 | size_t i, s; | |
688 | ||
4101f961 | 689 | (void)revents; |
01cf8814 | 690 | |
2119ab03 | 691 | s = serial_read(fd, in, sizeof(in)); |
01cf8814 DR |
692 | if (s <= 0) |
693 | return FALSE; | |
694 | ||
695 | /* No samples */ | |
ea9cfed7 UH |
696 | if (ctx->trigger_state != MSO_TRIGGER_DATAREADY) { |
697 | ctx->trigger_state = in[0]; | |
698 | if (ctx->trigger_state == MSO_TRIGGER_DATAREADY) { | |
01cf8814 | 699 | mso_read_buffer(sdi); |
ea9cfed7 | 700 | ctx->buffer_n = 0; |
01cf8814 DR |
701 | } else { |
702 | mso_check_trigger(sdi, NULL); | |
703 | } | |
704 | return FALSE; | |
705 | } | |
706 | ||
707 | /* the hardware always dumps 1024 samples, 24bits each */ | |
ea9cfed7 UH |
708 | if (ctx->buffer_n < 3072) { |
709 | memcpy(ctx->buffer + ctx->buffer_n, in, s); | |
710 | ctx->buffer_n += s; | |
01cf8814 | 711 | } |
ea9cfed7 | 712 | if (ctx->buffer_n < 3072) |
01cf8814 DR |
713 | return FALSE; |
714 | ||
715 | /* do the conversion */ | |
716 | for (i = 0; i < 1024; i++) { | |
717 | /* FIXME: Need to do conversion to mV */ | |
ea9cfed7 UH |
718 | analog_out[i] = (ctx->buffer[i * 3] & 0x3f) | |
719 | ((ctx->buffer[i * 3 + 1] & 0xf) << 6); | |
720 | logic_out[i] = ((ctx->buffer[i * 3 + 1] & 0x30) >> 4) | | |
721 | ((ctx->buffer[i * 3 + 2] & 0x3f) << 2); | |
01cf8814 DR |
722 | } |
723 | ||
5a2326a7 | 724 | packet.type = SR_DF_LOGIC; |
42eb54fb | 725 | packet.payload = &logic; |
e42ef08d RC |
726 | logic.length = 1024; |
727 | logic.unitsize = 1; | |
728 | logic.data = logic_out; | |
3cd3a20b | 729 | sr_session_send(ctx->session_dev_id, &packet); |
01cf8814 | 730 | |
42eb54fb UH |
731 | // Dont bother fixing this yet, keep it "old style" |
732 | /* | |
5a2326a7 | 733 | packet.type = SR_DF_ANALOG; |
01cf8814 DR |
734 | packet.length = 1024; |
735 | packet.unitsize = sizeof(double); | |
736 | packet.payload = analog_out; | |
3cd3a20b | 737 | sr_session_send(ctx->session_dev_id, &packet); |
42eb54fb | 738 | */ |
01cf8814 | 739 | |
5a2326a7 | 740 | packet.type = SR_DF_END; |
3cd3a20b | 741 | sr_session_send(ctx->session_dev_id, &packet); |
01cf8814 DR |
742 | |
743 | return TRUE; | |
744 | } | |
745 | ||
3cd3a20b | 746 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) |
01cf8814 | 747 | { |
d68e2d1a | 748 | struct sr_dev_inst *sdi; |
ea9cfed7 | 749 | struct context *ctx; |
b9c735a2 UH |
750 | struct sr_datafeed_packet packet; |
751 | struct sr_datafeed_header header; | |
e46b8fb1 | 752 | int ret = SR_ERR; |
01cf8814 | 753 | |
bb7ef793 | 754 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
01cf8814 | 755 | return ret; |
ea9cfed7 | 756 | ctx = sdi->priv; |
01cf8814 DR |
757 | |
758 | /* FIXME: No need to do full reconfigure every time */ | |
759 | // ret = mso_reset_fsm(sdi); | |
e46b8fb1 | 760 | // if (ret != SR_OK) |
01cf8814 DR |
761 | // return ret; |
762 | ||
763 | /* FIXME: ACDC Mode */ | |
ea9cfed7 UH |
764 | ctx->ctlbase1 &= 0x7f; |
765 | // ctx->ctlbase1 |= ctx->acdcmode; | |
01cf8814 | 766 | |
ea9cfed7 | 767 | ret = mso_configure_rate(sdi, ctx->cur_rate); |
e46b8fb1 | 768 | if (ret != SR_OK) |
01cf8814 DR |
769 | return ret; |
770 | ||
771 | /* set dac offset */ | |
ea9cfed7 | 772 | ret = mso_dac_out(sdi, ctx->dac_offset); |
e46b8fb1 | 773 | if (ret != SR_OK) |
01cf8814 DR |
774 | return ret; |
775 | ||
776 | ret = mso_configure_threshold_level(sdi); | |
e46b8fb1 | 777 | if (ret != SR_OK) |
01cf8814 DR |
778 | return ret; |
779 | ||
780 | ret = mso_configure_trigger(sdi); | |
e46b8fb1 | 781 | if (ret != SR_OK) |
01cf8814 DR |
782 | return ret; |
783 | ||
784 | /* FIXME: trigger_position */ | |
785 | ||
786 | ||
787 | /* END of config hardware part */ | |
788 | ||
789 | /* with trigger */ | |
790 | ret = mso_arm(sdi); | |
e46b8fb1 | 791 | if (ret != SR_OK) |
01cf8814 DR |
792 | return ret; |
793 | ||
794 | /* without trigger */ | |
795 | // ret = mso_force_capture(sdi); | |
e46b8fb1 | 796 | // if (ret != SR_OK) |
01cf8814 DR |
797 | // return ret; |
798 | ||
ea9cfed7 | 799 | mso_check_trigger(sdi, &ctx->trigger_state); |
01cf8814 | 800 | ret = mso_check_trigger(sdi, NULL); |
e46b8fb1 | 801 | if (ret != SR_OK) |
01cf8814 DR |
802 | return ret; |
803 | ||
3cd3a20b | 804 | ctx->session_dev_id = cb_data; |
6f1be0a2 | 805 | sr_source_add(sdi->serial->fd, G_IO_IN, -1, receive_data, sdi); |
01cf8814 | 806 | |
5a2326a7 | 807 | packet.type = SR_DF_HEADER; |
01cf8814 DR |
808 | packet.payload = (unsigned char *) &header; |
809 | header.feed_version = 1; | |
810 | gettimeofday(&header.starttime, NULL); | |
ea9cfed7 | 811 | header.samplerate = ctx->cur_rate; |
5c64390e | 812 | // header.num_analog_probes = 1; |
01cf8814 | 813 | header.num_logic_probes = 8; |
3cd3a20b | 814 | sr_session_send(ctx->session_dev_id, &packet); |
01cf8814 DR |
815 | |
816 | return ret; | |
817 | } | |
818 | ||
3cd3a20b UH |
819 | /* TODO: This stops acquisition on ALL devices, ignoring dev_index. */ |
820 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) | |
01cf8814 | 821 | { |
b9c735a2 | 822 | struct sr_datafeed_packet packet; |
01cf8814 | 823 | |
3cd3a20b | 824 | (void)dev_index; |
01cf8814 | 825 | |
5a2326a7 | 826 | packet.type = SR_DF_END; |
3cd3a20b | 827 | sr_session_send(cb_data, &packet); |
3010f21c UH |
828 | |
829 | return SR_OK; | |
01cf8814 DR |
830 | } |
831 | ||
c09f0b57 | 832 | SR_PRIV struct sr_dev_driver link_mso19_driver_info = { |
01cf8814 | 833 | .name = "link-mso19", |
9f8274a5 | 834 | .longname = "Link Instruments MSO-19", |
01cf8814 DR |
835 | .api_version = 1, |
836 | .init = hw_init, | |
837 | .cleanup = hw_cleanup, | |
61136ea6 | 838 | .scan = hw_scan, |
e7eb703f UH |
839 | .dev_open = hw_dev_open, |
840 | .dev_close = hw_dev_close, | |
5097b0d0 | 841 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 842 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 843 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 844 | .dev_config_set = hw_dev_config_set, |
69040b7c UH |
845 | .dev_acquisition_start = hw_dev_acquisition_start, |
846 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
01cf8814 | 847 | }; |