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sr: fx2lafw: Consistent #include guard naming.
[libsigrok.git] / hardware / link-mso19 / link-mso19.c
CommitLineData
01cf8814
DR
1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
a2936073 5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
01cf8814
DR
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
8a839354
UH
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
01cf8814
DR
19 */
20
21#include <stdio.h>
22#include <stdlib.h>
23#include <string.h>
24#include <unistd.h>
25#include <fcntl.h>
26#include <sys/time.h>
27#include <inttypes.h>
28#include <glib.h>
29#include <libudev.h>
01cf8814 30#include <arpa/inet.h>
b7f09cf8
UH
31#include "sigrok.h"
32#include "sigrok-internal.h"
01cf8814
DR
33#include "link-mso19.h"
34
35#define USB_VENDOR "3195"
36#define USB_PRODUCT "f190"
37
464d12c7
KS
38#define NUM_PROBES 8
39
ffedd0bf 40static int hwcaps[] = {
5a2326a7
UH
41 SR_HWCAP_LOGIC_ANALYZER,
42// SR_HWCAP_OSCILLOSCOPE,
43// SR_HWCAP_PAT_GENERATOR,
01cf8814 44
5a2326a7
UH
45 SR_HWCAP_SAMPLERATE,
46// SR_HWCAP_CAPTURE_RATIO,
47 SR_HWCAP_LIMIT_SAMPLES,
01cf8814
DR
48 0,
49};
50
464d12c7
KS
51static const char *probe_names[NUM_PROBES + 1] = {
52 "0",
53 "1",
54 "2",
55 "3",
56 "4",
57 "5",
58 "6",
59 "7",
60 NULL,
61};
62
01cf8814 63static uint64_t supported_samplerates[] = {
c9140419
UH
64 SR_HZ(100),
65 SR_HZ(200),
66 SR_HZ(500),
59df0c77
UH
67 SR_KHZ(1),
68 SR_KHZ(2),
69 SR_KHZ(5),
70 SR_KHZ(10),
71 SR_KHZ(20),
72 SR_KHZ(50),
73 SR_KHZ(100),
74 SR_KHZ(200),
75 SR_KHZ(500),
76 SR_MHZ(1),
77 SR_MHZ(2),
78 SR_MHZ(5),
79 SR_MHZ(10),
80 SR_MHZ(20),
81 SR_MHZ(50),
82 SR_MHZ(100),
83 SR_MHZ(200),
84 0,
01cf8814
DR
85};
86
60679b18 87static struct sr_samplerates samplerates = {
c9140419 88 SR_HZ(100),
59df0c77 89 SR_MHZ(200),
c9140419 90 SR_HZ(0),
59df0c77 91 supported_samplerates,
01cf8814
DR
92};
93
d68e2d1a 94static GSList *dev_insts = NULL;
01cf8814 95
d68e2d1a
UH
96static int mso_send_control_message(struct sr_dev_inst *sdi,
97 uint16_t payload[], int n)
01cf8814
DR
98{
99 int fd = sdi->serial->fd;
100 int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
101 char *p, *buf;
102
ecad043f
UH
103 ret = SR_ERR;
104
01cf8814
DR
105 if (fd < 0)
106 goto ret;
107
ecad043f
UH
108 if (!(buf = g_try_malloc(s))) {
109 sr_err("mso19: %s: buf malloc failed", __func__);
110 ret = SR_ERR_MALLOC;
01cf8814 111 goto ret;
ecad043f 112 }
01cf8814
DR
113
114 p = buf;
115 memcpy(p, mso_head, sizeof(mso_head));
116 p += sizeof(mso_head);
117
118 for (i = 0; i < n; i++) {
119 *(uint16_t *) p = htons(payload[i]);
120 p += 2;
121 }
122 memcpy(p, mso_foot, sizeof(mso_foot));
123
124 w = 0;
125 while (w < s) {
2119ab03 126 ret = serial_write(fd, buf + w, s - w);
01cf8814 127 if (ret < 0) {
e46b8fb1 128 ret = SR_ERR;
01cf8814
DR
129 goto free;
130 }
131 w += ret;
132 }
e46b8fb1 133 ret = SR_OK;
01cf8814 134free:
ecad043f 135 g_free(buf);
01cf8814
DR
136ret:
137 return ret;
138}
139
d68e2d1a 140static int mso_reset_adc(struct sr_dev_inst *sdi)
01cf8814 141{
ea9cfed7 142 struct context *ctx = sdi->priv;
01cf8814
DR
143 uint16_t ops[2];
144
ea9cfed7
UH
145 ops[0] = mso_trans(REG_CTL1, (ctx->ctlbase1 | BIT_CTL1_RESETADC));
146 ops[1] = mso_trans(REG_CTL1, ctx->ctlbase1);
147 ctx->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
01cf8814 148
7b48d6e1 149 sr_dbg("mso19: Requesting ADC reset");
01cf8814
DR
150 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
151}
152
d68e2d1a 153static int mso_reset_fsm(struct sr_dev_inst *sdi)
01cf8814 154{
ea9cfed7 155 struct context *ctx = sdi->priv;
01cf8814
DR
156 uint16_t ops[1];
157
ea9cfed7
UH
158 ctx->ctlbase1 |= BIT_CTL1_RESETFSM;
159 ops[0] = mso_trans(REG_CTL1, ctx->ctlbase1);
01cf8814 160
7b48d6e1 161 sr_dbg("mso19: Requesting ADC reset");
01cf8814
DR
162 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
163}
164
d68e2d1a 165static int mso_toggle_led(struct sr_dev_inst *sdi, int state)
01cf8814 166{
ea9cfed7 167 struct context *ctx = sdi->priv;
01cf8814
DR
168 uint16_t ops[1];
169
ea9cfed7 170 ctx->ctlbase1 &= ~BIT_CTL1_LED;
01cf8814 171 if (state)
ea9cfed7
UH
172 ctx->ctlbase1 |= BIT_CTL1_LED;
173 ops[0] = mso_trans(REG_CTL1, ctx->ctlbase1);
01cf8814 174
7b48d6e1 175 sr_dbg("mso19: Requesting LED toggle");
01cf8814
DR
176 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
177}
178
d68e2d1a 179static int mso_check_trigger(struct sr_dev_inst *sdi, uint8_t *info)
01cf8814
DR
180{
181 uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
182 char buf[1];
183 int ret;
184
7b48d6e1 185 sr_dbg("mso19: Requesting trigger state");
01cf8814 186 ret = mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
e46b8fb1 187 if (info == NULL || ret != SR_OK)
01cf8814
DR
188 return ret;
189
190 buf[0] = 0;
2119ab03 191 if (serial_read(sdi->serial->fd, buf, 1) != 1) /* FIXME: Need timeout */
e46b8fb1 192 ret = SR_ERR;
01cf8814
DR
193 *info = buf[0];
194
7b48d6e1 195 sr_dbg("mso19: Trigger state is: 0x%x", *info);
01cf8814
DR
196 return ret;
197}
198
d68e2d1a 199static int mso_read_buffer(struct sr_dev_inst *sdi)
01cf8814
DR
200{
201 uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
202
7b48d6e1 203 sr_dbg("mso19: Requesting buffer dump");
01cf8814
DR
204 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
205}
206
d68e2d1a 207static int mso_arm(struct sr_dev_inst *sdi)
01cf8814 208{
ea9cfed7 209 struct context *ctx = sdi->priv;
01cf8814 210 uint16_t ops[] = {
ea9cfed7
UH
211 mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_RESETFSM),
212 mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_ARM),
213 mso_trans(REG_CTL1, ctx->ctlbase1),
01cf8814
DR
214 };
215
7b48d6e1 216 sr_dbg("mso19: Requesting trigger arm");
01cf8814
DR
217 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
218}
219
d68e2d1a 220static int mso_force_capture(struct sr_dev_inst *sdi)
01cf8814 221{
ea9cfed7 222 struct context *ctx = sdi->priv;
01cf8814 223 uint16_t ops[] = {
ea9cfed7
UH
224 mso_trans(REG_CTL1, ctx->ctlbase1 | 8),
225 mso_trans(REG_CTL1, ctx->ctlbase1),
01cf8814
DR
226 };
227
7b48d6e1 228 sr_dbg("mso19: Requesting forced capture");
01cf8814
DR
229 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
230}
231
d68e2d1a 232static int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
01cf8814 233{
ea9cfed7 234 struct context *ctx = sdi->priv;
01cf8814
DR
235 uint16_t ops[] = {
236 mso_trans(REG_DAC1, (val >> 8) & 0xff),
237 mso_trans(REG_DAC2, val & 0xff),
ea9cfed7 238 mso_trans(REG_CTL1, ctx->ctlbase1 | BIT_CTL1_RESETADC),
01cf8814
DR
239 };
240
7b48d6e1 241 sr_dbg("mso19: Setting dac word to 0x%x", val);
01cf8814
DR
242 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
243}
244
d68e2d1a 245static int mso_clkrate_out(struct sr_dev_inst *sdi, uint16_t val)
01cf8814
DR
246{
247 uint16_t ops[] = {
248 mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
249 mso_trans(REG_CLKRATE2, val & 0xff),
250 };
251
7b48d6e1 252 sr_dbg("mso19: Setting clkrate word to 0x%x", val);
01cf8814
DR
253 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
254}
255
d68e2d1a 256static int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
01cf8814 257{
ea9cfed7 258 struct context *ctx = sdi->priv;
01cf8814 259 unsigned int i;
e46b8fb1 260 int ret = SR_ERR;
01cf8814
DR
261
262 for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
263 if (rate_map[i].rate == rate) {
ea9cfed7 264 ctx->ctlbase2 = rate_map[i].slowmode;
01cf8814 265 ret = mso_clkrate_out(sdi, rate_map[i].val);
e46b8fb1 266 if (ret == SR_OK)
ea9cfed7 267 ctx->cur_rate = rate;
01cf8814
DR
268 return ret;
269 }
270 }
271 return ret;
272}
273
ea9cfed7 274static inline uint16_t mso_calc_raw_from_mv(struct context *ctx)
01cf8814
DR
275{
276 return (uint16_t) (0x200 -
ea9cfed7
UH
277 ((ctx->dso_trigger_voltage / ctx->dso_probe_attn) /
278 ctx->vbit));
01cf8814
DR
279}
280
d68e2d1a 281static int mso_configure_trigger(struct sr_dev_inst *sdi)
01cf8814 282{
ea9cfed7 283 struct context *ctx = sdi->priv;
01cf8814 284 uint16_t ops[16];
ea9cfed7 285 uint16_t dso_trigger = mso_calc_raw_from_mv(ctx);
01cf8814
DR
286
287 dso_trigger &= 0x3ff;
ea9cfed7
UH
288 if ((!ctx->trigger_slope && ctx->trigger_chan == 1) ||
289 (ctx->trigger_slope &&
290 (ctx->trigger_chan == 0 ||
291 ctx->trigger_chan == 2 ||
292 ctx->trigger_chan == 3)))
01cf8814
DR
293 dso_trigger |= 0x400;
294
ea9cfed7 295 switch (ctx->trigger_chan) {
01cf8814
DR
296 case 1:
297 dso_trigger |= 0xe000;
298 case 2:
299 dso_trigger |= 0x4000;
300 break;
301 case 3:
302 dso_trigger |= 0x2000;
303 break;
304 case 4:
305 dso_trigger |= 0xa000;
306 break;
307 case 5:
308 dso_trigger |= 0x8000;
309 break;
310 default:
311 case 0:
312 break;
313 }
314
ea9cfed7 315 switch (ctx->trigger_outsrc) {
01cf8814
DR
316 case 1:
317 dso_trigger |= 0x800;
318 break;
319 case 2:
320 dso_trigger |= 0x1000;
321 break;
322 case 3:
323 dso_trigger |= 0x1800;
324 break;
325
326 }
327
ea9cfed7
UH
328 ops[0] = mso_trans(5, ctx->la_trigger);
329 ops[1] = mso_trans(6, ctx->la_trigger_mask);
01cf8814
DR
330 ops[2] = mso_trans(3, dso_trigger & 0xff);
331 ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
332 ops[4] = mso_trans(11,
ea9cfed7 333 ctx->dso_trigger_width / SR_HZ_TO_NS(ctx->cur_rate));
01cf8814 334
a2936073 335 /* Select the SPI/I2C trigger config bank */
ea9cfed7 336 ops[5] = mso_trans(REG_CTL2, (ctx->ctlbase2 | BITS_CTL2_BANK(2)));
a2936073 337 /* Configure the SPI/I2C protocol trigger */
ea9cfed7
UH
338 ops[6] = mso_trans(REG_PT_WORD(0), ctx->protocol_trigger.word[0]);
339 ops[7] = mso_trans(REG_PT_WORD(1), ctx->protocol_trigger.word[1]);
340 ops[8] = mso_trans(REG_PT_WORD(2), ctx->protocol_trigger.word[2]);
341 ops[9] = mso_trans(REG_PT_WORD(3), ctx->protocol_trigger.word[3]);
342 ops[10] = mso_trans(REG_PT_MASK(0), ctx->protocol_trigger.mask[0]);
343 ops[11] = mso_trans(REG_PT_MASK(1), ctx->protocol_trigger.mask[1]);
344 ops[12] = mso_trans(REG_PT_MASK(2), ctx->protocol_trigger.mask[2]);
345 ops[13] = mso_trans(REG_PT_MASK(3), ctx->protocol_trigger.mask[3]);
346 ops[14] = mso_trans(REG_PT_SPIMODE, ctx->protocol_trigger.spimode);
a2936073 347 /* Select the default config bank */
ea9cfed7 348 ops[15] = mso_trans(REG_CTL2, ctx->ctlbase2);
01cf8814
DR
349
350 return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
351}
352
d68e2d1a 353static int mso_configure_threshold_level(struct sr_dev_inst *sdi)
01cf8814 354{
ea9cfed7 355 struct context *ctx = sdi->priv;
01cf8814 356
ea9cfed7 357 return mso_dac_out(sdi, la_threshold_map[ctx->la_threshold]);
01cf8814
DR
358}
359
360static int mso_parse_serial(const char *iSerial, const char *iProduct,
ea9cfed7 361 struct context *ctx)
01cf8814
DR
362{
363 unsigned int u1, u2, u3, u4, u5, u6;
364
365 iProduct = iProduct;
366 /* FIXME: This code is in the original app, but I think its
367 * used only for the GUI */
368/* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
ea9cfed7 369 ctx->num_sample_rates = 0x16;
01cf8814 370 else
ea9cfed7 371 ctx->num_sample_rates = 0x10; */
01cf8814
DR
372
373 /* parse iSerial */
374 if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
375 &u1, &u2, &u3, &u4, &u5, &u6) != 6)
e46b8fb1 376 return SR_ERR;
ea9cfed7
UH
377 ctx->hwmodel = u4;
378 ctx->hwrev = u5;
379 ctx->serial = u6;
380 ctx->vbit = u1 / 10000;
381 if (ctx->vbit == 0)
382 ctx->vbit = 4.19195;
383 ctx->dac_offset = u2;
384 if (ctx->dac_offset == 0)
385 ctx->dac_offset = 0x1ff;
386 ctx->offset_range = u3;
387 if (ctx->offset_range == 0)
388 ctx->offset_range = 0x17d;
01cf8814
DR
389
390 /*
391 * FIXME: There is more code on the original software to handle
392 * bigger iSerial strings, but as I can't test on my device
393 * I will not implement it yet
394 */
395
e46b8fb1 396 return SR_OK;
01cf8814
DR
397}
398
bb7ef793 399static int hw_init(const char *devinfo)
01cf8814 400{
d68e2d1a 401 struct sr_dev_inst *sdi;
01cf8814
DR
402 int devcnt = 0;
403 struct udev *udev;
404 struct udev_enumerate *enumerate;
bb7ef793 405 struct udev_list_entry *devs, *dev_list_entry;
ea9cfed7 406 struct context *ctx;
01cf8814 407
bb7ef793 408 devinfo = devinfo;
01cf8814
DR
409
410 /* It's easier to map usb<->serial using udev */
411 /*
412 * FIXME: On windows we can get the same information from the
413 * registry, add an #ifdef here later
414 */
415 udev = udev_new();
416 if (!udev) {
7b48d6e1 417 sr_err("mso19: Failed to initialize udev.");
01cf8814
DR
418 goto ret;
419 }
420 enumerate = udev_enumerate_new(udev);
421 udev_enumerate_add_match_subsystem(enumerate, "usb-serial");
422 udev_enumerate_scan_devices(enumerate);
bb7ef793
UH
423 devs = udev_enumerate_get_list_entry(enumerate);
424 udev_list_entry_foreach(dev_list_entry, devs) {
01cf8814
DR
425 const char *syspath, *sysname, *idVendor, *idProduct,
426 *iSerial, *iProduct;
427 char path[32], manufacturer[32], product[32], hwrev[32];
428 struct udev_device *dev, *parent;
429 size_t s;
430
431 syspath = udev_list_entry_get_name(dev_list_entry);
432 dev = udev_device_new_from_syspath(udev, syspath);
433 sysname = udev_device_get_sysname(dev);
434 parent = udev_device_get_parent_with_subsystem_devtype(
435 dev, "usb", "usb_device");
436 if (!parent) {
7b48d6e1 437 sr_err("mso19: Unable to find parent usb device for %s",
133a37bf 438 sysname);
01cf8814
DR
439 continue;
440 }
441
442 idVendor = udev_device_get_sysattr_value(parent, "idVendor");
443 idProduct = udev_device_get_sysattr_value(parent, "idProduct");
444 if (strcmp(USB_VENDOR, idVendor)
445 || strcmp(USB_PRODUCT, idProduct))
446 continue;
447
448 iSerial = udev_device_get_sysattr_value(parent, "serial");
449 iProduct = udev_device_get_sysattr_value(parent, "product");
450
451 snprintf(path, sizeof(path), "/dev/%s", sysname);
452
453 s = strcspn(iProduct, " ");
454 if (s > sizeof(product) ||
455 strlen(iProduct) - s > sizeof(manufacturer)) {
7b48d6e1 456 sr_err("mso19: Could not parse iProduct: %s", iProduct);
01cf8814
DR
457 continue;
458 }
459 strncpy(product, iProduct, s);
460 product[s] = 0;
461 strcpy(manufacturer, iProduct + s);
01cf8814 462
ea9cfed7
UH
463 if (!(ctx = g_try_malloc0(sizeof(struct context)))) {
464 sr_err("mso19: %s: ctx malloc failed", __func__);
ecad043f
UH
465 continue; /* TODO: Errors handled correctly? */
466 }
01cf8814 467
ea9cfed7 468 if (mso_parse_serial(iSerial, iProduct, ctx) != SR_OK) {
7b48d6e1 469 sr_err("mso19: Invalid iSerial: %s", iSerial);
ea9cfed7 470 goto err_free_ctx;
01cf8814 471 }
ea9cfed7 472 sprintf(hwrev, "r%d", ctx->hwrev);
a2936073 473
01cf8814 474 /* hardware initial state */
ea9cfed7 475 ctx->ctlbase1 = 0;
a2936073
RC
476 {
477 /* Initialize the protocol trigger configuration */
478 int i;
7b48d6e1 479 for (i = 0; i < 4; i++) {
ea9cfed7
UH
480 ctx->protocol_trigger.word[i] = 0;
481 ctx->protocol_trigger.mask[i] = 0xff;
a2936073 482 }
ea9cfed7 483 ctx->protocol_trigger.spimode = 0;
a2936073 484 }
01cf8814 485
d3683c42 486 sdi = sr_dev_inst_new(devcnt, SR_ST_INITIALIZING,
7b48d6e1 487 manufacturer, product, hwrev);
01cf8814 488 if (!sdi) {
7b48d6e1 489 sr_err("mso19: Unable to create device instance for %s",
133a37bf 490 sysname);
ea9cfed7 491 goto err_free_ctx;
01cf8814
DR
492 }
493
494 /* save a pointer to our private instance data */
ea9cfed7 495 sdi->priv = ctx;
01cf8814 496
d3683c42 497 sdi->serial = sr_serial_dev_inst_new(path, -1);
01cf8814 498 if (!sdi->serial)
d68e2d1a 499 goto err_dev_inst_free;
01cf8814 500
d68e2d1a 501 dev_insts = g_slist_append(dev_insts, sdi);
01cf8814
DR
502 devcnt++;
503 continue;
504
d68e2d1a 505err_dev_inst_free:
d3683c42 506 sr_dev_inst_free(sdi);
ea9cfed7
UH
507err_free_ctx:
508 g_free(ctx);
01cf8814
DR
509 }
510
511 udev_enumerate_unref(enumerate);
512 udev_unref(udev);
513
514ret:
515 return devcnt;
516}
517
57ab7d9f 518static int hw_cleanup(void)
01cf8814
DR
519{
520 GSList *l;
d68e2d1a 521 struct sr_dev_inst *sdi;
341ce415 522 int ret;
01cf8814 523
341ce415 524 ret = SR_OK;
01cf8814 525 /* Properly close all devices. */
d68e2d1a 526 for (l = dev_insts; l; l = l->next) {
57ab7d9f
UH
527 if (!(sdi = l->data)) {
528 /* Log error, but continue cleaning up the rest. */
529 sr_err("mso19: %s: sdi was NULL, continuing", __func__);
530 ret = SR_ERR_BUG;
531 continue;
532 }
01cf8814
DR
533 if (sdi->serial->fd != -1)
534 serial_close(sdi->serial->fd);
d3683c42 535 sr_dev_inst_free(sdi);
01cf8814 536 }
d68e2d1a
UH
537 g_slist_free(dev_insts);
538 dev_insts = NULL;
57ab7d9f 539
341ce415 540 return ret;
01cf8814
DR
541}
542
e7eb703f 543static int hw_dev_open(int dev_index)
01cf8814 544{
d68e2d1a 545 struct sr_dev_inst *sdi;
ea9cfed7 546 struct context *ctx;
e46b8fb1 547 int ret = SR_ERR;
01cf8814 548
bb7ef793 549 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
01cf8814
DR
550 return ret;
551
ea9cfed7 552 ctx = sdi->priv;
01cf8814
DR
553 sdi->serial->fd = serial_open(sdi->serial->port, O_RDWR);
554 if (sdi->serial->fd == -1)
555 return ret;
556
557 ret = serial_set_params(sdi->serial->fd, 460800, 8, 0, 1, 2);
e46b8fb1 558 if (ret != SR_OK)
01cf8814
DR
559 return ret;
560
5a2326a7 561 sdi->status = SR_ST_ACTIVE;
01cf8814
DR
562
563 /* FIXME: discard serial buffer */
564
ea9cfed7
UH
565 mso_check_trigger(sdi, &ctx->trigger_state);
566 sr_dbg("mso19: trigger state: 0x%x", ctx->trigger_state);
01cf8814
DR
567
568 ret = mso_reset_adc(sdi);
e46b8fb1 569 if (ret != SR_OK)
01cf8814
DR
570 return ret;
571
ea9cfed7
UH
572 mso_check_trigger(sdi, &ctx->trigger_state);
573 sr_dbg("mso19: trigger state: 0x%x", ctx->trigger_state);
01cf8814
DR
574
575// ret = mso_reset_fsm(sdi);
e46b8fb1 576// if (ret != SR_OK)
01cf8814
DR
577// return ret;
578
7b48d6e1 579 sr_dbg("mso19: Finished %s", __func__);
357285a9 580
e46b8fb1
UH
581// return SR_ERR;
582 return SR_OK;
01cf8814
DR
583}
584
e7eb703f 585static int hw_dev_close(int dev_index)
01cf8814 586{
d68e2d1a 587 struct sr_dev_inst *sdi;
01cf8814 588
bb7ef793 589 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
697785d1
UH
590 sr_err("mso19: %s: sdi was NULL", __func__);
591 return SR_ERR; /* TODO: SR_ERR_ARG? */
592 }
01cf8814 593
697785d1 594 /* TODO */
01cf8814
DR
595 if (sdi->serial->fd != -1) {
596 serial_close(sdi->serial->fd);
597 sdi->serial->fd = -1;
5a2326a7 598 sdi->status = SR_ST_INACTIVE;
01cf8814 599 }
697785d1 600
7b48d6e1 601 sr_dbg("mso19: finished %s", __func__);
697785d1 602 return SR_OK;
01cf8814
DR
603}
604
5097b0d0 605static void *hw_dev_info_get(int dev_index, int dev_info_id)
01cf8814 606{
d68e2d1a 607 struct sr_dev_inst *sdi;
ea9cfed7 608 struct context *ctx;
01cf8814
DR
609 void *info = NULL;
610
bb7ef793 611 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
01cf8814 612 return NULL;
ea9cfed7 613 ctx = sdi->priv;
01cf8814 614
bb7ef793 615 switch (dev_info_id) {
1d9a8a5f 616 case SR_DI_INST:
01cf8814
DR
617 info = sdi;
618 break;
5a2326a7 619 case SR_DI_NUM_PROBES: /* FIXME: How to report analog probe? */
464d12c7
KS
620 info = GINT_TO_POINTER(NUM_PROBES);
621 break;
622 case SR_DI_PROBE_NAMES:
623 info = probe_names;
01cf8814 624 break;
5a2326a7 625 case SR_DI_SAMPLERATES:
01cf8814
DR
626 info = &samplerates;
627 break;
5a2326a7 628 case SR_DI_TRIGGER_TYPES:
01cf8814
DR
629 info = "01"; /* FIXME */
630 break;
5a2326a7 631 case SR_DI_CUR_SAMPLERATE:
ea9cfed7 632 info = &ctx->cur_rate;
01cf8814
DR
633 break;
634 }
635 return info;
636}
637
e7eb703f 638static int hw_dev_status_get(int dev_index)
01cf8814 639{
d68e2d1a 640 struct sr_dev_inst *sdi;
01cf8814 641
bb7ef793 642 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
5a2326a7 643 return SR_ST_NOT_FOUND;
01cf8814
DR
644
645 return sdi->status;
646}
647
ffedd0bf 648static int *hw_hwcap_get_all(void)
01cf8814 649{
ffedd0bf 650 return hwcaps;
01cf8814
DR
651}
652
a9a245b4 653static int hw_dev_config_set(int dev_index, int hwcap, void *value)
01cf8814 654{
d68e2d1a 655 struct sr_dev_inst *sdi;
01cf8814 656
bb7ef793 657 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
e46b8fb1 658 return SR_ERR;
01cf8814 659
ffedd0bf 660 switch (hwcap) {
5a2326a7 661 case SR_HWCAP_SAMPLERATE:
01cf8814 662 return mso_configure_rate(sdi, *(uint64_t *) value);
5a2326a7
UH
663 case SR_HWCAP_PROBECONFIG:
664 case SR_HWCAP_LIMIT_SAMPLES:
01cf8814 665 default:
e46b8fb1 666 return SR_OK; /* FIXME */
01cf8814 667 }
01cf8814
DR
668}
669
670#define MSO_TRIGGER_UNKNOWN '!'
671#define MSO_TRIGGER_UNKNOWN1 '1'
672#define MSO_TRIGGER_UNKNOWN2 '2'
673#define MSO_TRIGGER_UNKNOWN3 '3'
674#define MSO_TRIGGER_WAIT '4'
675#define MSO_TRIGGER_FIRED '5'
676#define MSO_TRIGGER_DATAREADY '6'
677
678/* FIXME: Pass errors? */
679static int receive_data(int fd, int revents, void *user_data)
680{
d68e2d1a 681 struct sr_dev_inst *sdi = user_data;
ea9cfed7 682 struct context *ctx = sdi->priv;
b9c735a2 683 struct sr_datafeed_packet packet;
e42ef08d 684 struct sr_datafeed_logic logic;
01cf8814
DR
685 uint8_t in[1024], logic_out[1024];
686 double analog_out[1024];
687 size_t i, s;
688
689 revents = revents;
690
2119ab03 691 s = serial_read(fd, in, sizeof(in));
01cf8814
DR
692 if (s <= 0)
693 return FALSE;
694
695 /* No samples */
ea9cfed7
UH
696 if (ctx->trigger_state != MSO_TRIGGER_DATAREADY) {
697 ctx->trigger_state = in[0];
698 if (ctx->trigger_state == MSO_TRIGGER_DATAREADY) {
01cf8814 699 mso_read_buffer(sdi);
ea9cfed7 700 ctx->buffer_n = 0;
01cf8814
DR
701 } else {
702 mso_check_trigger(sdi, NULL);
703 }
704 return FALSE;
705 }
706
707 /* the hardware always dumps 1024 samples, 24bits each */
ea9cfed7
UH
708 if (ctx->buffer_n < 3072) {
709 memcpy(ctx->buffer + ctx->buffer_n, in, s);
710 ctx->buffer_n += s;
01cf8814 711 }
ea9cfed7 712 if (ctx->buffer_n < 3072)
01cf8814
DR
713 return FALSE;
714
715 /* do the conversion */
716 for (i = 0; i < 1024; i++) {
717 /* FIXME: Need to do conversion to mV */
ea9cfed7
UH
718 analog_out[i] = (ctx->buffer[i * 3] & 0x3f) |
719 ((ctx->buffer[i * 3 + 1] & 0xf) << 6);
720 logic_out[i] = ((ctx->buffer[i * 3 + 1] & 0x30) >> 4) |
721 ((ctx->buffer[i * 3 + 2] & 0x3f) << 2);
01cf8814
DR
722 }
723
5a2326a7 724 packet.type = SR_DF_LOGIC;
42eb54fb 725 packet.payload = &logic;
e42ef08d
RC
726 logic.length = 1024;
727 logic.unitsize = 1;
728 logic.data = logic_out;
ea9cfed7 729 sr_session_bus(ctx->session_id, &packet);
01cf8814 730
42eb54fb
UH
731 // Dont bother fixing this yet, keep it "old style"
732 /*
5a2326a7 733 packet.type = SR_DF_ANALOG;
01cf8814
DR
734 packet.length = 1024;
735 packet.unitsize = sizeof(double);
736 packet.payload = analog_out;
ea9cfed7 737 sr_session_bus(ctx->session_id, &packet);
42eb54fb 738 */
01cf8814 739
5a2326a7 740 packet.type = SR_DF_END;
ea9cfed7 741 sr_session_bus(ctx->session_id, &packet);
01cf8814
DR
742
743 return TRUE;
744}
745
69040b7c 746static int hw_dev_acquisition_start(int dev_index, gpointer session_dev_id)
01cf8814 747{
d68e2d1a 748 struct sr_dev_inst *sdi;
ea9cfed7 749 struct context *ctx;
b9c735a2
UH
750 struct sr_datafeed_packet packet;
751 struct sr_datafeed_header header;
e46b8fb1 752 int ret = SR_ERR;
01cf8814 753
bb7ef793 754 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
01cf8814 755 return ret;
ea9cfed7 756 ctx = sdi->priv;
01cf8814
DR
757
758 /* FIXME: No need to do full reconfigure every time */
759// ret = mso_reset_fsm(sdi);
e46b8fb1 760// if (ret != SR_OK)
01cf8814
DR
761// return ret;
762
763 /* FIXME: ACDC Mode */
ea9cfed7
UH
764 ctx->ctlbase1 &= 0x7f;
765// ctx->ctlbase1 |= ctx->acdcmode;
01cf8814 766
ea9cfed7 767 ret = mso_configure_rate(sdi, ctx->cur_rate);
e46b8fb1 768 if (ret != SR_OK)
01cf8814
DR
769 return ret;
770
771 /* set dac offset */
ea9cfed7 772 ret = mso_dac_out(sdi, ctx->dac_offset);
e46b8fb1 773 if (ret != SR_OK)
01cf8814
DR
774 return ret;
775
776 ret = mso_configure_threshold_level(sdi);
e46b8fb1 777 if (ret != SR_OK)
01cf8814
DR
778 return ret;
779
780 ret = mso_configure_trigger(sdi);
e46b8fb1 781 if (ret != SR_OK)
01cf8814
DR
782 return ret;
783
784 /* FIXME: trigger_position */
785
786
787 /* END of config hardware part */
788
789 /* with trigger */
790 ret = mso_arm(sdi);
e46b8fb1 791 if (ret != SR_OK)
01cf8814
DR
792 return ret;
793
794 /* without trigger */
795// ret = mso_force_capture(sdi);
e46b8fb1 796// if (ret != SR_OK)
01cf8814
DR
797// return ret;
798
ea9cfed7 799 mso_check_trigger(sdi, &ctx->trigger_state);
01cf8814 800 ret = mso_check_trigger(sdi, NULL);
e46b8fb1 801 if (ret != SR_OK)
01cf8814
DR
802 return ret;
803
ea9cfed7 804 ctx->session_id = session_dev_id;
6f1be0a2 805 sr_source_add(sdi->serial->fd, G_IO_IN, -1, receive_data, sdi);
01cf8814 806
5a2326a7 807 packet.type = SR_DF_HEADER;
01cf8814
DR
808 packet.payload = (unsigned char *) &header;
809 header.feed_version = 1;
810 gettimeofday(&header.starttime, NULL);
ea9cfed7 811 header.samplerate = ctx->cur_rate;
5c64390e 812 // header.num_analog_probes = 1;
01cf8814 813 header.num_logic_probes = 8;
bb7ef793 814 sr_session_bus(session_dev_id, &packet);
01cf8814
DR
815
816 return ret;
817}
818
819/* FIXME */
69040b7c 820static int hw_dev_acquisition_stop(int dev_index, gpointer session_dev_id)
01cf8814 821{
b9c735a2 822 struct sr_datafeed_packet packet;
01cf8814 823
bb7ef793 824 dev_index = dev_index;
01cf8814 825
5a2326a7 826 packet.type = SR_DF_END;
bb7ef793 827 sr_session_bus(session_dev_id, &packet);
3010f21c
UH
828
829 return SR_OK;
01cf8814
DR
830}
831
bb7ef793 832SR_PRIV struct sr_dev_plugin link_mso19_plugin_info = {
01cf8814 833 .name = "link-mso19",
9f8274a5 834 .longname = "Link Instruments MSO-19",
01cf8814
DR
835 .api_version = 1,
836 .init = hw_init,
837 .cleanup = hw_cleanup,
e7eb703f
UH
838 .dev_open = hw_dev_open,
839 .dev_close = hw_dev_close,
5097b0d0 840 .dev_info_get = hw_dev_info_get,
e7eb703f 841 .dev_status_get = hw_dev_status_get,
ffedd0bf 842 .hwcap_get_all = hw_hwcap_get_all,
a9a245b4 843 .dev_config_set = hw_dev_config_set,
69040b7c
UH
844 .dev_acquisition_start = hw_dev_acquisition_start,
845 .dev_acquisition_stop = hw_dev_acquisition_stop,
01cf8814 846};