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3b533202 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
3b533202 BV |
3 | * |
4 | * Copyright (C) 2012 Bert Vermeulen <bert@biot.com> | |
5 | * With protocol information from the hantekdso project, | |
6 | * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H | |
23 | #define LIBSIGROK_HARDWARE_HANTEK_DSO_H | |
24 | ||
29a27196 UH |
25 | /* Message logging helpers with subsystem-specific prefix string. */ |
26 | #define LOG_PREFIX "hantek-dso: " | |
27 | #define sr_log(l, s, args...) sr_log(l, LOG_PREFIX s, ## args) | |
28 | #define sr_spew(s, args...) sr_spew(LOG_PREFIX s, ## args) | |
29 | #define sr_dbg(s, args...) sr_dbg(LOG_PREFIX s, ## args) | |
30 | #define sr_info(s, args...) sr_info(LOG_PREFIX s, ## args) | |
31 | #define sr_warn(s, args...) sr_warn(LOG_PREFIX s, ## args) | |
32 | #define sr_err(s, args...) sr_err(LOG_PREFIX s, ## args) | |
cbc6f3b2 | 33 | |
8c971b6e BV |
34 | #define USB_INTERFACE 0 |
35 | #define USB_CONFIGURATION 1 | |
36 | #define DSO_EP_IN 0x86 | |
37 | #define DSO_EP_OUT 0x02 | |
3b533202 BV |
38 | |
39 | /* FX2 renumeration delay in ms */ | |
8c971b6e | 40 | #define MAX_RENUM_DELAY_MS 3000 |
3b533202 | 41 | |
8c971b6e | 42 | #define MAX_CAPTURE_EMPTY 3 |
3b533202 | 43 | |
8c971b6e BV |
44 | #define DEFAULT_VOLTAGE VDIV_500MV |
45 | #define DEFAULT_FRAMESIZE FRAMESIZE_SMALL | |
46 | #define DEFAULT_TIMEBASE TIME_100us | |
47 | #define DEFAULT_TRIGGER_SOURCE "CH1" | |
48 | #define DEFAULT_COUPLING COUPLING_DC | |
49 | #define DEFAULT_HORIZ_TRIGGERPOS 0.5 | |
50 | #define DEFAULT_VERT_OFFSET 0.5 | |
51 | #define DEFAULT_VERT_TRIGGERPOS 0.5 | |
3b533202 | 52 | |
8c971b6e | 53 | #define MAX_VERT_TRIGGER 0xfe |
3b533202 BV |
54 | |
55 | /* Hantek DSO-specific protocol values */ | |
8c971b6e | 56 | #define EEPROM_CHANNEL_OFFSETS 0x08 |
3b533202 | 57 | |
034accb5 | 58 | /* All models have this for their "fast" mode. */ |
8c971b6e | 59 | #define FRAMESIZE_SMALL 10240 |
3b533202 BV |
60 | |
61 | enum control_requests { | |
62 | CTRL_READ_EEPROM = 0xa2, | |
63 | CTRL_GETSPEED = 0xb2, | |
64 | CTRL_BEGINCOMMAND = 0xb3, | |
65 | CTRL_SETOFFSET = 0xb4, | |
e98b7f1b | 66 | CTRL_SETRELAYS = 0xb5, |
3b533202 BV |
67 | }; |
68 | ||
69 | enum dso_commands { | |
70 | CMD_SET_FILTERS = 0, | |
71 | CMD_SET_TRIGGER_SAMPLERATE, | |
72 | CMD_FORCE_TRIGGER, | |
73 | CMD_CAPTURE_START, | |
74 | CMD_ENABLE_TRIGGER, | |
75 | CMD_GET_CHANNELDATA, | |
76 | CMD_GET_CAPTURESTATE, | |
77 | CMD_SET_VOLTAGE, | |
313deed2 | 78 | /* unused */ |
3b533202 | 79 | cmdSetLogicalData, |
e98b7f1b | 80 | cmdGetLogicalData, |
3b533202 BV |
81 | }; |
82 | ||
b58fbd99 | 83 | /* Must match the coupling table. */ |
3b533202 BV |
84 | enum couplings { |
85 | COUPLING_AC = 0, | |
86 | COUPLING_DC, | |
2715c0b8 | 87 | /* TODO not used, how to enable? */ |
e98b7f1b | 88 | COUPLING_GND, |
3b533202 BV |
89 | }; |
90 | ||
b58fbd99 | 91 | /* Must match the timebases table. */ |
3b533202 BV |
92 | enum time_bases { |
93 | TIME_10us = 0, | |
94 | TIME_20us, | |
95 | TIME_40us, | |
96 | TIME_100us, | |
97 | TIME_200us, | |
98 | TIME_400us, | |
99 | TIME_1ms, | |
100 | TIME_2ms, | |
101 | TIME_4ms, | |
102 | TIME_10ms, | |
103 | TIME_20ms, | |
104 | TIME_40ms, | |
105 | TIME_100ms, | |
106 | TIME_200ms, | |
e98b7f1b | 107 | TIME_400ms, |
3b533202 BV |
108 | }; |
109 | ||
b58fbd99 | 110 | /* Must match the vdivs table. */ |
313deed2 BV |
111 | enum { |
112 | VDIV_10MV, | |
113 | VDIV_20MV, | |
114 | VDIV_50MV, | |
115 | VDIV_100MV, | |
116 | VDIV_200MV, | |
117 | VDIV_500MV, | |
118 | VDIV_1V, | |
119 | VDIV_2V, | |
120 | VDIV_5V, | |
121 | }; | |
122 | ||
3b533202 BV |
123 | enum trigger_slopes { |
124 | SLOPE_POSITIVE = 0, | |
e98b7f1b | 125 | SLOPE_NEGATIVE, |
3b533202 BV |
126 | }; |
127 | ||
128 | enum trigger_sources { | |
129 | TRIGGER_CH2 = 0, | |
130 | TRIGGER_CH1, | |
3b533202 | 131 | TRIGGER_EXT, |
3b533202 BV |
132 | }; |
133 | ||
3b533202 BV |
134 | enum capturestates { |
135 | CAPTURE_EMPTY = 0, | |
136 | CAPTURE_FILLING = 1, | |
137 | CAPTURE_READY_8BIT = 2, | |
138 | CAPTURE_READY_9BIT = 7, | |
139 | CAPTURE_TIMEOUT = 127, | |
e98b7f1b | 140 | CAPTURE_UNKNOWN = 255, |
3b533202 BV |
141 | }; |
142 | ||
143 | enum triggermodes { | |
144 | TRIGGERMODE_AUTO, | |
145 | TRIGGERMODE_NORMAL, | |
e98b7f1b | 146 | TRIGGERMODE_SINGLE, |
3b533202 BV |
147 | }; |
148 | ||
149 | enum states { | |
150 | IDLE, | |
151 | NEW_CAPTURE, | |
152 | CAPTURE, | |
a3508e33 BV |
153 | FETCH_DATA, |
154 | STOPPING, | |
3b533202 BV |
155 | }; |
156 | ||
157 | struct dso_profile { | |
158 | /* VID/PID after cold boot */ | |
159 | uint16_t orig_vid; | |
160 | uint16_t orig_pid; | |
161 | /* VID/PID after firmware upload */ | |
162 | uint16_t fw_vid; | |
163 | uint16_t fw_pid; | |
164 | char *vendor; | |
165 | char *model; | |
034accb5 | 166 | const uint64_t *buffersizes; |
3b533202 BV |
167 | char *firmware; |
168 | }; | |
169 | ||
269971dd | 170 | struct dev_context { |
62bb8840 | 171 | const struct dso_profile *profile; |
3b533202 | 172 | void *cb_data; |
ae88b97b BV |
173 | uint64_t limit_frames; |
174 | uint64_t num_frames; | |
69e19dd7 | 175 | GSList *enabled_probes; |
3b533202 BV |
176 | /* We can't keep track of an FX2-based device after upgrading |
177 | * the firmware (it re-enumerates into a different device address | |
178 | * after the upgrade) this is like a global lock. No device will open | |
179 | * until a proper delay after the last device was upgraded. | |
180 | */ | |
fc8fe3e3 | 181 | int64_t fw_updated; |
3b533202 BV |
182 | int epin_maxpacketsize; |
183 | int capture_empty_count; | |
3b533202 BV |
184 | int dev_state; |
185 | ||
e749a8cb | 186 | /* Oscilloscope settings. */ |
3b533202 BV |
187 | int timebase; |
188 | gboolean ch1_enabled; | |
189 | gboolean ch2_enabled; | |
190 | int voltage_ch1; | |
191 | int voltage_ch2; | |
192 | int coupling_ch1; | |
193 | int coupling_ch2; | |
194 | // voltage offset (vertical position) | |
195 | float voffset_ch1; | |
196 | float voffset_ch2; | |
197 | float voffset_trigger; | |
198 | uint16_t channel_levels[2][9][2]; | |
e749a8cb | 199 | unsigned int framesize; |
3b533202 BV |
200 | gboolean filter_ch1; |
201 | gboolean filter_ch2; | |
202 | gboolean filter_trigger; | |
203 | int triggerslope; | |
a370ef19 | 204 | char *triggersource; |
bc79e906 | 205 | float triggerposition; |
3b533202 | 206 | int triggermode; |
e749a8cb BV |
207 | |
208 | /* Frame transfer */ | |
209 | unsigned int samp_received; | |
210 | unsigned int samp_buffered; | |
211 | unsigned int trigger_offset; | |
212 | unsigned char *framebuf; | |
3b533202 BV |
213 | }; |
214 | ||
25a0f108 | 215 | SR_PRIV int dso_open(struct sr_dev_inst *sdi); |
3b533202 | 216 | SR_PRIV void dso_close(struct sr_dev_inst *sdi); |
c118080b BV |
217 | SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi); |
218 | SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi); | |
219 | SR_PRIV int dso_init(const struct sr_dev_inst *sdi); | |
220 | SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi, | |
e98b7f1b | 221 | uint8_t *capturestate, uint32_t *trigger_offset); |
c118080b | 222 | SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi); |
69e19dd7 | 223 | SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi, |
e98b7f1b | 224 | libusb_transfer_cb_fn cb); |
3b533202 BV |
225 | |
226 | #endif |